Summary

OpenTitan

Hardware

• Introduction

• Top Earlgrey

  • Datasheet
  • Design
  • Design Verification
  • Analog Sensor Top
  • Alert Handler
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Interrupt Controller
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Sensor Control
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • TL-UL Checklist
  • Pinmux Targets
    • ASIC Target Pinout and Pinmux Connectivity
    • CW310 Target Pinout and Pinmux Connectivity
    • NEXYSVIDEO Target Pinout and Pinmux Connectivity

• Cores

  • Ibex RISC-V Core Wrapper
    • Design Verification
    • Interface and Registers
    • Checklist
  • OTBN
    • Developer Guide
    • ISA Guide
    • Design Verification
      • Random Instruction Generator
        • Internals
        • Configuration
      • memutil wrapper
      • OTBN Simulation Software
      • Tracer
      • Formal Masking Verification Using Alma
    • Functional Coverage
    • Interface and Registers
    • Checklist

• Hardware IP Blocks

  • Analog to Digital Converter Control
    • Design Verification
      • Testplan
    • Checklist
    • Interface and Registers
  • AES
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • AON Timer
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Clock Manager
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • CSRNG
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • EDN
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Entropy Source
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Flash Controller
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • GPIO
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • HMAC
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • I2C
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Key Manager
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • KMAC
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Life Cycle Controller
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • OTP Controller
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Pattern Generator
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Pinmux
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Pulse Width Modulator
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Power Management
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • ROM Control
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Reset Manager
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • RISC-V Debug Manager
    • Design Verification
      • Testplan
    • Interface and Registers
    • Checklist
  • SPI Device
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • SPI Host
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • SRAM Controller
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • System Reset Controller
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • Timer
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • TL-UL Bus
    • Design Verification
      • Testplan
      • Protocol Checker
  • UART
    • Design Verification
      • Testplan
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • USB 2.0
    • Design Verification
      • Testplan
    • Suspending and Resuming
    • Interface and Registers
    • Device Interface Functions
    • Checklist
  • lowRISC Hardware Primitives
    • Two Input Clock
    • Flash Wrapper
    • Keccak Permutation
    • Linear Feedback Shift Register
    • Packer
    • Packer FIFO
    • Present Scrambler
    • Prince Scrambler
    • SRAM Scrambler
    • Pseudo Random Number Generator

• Common SystemVerilog and UVM Components

  • ALERT_ESC Agent
  • Bus Params Package
  • Comportable IP Testbench Architecture
  • Common Interfaces
  • CSR Utils
  • CSRNG Agent
  • DV Library Classes
  • DV Utils
  • FLASH_PHY_PRIM Agent
  • I2C Agent
  • JTAG Agent
  • JTAG DMI Agent
  • JTAG RISCV Agent
  • KEY_SIDELOAD Agent
  • KMAC_APP Agent
  • Memory Backdoor Scoreboard
  • Memory Backdoor Utility
  • Memory Model
  • PATTGEN Agent
  • PUSH_PULL Agent
  • PWM Monitor
  • RNG Agent
  • Scoreboard
  • Simulation SRAM
  • SPI Agent
  • String Utils
  • Test Vectors
  • Tile Link Agent
  • UART Agent
  • USB20 Agent

Software

• Introduction

• Build Software

• Device Software

  • Device Libraries
    • DIF Library
      • ADC Checklist
      • AES Checklist
      • Alert Handler Checklist
      • Always-On Timer Checklist
      • Clock Manager Checklist
      • CSRNG Checklist
      • EDN Checklist
      • Entropy Source Checklist
      • Flash Controller Checklist
      • GPIO Checklist
      • HMAC Checklist
      • I2C Checklist
      • Key Manager Checklist
      • KMAC Checklist
      • Lifecycle Checklist
      • OTBN Checklist
      • OTP Controller Checklist
      • Pattern Generator Checklist
      • Pin Multiplexer Checklist
      • PWM Checklist
      • Power Manager Checklist
      • ROM Checklist
      • Reset Manager Checklist
      • RV Core Ibex Checklist
      • PLIC Checklist
      • RV Timer Checklist
      • Sensor Controller Checklist
      • SPI Device Checklist
      • SPI Host Checklist
      • SRAM Controller Checklist
      • System Reset Controller Checklist
      • UART Checklist
      • USB Checklist
    • Top-Level Test Libraries
      • On-Device Test Framework
    • OpenTitan Standard Library
      • Freestanding C Headers
  • Silicon Creator Software
    • Manufacturing Firmware
    • ROM
      • Memory Protection
      • Signing Keys
    • Manifest Format
  • Top-Level Tests
    • Manufacturer Test Hooks
    • Crypto Library Tests

• Host Software

Tooling

• Tools Overview

• Design-Related Tooling

• dvsim: Testplanner

• fpvgen: Initial FPV Testbench Generation

• reggen & regtool: Register Generator

  • Setup and use of regtool

• ralgen: FuseSoC UVM RAL Generator

• uvmdvgen: Initial Testbench Auto-generation

• tlgen: Crossbar Generation

• ipgen: Generate IP Blocks from IP Templates

• topgen: Top Generator

• vendor: Vendoring In Tool

• i2csvg: Generate SVGs of I2C Commands

Contributing

• Contributing

  • Detailed Contribution Guide
  • Directory Structure
  • Continueous Intergration
  • Top-Level Design and Targets
  • GitHub Notes
  • Bazel Notes
  • Using the Container

• Contributing to Hardware

  • Comportability
  • Hardware Design
  • Design Methodology
  • Vendoring in Hardware
  • Linting
  • Synthesis Flow

• Contributing to Verification

  • Verification Methodology
  • Security Countermeasure Verification Framework
  • Assertions

• Contributing to Software

  • Device Interface Functions
  • Writing and Building Software for OTBN

• Style Guides

  • HJSON
  • Python
  • C & C++
  • Markdown
  • RISC-V Assembly
  • OTBN Assembly
  • Guidance for Volatile

• Developing on an FPGA

  • Get a Board
  • FPGA Reference Manual

Project Governance

• Introduction
• Committers
• RFC Process
• Generalized Priority Definitions
• OpenTitan Technical Committee
• Hardware Development Stages
• Signoff Checklist

Security

• Security

• Implementation Guidelines

  • Secure Hardware Design Guidelines

• Logical Security Model

• Security Model Specification

  • Device Attestation
  • Device Life Cycle
  • Device Provisioning
  • Firmware Update
  • Identities and Root Keys
  • Ownership Transfer
  • Secure Boot

• Lightweight Threat Model

Use Cases

• Use Cases
• Platform Integrity Module
• Trusted Platform Module
• Universal 2nd-Factor Security Key

Rust for C Developers

• Rust for Embedded C Programmers