| commit | 8fc01c602dc4f5d2c2b6d45f263c7b3505a04040 | [log] [tgz] |
|---|---|---|
| author | Cindy Liu <hcindyl@google.com> | Wed Jan 26 20:36:01 2022 -0800 |
| committer | Cindy Liu <hcindyl@google.com> | Wed Jan 26 20:36:01 2022 -0800 |
| tree | 39ca383de242becfbbd3526d765c5060cc601404 | |
| parent | eac8e53421f81bb8752197961d4eeaf5eb42af51 [diff] |
sw:vec_iree: Use explicit zvl and zve ISA set to generate vector ops
Explicitly set zvl512b to support "--riscv-v-vector-bits-min=512",
and zve32x to support "--riscv-v-fixed-length-vector-elen-max=32" for
integer {8, 16, 32} types. By using these ISA set instead of the
top-level "v", we can ensure the compiler doesn't generate "vfxx" ops,
even when processing float models.
See https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-extensions
Change-Id: I5370bc17b70fc10514145fa1a42688ef5cfffbbf