sw:vec_iree: Use explicit zvl and zve ISA set to generate vector ops

Explicitly set zvl512b to support "--riscv-v-vector-bits-min=512",
and zve32x to support "--riscv-v-fixed-length-vector-elen-max=32" for
integer {8, 16, 32} types. By using these ISA set instead of the
top-level "v", we can ensure the compiler doesn't generate "vfxx" ops,
even when processing float models.

See https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-extensions

Change-Id: I5370bc17b70fc10514145fa1a42688ef5cfffbbf
diff --git a/cmake/riscv_iree.cmake b/cmake/riscv_iree.cmake
index f00f184..36b08d1 100644
--- a/cmake/riscv_iree.cmake
+++ b/cmake/riscv_iree.cmake
@@ -48,7 +48,7 @@
   set(CMAKE_C_STANDARD 11)
   set(CMAKE_C_EXTENSIONS OFF)     # Force the usage of _ISOC11_SOURCE
   set(CMAKE_SYSTEM_LIBRARY_PATH "${RISCV_TOOLCHAIN_ROOT}/riscv32-unknown-elf/lib")
-  set(RISCV_COMPILER_FLAGS "${RISCV_COMPILER_FLAGS} -menable-experimental-extensions -march=rv32imfv1p0 -mabi=ilp32")
+  set(RISCV_COMPILER_FLAGS "${RISCV_COMPILER_FLAGS} -menable-experimental-extensions -march=rv32imf_zvl512b_zve32x -mabi=ilp32")
 endif()
 
 set(CMAKE_C_FLAGS             "${RISCV_COMPILER_FLAGS} ${CMAKE_C_FLAGS}")
diff --git a/cmake/springbok_bytecode_module.cmake b/cmake/springbok_bytecode_module.cmake
index 11aef33..8e8e7f5 100644
--- a/cmake/springbok_bytecode_module.cmake
+++ b/cmake/springbok_bytecode_module.cmake
@@ -77,7 +77,7 @@
       "-iree-hal-target-backends=dylib-llvm-aot"
       "-iree-llvm-target-triple=riscv32-pc-linux-elf"
       "-iree-llvm-target-cpu=generic-rv32"
-      "-iree-llvm-target-cpu-features=+m,+f,+v"
+      "-iree-llvm-target-cpu-features=+m,+f,+zvl512b,+zve32x"
       "-iree-llvm-target-abi=ilp32"
       "-iree-llvm-link-embedded=true"
       "-iree-llvm-debug-symbols=false"
diff --git a/cmake/springbok_c_module.cmake b/cmake/springbok_c_module.cmake
index 1b86eb7..381c048 100644
--- a/cmake/springbok_c_module.cmake
+++ b/cmake/springbok_c_module.cmake
@@ -87,7 +87,7 @@
   list(APPEND _TRANSLATE_ARGS "-iree-hal-target-backends=dylib-llvm-aot")
   list(APPEND _TRANSLATE_ARGS "-iree-llvm-target-triple=riscv32-pc-linux-elf")
   list(APPEND _TRANSLATE_ARGS "-iree-llvm-target-cpu=generic-rv32")
-  list(APPEND _TRANSLATE_ARGS "-iree-llvm-target-cpu-features=+m,+f,+v")
+  list(APPEND _TRANSLATE_ARGS "-iree-llvm-target-cpu-features=+m,+f,+zvl512b,+zve32x")
   list(APPEND _TRANSLATE_ARGS "-iree-llvm-target-abi=ilp32")
   list(APPEND _TRANSLATE_ARGS "-iree-llvm-link-embedded=false")
   list(APPEND _TRANSLATE_ARGS "-iree-llvm-link-static")