)]}'
{
  "commit": "8fc01c602dc4f5d2c2b6d45f263c7b3505a04040",
  "tree": "39ca383de242becfbbd3526d765c5060cc601404",
  "parents": [
    "eac8e53421f81bb8752197961d4eeaf5eb42af51"
  ],
  "author": {
    "name": "Cindy Liu",
    "email": "hcindyl@google.com",
    "time": "Wed Jan 26 20:36:01 2022 -0800"
  },
  "committer": {
    "name": "Cindy Liu",
    "email": "hcindyl@google.com",
    "time": "Wed Jan 26 20:36:01 2022 -0800"
  },
  "message": "sw:vec_iree: Use explicit zvl and zve ISA set to generate vector ops\n\nExplicitly set zvl512b to support \"--riscv-v-vector-bits-min\u003d512\",\nand zve32x to support \"--riscv-v-fixed-length-vector-elen-max\u003d32\" for\ninteger {8, 16, 32} types. By using these ISA set instead of the\ntop-level \"v\", we can ensure the compiler doesn\u0027t generate \"vfxx\" ops,\neven when processing float models.\n\nSee https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-extensions\n\nChange-Id: I5370bc17b70fc10514145fa1a42688ef5cfffbbf\n",
  "tree_diff": [
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      "new_path": "cmake/riscv_iree.cmake"
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      "old_id": "11aef33e26ed718f49d136e99ae1e7be6c6572d3",
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      "old_path": "cmake/springbok_bytecode_module.cmake",
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      "new_mode": 33188,
      "new_path": "cmake/springbok_bytecode_module.cmake"
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    {
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}