Debug readability improvement

- In both Chisel and Python, define some enumerations for magic numbers
  we've had floating around.

Change-Id: I9ada036ab9be33f88bdcc606628ab3f9f0ed876f
diff --git a/hdl/chisel/src/kelvin/scalar/Debug.scala b/hdl/chisel/src/kelvin/scalar/Debug.scala
index 4b683cf..036645b 100644
--- a/hdl/chisel/src/kelvin/scalar/Debug.scala
+++ b/hdl/chisel/src/kelvin/scalar/Debug.scala
@@ -30,6 +30,20 @@
     val BUSY    = Value(3.U(2.W))
 }
 
+// See RISC-V Debug Specification v0.13.2
+object DebugModuleAddress {
+  def Data0       = 0x4.U(32.W)
+  def Dmcontrol   = 0x10.U(32.W)
+  def Dmstatus    = 0x11.U(32.W)
+  def Hartinfo    = 0x12.U(32.W)
+  def Abstractcs  = 0x16.U(32.W)
+  def Command     = 0x17.U(32.W)
+}
+
+object AccessRegisterCommand {
+  def Cmdtype   = 0.U(8.W)
+}
+
 class DebugModuleReqIO(p: Parameters) extends Bundle {
     val address = UInt(32.W)
     val data = UInt(32.W)
@@ -38,12 +52,12 @@
     def isRead: Bool = (op === DmReqOp.READ)
     def isWrite: Bool = (op === DmReqOp.WRITE)
     def isOp: Bool = op.isOneOf(DmReqOp.READ, DmReqOp.WRITE)
-    def isAddrData0: Bool = (address === 0x4.U)
-    def isAddrDmcontrol: Bool = (address === 0x10.U)
-    def isAddrDmstatus: Bool = (address === 0x11.U)
-    def isAddrHartinfo: Bool = (address === 0x12.U)
-    def isAddrAbstractcs: Bool = (address === 0x16.U)
-    def isAddrCommand: Bool = (address === 0x17.U)
+    def isAddrData0: Bool = (address === DebugModuleAddress.Data0)
+    def isAddrDmcontrol: Bool = (address === DebugModuleAddress.Dmcontrol)
+    def isAddrDmstatus: Bool = (address === DebugModuleAddress.Dmstatus)
+    def isAddrHartinfo: Bool = (address === DebugModuleAddress.Hartinfo)
+    def isAddrAbstractcs: Bool = (address === DebugModuleAddress.Abstractcs)
+    def isAddrCommand: Bool = (address === DebugModuleAddress.Command)
     def cmdtype: UInt = data(31,24)
     def write: Bool = data(16)
     def regno: UInt = data(15,0)
@@ -144,7 +158,7 @@
     )
 
     val abstractCmdValid = req.valid && req.bits.isWrite && req.bits.isAddrCommand
-    val cmdtypeIsAccessRegister = (req.bits.cmdtype === 0.U(8.W))
+    val cmdtypeIsAccessRegister = (req.bits.cmdtype === AccessRegisterCommand.Cmdtype)
     val regnoIsCsr = (req.bits.regno >= 0.U(16.W)) && (req.bits.regno < "x1000".U(16.W))
     val regnoIsScalar = (req.bits.regno >= "x1000".U(16.W)) && (req.bits.regno < "x1020".U(16.W))
     val regnoIsFloat = (req.bits.regno >= "x1020".U(16.W) && (req.bits.regno < "x1040".U(16.W)))
@@ -188,17 +202,17 @@
     )
 
     val scalarRegno = req.bits.regno(4,0)
-    io.scalar_rd.valid := io.halted(0) && abstractCmdValid && (req.bits.cmdtype === 0.U(8.W)) && regnoIsScalar && req.bits.write
+    io.scalar_rd.valid := io.halted(0) && abstractCmdValid && (req.bits.cmdtype === AccessRegisterCommand.Cmdtype) && regnoIsScalar && req.bits.write
     io.scalar_rd.bits.addr := scalarRegno
     io.scalar_rd.bits.data := data0
-    io.scalar_rs.idx := MuxOR(io.halted(0) && abstractCmdValid && (req.bits.cmdtype === 0.U(8.W)) && regnoIsScalar && !req.bits.write, scalarRegno)
+    io.scalar_rs.idx := MuxOR(io.halted(0) && abstractCmdValid && (req.bits.cmdtype === AccessRegisterCommand.Cmdtype) && regnoIsScalar && !req.bits.write, scalarRegno)
 
     if (p.enableFloat) {
         val floatRegno = req.bits.regno(4,0)
-        io.float_rd.get.valid := io.halted(0) && abstractCmdValid && (req.bits.cmdtype === 0.U(8.W)) && regnoIsFloat && req.bits.write
+        io.float_rd.get.valid := io.halted(0) && abstractCmdValid && (req.bits.cmdtype === AccessRegisterCommand.Cmdtype) && regnoIsFloat && req.bits.write
         io.float_rd.get.addr := floatRegno
         io.float_rd.get.data := Fp32.fromWord(data0)
-        io.float_rs.get.valid := io.halted(0) && abstractCmdValid && (req.bits.cmdtype === 0.U(8.W)) && regnoIsFloat && !req.bits.write
+        io.float_rs.get.valid := io.halted(0) && abstractCmdValid && (req.bits.cmdtype === AccessRegisterCommand.Cmdtype) && regnoIsFloat && !req.bits.write
         io.float_rs.get.addr := floatRegno
     }
 
@@ -234,4 +248,4 @@
     rsp.valid := req.valid && (!abstractCmdValid || abstractCmdComplete)
     req.ready := rsp.ready && (!abstractCmdValid || abstractCmdComplete)
     io.ext.rsp <> Queue(rsp, 1)
-}
\ No newline at end of file
+}
diff --git a/kelvin_test_utils/core_mini_axi_interface.py b/kelvin_test_utils/core_mini_axi_interface.py
index f567e11..ab184d5 100644
--- a/kelvin_test_utils/core_mini_axi_interface.py
+++ b/kelvin_test_utils/core_mini_axi_interface.py
@@ -58,6 +58,16 @@
   ACCESS_MEMORY = 2
 
 
+# See RISC-V Debug Specification v0.13.2
+class DmAddress:
+  DATA0       = 0x04
+  DMCONTROL   = 0x10
+  DMSTATUS    = 0x11
+  HARTINFO    = 0x12
+  ABSTRACTCS  = 0x16
+  COMMAND     = 0x17
+
+
 def format_line_from_word(word, addr):
   shift = addr % 16
   line = np.zeros([4], dtype=np.uint32)
@@ -456,34 +466,34 @@
 
   async def dm_read_reg(self, addr, expected_op=DmRspOp.SUCCESS):
     command = ((DmCmdType.ACCESS_REGISTER << 24) & 0xFF) | (((2 << 20) | (1 << 17) | (addr)) & 0xFFFFFF)
-    rsp = await self.dm_write(0x17, command)
+    rsp = await self.dm_write(DmAddress.COMMAND, command)
     assert rsp["op"] == expected_op
     if rsp["op"] != DmRspOp.SUCCESS:
         return 0
 
-    data = await self.dm_read(0x04)
-    status = await self.dm_read(0x16)
+    data = await self.dm_read(DmAddress.DATA0)
+    status = await self.dm_read(DmAddress.ABSTRACTCS)
     cmderr = (status >> 8) & 0b111
     assert (cmderr == 0)
     return data
 
   async def dm_write_reg(self, addr, data):
-    rsp = await self.dm_write(0x04, data)
+    rsp = await self.dm_write(DmAddress.DATA0, data)
     assert rsp["op"] == DmRspOp.SUCCESS
     command = ((DmCmdType.ACCESS_REGISTER << 24) & 0xFF) | (((2 << 20) | (1 << 17) | (1 << 16) | addr) & 0xFFFFFF)
-    rsp = await self.dm_write(0x17, command)
+    rsp = await self.dm_write(DmAddress.COMMAND, command)
     assert rsp["op"] == DmRspOp.SUCCESS
-    status = await self.dm_read(0x16)
+    status = await self.dm_read(DmAddress.ABSTRACTCS)
     cmderr = (status >> 8) & 0b111
     assert (cmderr == 0)
 
   async def dm_request_halt(self):
-    dmcontrol = await self.dm_read(0x10)
+    dmcontrol = await self.dm_read(DmAddress.DMCONTROL)
     dmcontrol = dmcontrol | (1 << 31) & ~(1 << 30)
-    return await self.dm_write(0x10, dmcontrol)
+    return await self.dm_write(DmAddress.DMCONTROL, dmcontrol)
 
   async def dm_check_for_halted(self):
-        dmstatus = await self.dm_read(0x11)
+        dmstatus = await self.dm_read(DmAddress.DMSTATUS)
         allhalted = dmstatus & (1 << 9)
         anyhalted = dmstatus & (1 << 8)
         if allhalted and anyhalted:
@@ -493,7 +503,7 @@
   async def dm_wait_for_halted(self, retry_count=100):
     retries = 0
     while True:
-        dmstatus = await self.dm_read(0x11)
+        dmstatus = await self.dm_read(DmAddress.DMSTATUS)
         allhalted = dmstatus & (1 << 9)
         anyhalted = dmstatus & (1 << 8)
         if allhalted and anyhalted:
@@ -502,14 +512,14 @@
         assert retries < retry_count
 
   async def dm_request_resume(self):
-    dmcontrol = await self.dm_read(0x10)
+    dmcontrol = await self.dm_read(DmAddress.DMCONTROL)
     dmcontrol = dmcontrol | (1 << 30) & ~(1 << 31)
-    await self.dm_write(0x10, dmcontrol)
+    await self.dm_write(DmAddress.DMCONTROL, dmcontrol)
 
   async def dm_wait_for_resumed(self, retry_count=100):
     retries = 0
     while True:
-        dmstatus = await self.dm_read(0x11)
+        dmstatus = await self.dm_read(DmAddress.DMSTATUS)
         allrunning = dmstatus & (1 << 11)
         anyrunning = dmstatus & (1 << 10)
         if allrunning and anyrunning: