ClockGate wraps lowrisc's prim_clock_gating - By default, this primitive provides a generic clock gate for simulation. There's also a preprocessor define that can be set at synth time, to get a Xilinx-specific gate implementation. Change-Id: I011f3b6211ef27be4458d7c312ac06823e0b1edb
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog