commit	f4ca25810ddedb342d0d2d109187e414f58e3a7f	[log] [tgz]
author	Alex Van Damme <atv@google.com>	Wed Feb 14 12:10:58 2024 -0800
committer	Alex Van Damme <atv@google.com>	Thu Feb 15 13:47:37 2024 -0800
tree	47bd435e7f7a3e3f4e83aa5552f314a7561fa060
parent	06ce364c7b2255d6cc5eeffcea8fc396c389b48b [diff]

ClockGate wraps lowrisc's prim_clock_gating

- By default, this primitive provides a generic clock gate for
  simulation. There's also a preprocessor define that can be set at
  synth time, to get a Xilinx-specific gate implementation.

Change-Id: I011f3b6211ef27be4458d7c312ac06823e0b1edb

hdl/chisel/BUILD[diff]
hdl/chisel/kelvin.core.in[diff]
hdl/verilog/BUILD[diff]
hdl/verilog/ClockGate.sv[Renamed from hdl/verilog/ClockGate.v - diff]
rules/repos.bzl[diff]
third_party/ip/lowrisc/0001-Add-BUILD.bazel.patch[Added - diff]
third_party/ip/lowrisc/BUILD[Added - diff]

7 files changed

tree: 47bd435e7f7a3e3f4e83aa5552f314a7561fa060

README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog