tree 47bd435e7f7a3e3f4e83aa5552f314a7561fa060
parent 06ce364c7b2255d6cc5eeffcea8fc396c389b48b
author Alex Van Damme <atv@google.com> 1707941458 -0800
committer Alex Van Damme <atv@google.com> 1708033657 -0800

ClockGate wraps lowrisc's prim_clock_gating

- By default, this primitive provides a generic clock gate for
  simulation. There's also a preprocessor define that can be set at
  synth time, to get a Xilinx-specific gate implementation.

Change-Id: I011f3b6211ef27be4458d7c312ac06823e0b1edb