)]}'
{
  "commit": "f4ca25810ddedb342d0d2d109187e414f58e3a7f",
  "tree": "47bd435e7f7a3e3f4e83aa5552f314a7561fa060",
  "parents": [
    "06ce364c7b2255d6cc5eeffcea8fc396c389b48b"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Wed Feb 14 12:10:58 2024 -0800"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Feb 15 13:47:37 2024 -0800"
  },
  "message": "ClockGate wraps lowrisc\u0027s prim_clock_gating\n\n- By default, this primitive provides a generic clock gate for\n  simulation. There\u0027s also a preprocessor define that can be set at\n  synth time, to get a Xilinx-specific gate implementation.\n\nChange-Id: I011f3b6211ef27be4458d7c312ac06823e0b1edb\n",
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