|  | // Copyright (c) 2024 Google LLC | 
|  | // | 
|  | // Licensed under the Apache License, Version 2.0 (the "License"); | 
|  | // you may not use this file except in compliance with the License. | 
|  | // You may obtain a copy of the License at | 
|  | // | 
|  | //     https://www.apache.org/licenses/LICENSE-2.0 | 
|  | // | 
|  | // Unless required by applicable law or agreed to in writing, software | 
|  | // distributed under the License is distributed on an "AS IS" BASIS, | 
|  | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | 
|  | // See the License for the specific language governing permissions and | 
|  | // limitations under the License. | 
|  |  | 
|  | core_mini_axi_slave: Verilated.VerilatedPeripheral @ sysbus <0x70000000, +0x40000> | 
|  | maxWidth: 128 | 
|  | address: "127.0.0.1" | 
|  | limitBuffer: 10000 | 
|  |  | 
|  | core_mini_axi_master: Verilated.VerilatedPeripheral @ sysbus <0x80000000, +0x40000> | 
|  | maxWidth: 128 | 
|  | address: "127.0.0.1" | 
|  | limitBuffer: 10000 | 
|  |  | 
|  | rv_core: CPU.RiscV32 @ sysbus | 
|  | hartId: 0 | 
|  | cpuType: "rv32im" | 
|  | allowUnalignedAccesses: true | 
|  |  | 
|  | rv_memory: Memory.MappedMemory @ sysbus 0x20000000 | 
|  | size: 0x400000 | 
|  |  | 
|  | uart0: Antmicro.Renode.Peripherals.UART.TrivialUart @ sysbus 0x54000000 |