Refactor testbenches to scale w/ instructionLanes

- Using the exported parameters from the HDL, refactor the test benches
  to use the specified count of instruction lanes. This should allow us
  to compile the testbenches against verilated models with different
  parameters, without additional source changes.
- Define a few handy utility macros to help with this.

Change-Id: I75dbf43d6f8edfcdf84688a9e05de400f8a8e0fa
10 files changed
tree: c2bf1def9b8d2465aa315b51d709940f13a4051b
  1. doc/
  2. external/
  3. hdl/
  4. lib/
  5. rules/
  6. tests/
  7. third_party/
  8. utils/
  9. .bazelrc
  10. .bazelversion
  11. .gitignore
  14. PREUPLOAD.cfg


Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.


Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog