commit | b754f7c18c648a0a4a89b057d6d30b3679e18b30 | [log] [tgz] |
---|---|---|
author | Alex Van Damme <atv@google.com> | Thu Feb 29 15:46:01 2024 -0800 |
committer | Alex Van Damme <atv@google.com> | Mon Mar 04 13:59:19 2024 -0800 |
tree | c2bf1def9b8d2465aa315b51d709940f13a4051b | |
parent | 0a5012dac31defec46ced59c1a3110f93e40ec21 [diff] |
Refactor testbenches to scale w/ instructionLanes - Using the exported parameters from the HDL, refactor the test benches to use the specified count of instruction lanes. This should allow us to compile the testbenches against verilated models with different parameters, without additional source changes. - Define a few handy utility macros to help with this. Change-Id: I75dbf43d6f8edfcdf84688a9e05de400f8a8e0fa
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog