)]}'
{
  "commit": "b754f7c18c648a0a4a89b057d6d30b3679e18b30",
  "tree": "c2bf1def9b8d2465aa315b51d709940f13a4051b",
  "parents": [
    "0a5012dac31defec46ced59c1a3110f93e40ec21"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Feb 29 15:46:01 2024 -0800"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Mon Mar 04 13:59:19 2024 -0800"
  },
  "message": "Refactor testbenches to scale w/ instructionLanes\n\n- Using the exported parameters from the HDL, refactor the test benches\n  to use the specified count of instruction lanes. This should allow us\n  to compile the testbenches against verilated models with different\n  parameters, without additional source changes.\n- Define a few handy utility macros to help with this.\n\nChange-Id: I75dbf43d6f8edfcdf84688a9e05de400f8a8e0fa\n",
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