Revert "Add option to disable VCore." This reverts commit c27390cfa588e41bb121932dbf8fc6bc7fd6d806. Reason for revert: Need to update call site in Matcha Change-Id: I6b890d0039a691e0764261dd7ed74b57ed966def
diff --git a/hdl/chisel/src/kelvin/Core.scala b/hdl/chisel/src/kelvin/Core.scala index 72b1c03..100078c 100644 --- a/hdl/chisel/src/kelvin/Core.scala +++ b/hdl/chisel/src/kelvin/Core.scala
@@ -34,9 +34,7 @@ val ibus = new IBusIO(p) val dbus = new DBusIO(p) - val axi0 = if(p.enableVector) { - Some(new AxiMasterIO(p.axi2AddrBits, p.axi2DataBits, p.axi2IdBits)) - } else { None } + val axi0 = new AxiMasterIO(p.axi2AddrBits, p.axi2DataBits, p.axi2IdBits) val axi1 = new AxiMasterIO(p.axi2AddrBits, p.axi2DataBits, p.axi2IdBits) val iflush = new IFlushIO(p) @@ -47,7 +45,8 @@ }) val score = SCore(p) - val vcore = if (p.enableVector) { Some(VCore(p)) } else { None } + val vcore = VCore(p) + val dbusmux = DBusMux(p) // --------------------------------------------------------------------------- // Scalar Core outputs. @@ -62,22 +61,17 @@ // --------------------------------------------------------------------------- // Vector core. - if (p.enableVector) { - score.io.vcore.get <> vcore.get.io.score - } + score.io.vcore <> vcore.io.score // --------------------------------------------------------------------------- // Local Data Bus Port - if (p.enableVector) { - val dbusmux = DBusMux(p) - dbusmux.io.vldst := score.io.vldst.get - dbusmux.io.vlast := vcore.get.io.last - dbusmux.io.vcore <> vcore.get.io.dbus - dbusmux.io.score <> score.io.dbus - io.dbus <> dbusmux.io.dbus - } else { - io.dbus <> score.io.dbus - } + dbusmux.io.vldst := score.io.vldst + dbusmux.io.vlast := vcore.io.last + + dbusmux.io.vcore <> vcore.io.dbus + dbusmux.io.score <> score.io.dbus + + io.dbus <> dbusmux.io.dbus // --------------------------------------------------------------------------- // Scalar DBus to AXI. @@ -86,10 +80,8 @@ // --------------------------------------------------------------------------- // AXI ports. - if (p.enableVector) { - io.axi0.get.read <> vcore.get.io.ld - io.axi0.get.write <> vcore.get.io.st - } + io.axi0.read <> vcore.io.ld + io.axi0.write <> vcore.io.st io.axi1 <> dbus2axi.io.axi }
diff --git a/hdl/chisel/src/kelvin/Parameters.scala b/hdl/chisel/src/kelvin/Parameters.scala index a93f69e..3546a74 100644 --- a/hdl/chisel/src/kelvin/Parameters.scala +++ b/hdl/chisel/src/kelvin/Parameters.scala
@@ -56,8 +56,6 @@ val vectorCountBits = log2Ceil(vectorBits / 8) + 1 + 2 // +2 stripmine - // Enable Vector - val enableVector = true val vectorAluCount = 2 val vectorReadPorts = (vectorAluCount * 3) + 1 val vectorWritePorts = 6
diff --git a/hdl/chisel/src/kelvin/scalar/Csr.scala b/hdl/chisel/src/kelvin/scalar/Csr.scala index 621de70..18202d3 100644 --- a/hdl/chisel/src/kelvin/scalar/Csr.scala +++ b/hdl/chisel/src/kelvin/scalar/Csr.scala
@@ -47,12 +47,8 @@ val rfwriteCount = UInt(3.W) val storeCount = UInt(2.W) val branchCount = UInt(1.W) - val vrfwriteCount = if (p.enableVector) { - Some(UInt(3.W)) - } else { None } - val vstoreCount = if (p.enableVector) { - Some(UInt(2.W)) - } else { None } + val vrfwriteCount = UInt(3.W) + val vstoreCount = UInt(2.W) } class CsrBruIO(p: Parameters) extends Bundle { @@ -96,9 +92,7 @@ val bru = Flipped(new CsrBruIO(p)) // Vector core. - val vcore = (if (p.enableVector) { - Some(Input(new Bundle { val undef = Bool() })) - } else { None }) + val vcore = Input(new Bundle { val undef = Bool() }) val counters = Input(new CsrCounters(p)) @@ -193,15 +187,13 @@ val kisaEn = req.bits.index === 0xFC0.U // Pipeline Control. - val vcoreUndef = if (p.enableVector) { io.vcore.get.undef } else { false.B } - when (io.bru.in.halt || vcoreUndef) { + when (io.bru.in.halt || io.vcore.undef) { halted := true.B } - when (io.bru.in.fault || vcoreUndef) { + when (io.bru.in.fault || io.vcore.undef) { fault := true.B } - io.halted := halted io.fault := fault @@ -288,10 +280,8 @@ io.counters.rfwriteCount + io.counters.storeCount + io.counters.branchCount + - (if (p.enableVector) { - io.counters.vrfwriteCount.get + - io.counters.vstoreCount.get - } else { 0.U }) + io.counters.vrfwriteCount + + io.counters.vstoreCount when (io.bru.in.mode.valid) { mode := io.bru.in.mode.bits
diff --git a/hdl/chisel/src/kelvin/scalar/Decode.scala b/hdl/chisel/src/kelvin/scalar/Decode.scala index 206c516..37a0c86 100644 --- a/hdl/chisel/src/kelvin/scalar/Decode.scala +++ b/hdl/chisel/src/kelvin/scalar/Decode.scala
@@ -206,9 +206,7 @@ val dvu = Decoupled(new DvuCmd) // Vector interface. - val vinst = if (p.enableVector) { - Some(Decoupled(new VInstCmd)) - } else { None } + val vinst = Decoupled(new VInstCmd) // Branch status. val branchTaken = Input(Bool()) @@ -225,7 +223,7 @@ val decodeEn = io.inst.valid && io.inst.ready && !io.branchTaken // The decode logic. - val d = DecodeInstruction(p, pipeline, io.inst.addr, io.inst.inst) + val d = DecodeInstruction(pipeline, io.inst.addr, io.inst.inst) val vldst = d.vld || d.vst val vldst_wb = vldst && io.inst.inst(28) @@ -238,9 +236,7 @@ val isCsrImm = d.isCsr() && io.inst.inst(14) val isCsrReg = d.isCsr() && !io.inst.inst(14) - val isVIop = if (p.enableVector) { - io.vinst.get.bits.op === VInstOp.VIOP - } else { false.B } + val isVIop = (io.vinst.bits.op === VInstOp.VIOP) val isVIopVs1 = isVIop val isVIopVs2 = isVIop && io.inst.inst(1,0) === 0.U // exclude: .vv @@ -271,10 +267,8 @@ // Vector extension interlock. - val vinstEn = if (p.enableVector) { - !(io.serializeIn.vinst || isVIop && io.serializeIn.brcond) && - !(d.isVector() && !io.vinst.get.ready) - } else { false.B } + val vinstEn = !(io.serializeIn.vinst || isVIop && io.serializeIn.brcond) && + !(d.isVector() && !io.vinst.ready) // Fence interlock. // Input mactive used passthrough, prefer to avoid registers in Decode. @@ -401,12 +395,10 @@ d.getvl -> MakeValid(true.B, VInstOp.GETVL), d.getmaxvl -> MakeValid(true.B, VInstOp.GETMAXVL), )) - if (p.enableVector) { - io.vinst.get.valid := decodeEn && vinst.valid - io.vinst.get.bits.addr := rdAddr - io.vinst.get.bits.inst := io.inst.inst - io.vinst.get.bits.op := vinst.bits - } + io.vinst.valid := decodeEn && vinst.valid + io.vinst.bits.addr := rdAddr + io.vinst.bits.inst := io.inst.inst + io.vinst.bits.op := vinst.bits // Scalar logging. io.slog := decodeEn && d.slog @@ -484,7 +476,7 @@ } object DecodeInstruction { - def apply(p: Parameters, pipeline: Int, addr: UInt, op: UInt): DecodedInstruction = { + def apply(pipeline: Int, addr: UInt, op: UInt): DecodedInstruction = { val d = Wire(new DecodedInstruction) // Immediates @@ -565,35 +557,27 @@ // Decode scalar log. val slog = DecodeBits(op, "01111_00_00000_xxxxx_0xx_00000_11101_11") - if (p.enableVector) { - // Vector length. - d.getvl := DecodeBits(op, "0001x_xx_xxxxx_xxxxx_000_xxxxx_11101_11") && op(26,25) =/= 3.U && (op(24,20) =/= 0.U || op(19,15) =/= 0.U) - d.getmaxvl := DecodeBits(op, "0001x_xx_00000_00000_000_xxxxx_11101_11") && op(26,25) =/= 3.U + // Vector length. + d.getvl := DecodeBits(op, "0001x_xx_xxxxx_xxxxx_000_xxxxx_11101_11") && op(26,25) =/= 3.U && (op(24,20) =/= 0.U || op(19,15) =/= 0.U) + d.getmaxvl := DecodeBits(op, "0001x_xx_00000_00000_000_xxxxx_11101_11") && op(26,25) =/= 3.U - // Vector load/store. - d.vld := DecodeBits(op, "000xxx_0xxxxx_xxxxx0_xx_xxxxxx_x_111_11") // vld + // Vector load/store. + d.vld := DecodeBits(op, "000xxx_0xxxxx_xxxxx0_xx_xxxxxx_x_111_11") // vld - d.vst := DecodeBits(op, "001xxx_0xxxxx_xxxxx0_xx_xxxxxx_x_111_11") || // vst - DecodeBits(op, "011xxx_0xxxxx_xxxxx0_xx_xxxxxx_x_111_11") // vstq + d.vst := DecodeBits(op, "001xxx_0xxxxx_xxxxx0_xx_xxxxxx_x_111_11") || // vst + DecodeBits(op, "011xxx_0xxxxx_xxxxx0_xx_xxxxxx_x_111_11") // vstq - // Convolution transfer accumulators to vregs. Also decodes acset/actr ops. - val vconv = DecodeBits(op, "010100_000000_000000_xx_xxxxxx_x_111_11") + // Convolution transfer accumulators to vregs. Also decodes acset/actr ops. + val vconv = DecodeBits(op, "010100_000000_000000_xx_xxxxxx_x_111_11") - // Duplicate - val vdup = DecodeBits(op, "01000x_0xxxxx_000000_xx_xxxxxx_x_111_11") && op(13,12) <= 2.U - val vdupi = vdup && op(26) === 0.U + // Duplicate + val vdup = DecodeBits(op, "01000x_0xxxxx_000000_xx_xxxxxx_x_111_11") && op(13,12) <= 2.U + val vdupi = vdup && op(26) === 0.U - // Vector instructions. - d.viop := op(0) === 0.U || // .vv .vx - op(1,0) === 1.U || // .vvv .vxv - vconv || vdupi - } else { - d.getvl := false.B - d.getmaxvl := false.B - d.vld := false.B - d.vst := false.B - d.viop := false.B - } + // Vector instructions. + d.viop := op(0) === 0.U || // .vv .vx + op(1,0) === 1.U || // .vvv .vxv + vconv || vdupi // [extensions] Core controls. d.ebreak := DecodeBits(op, "000000000001_00000_000_00000_11100_11")
diff --git a/hdl/chisel/src/kelvin/scalar/SCore.scala b/hdl/chisel/src/kelvin/scalar/SCore.scala index 6c9c47e..0c51a55 100644 --- a/hdl/chisel/src/kelvin/scalar/SCore.scala +++ b/hdl/chisel/src/kelvin/scalar/SCore.scala
@@ -36,11 +36,9 @@ val ibus = new IBusIO(p) val dbus = new DBusIO(p) val ubus = new DBusIO(p) + val vldst = Output(Bool()) - val vldst = if (p.enableVector) { Some(Output(Bool())) } else { None } - val vcore = if (p.enableVector) { - Some(Flipped(new VCoreIO(p))) - } else { None } + val vcore = Flipped(new VCoreIO(p)) val iflush = new IFlushIO(p) val dflush = new DFlushIO(p) @@ -129,7 +127,7 @@ decode(i).io.scoreboard.regd := regfile.io.scoreboard.regd | scoreboard_spec(i) } - decode(0).io.mactive := (if (p.enableVector) { io.vcore.get.mactive } else { false.B }) + decode(0).io.mactive := io.vcore.mactive for (i <- 1 until p.instructionLanes) { decode(i).io.mactive := false.B } @@ -162,10 +160,8 @@ csr.io.counters.rfwriteCount := regfile.io.rfwriteCount csr.io.counters.storeCount := lsu.io.storeCount csr.io.counters.branchCount := bru(0).io.taken.valid - if (p.enableVector) { - csr.io.counters.vrfwriteCount.get := io.vcore.get.vrfwriteCount - csr.io.counters.vstoreCount.get := io.vcore.get.vstoreCount - } + csr.io.counters.vrfwriteCount := io.vcore.vrfwriteCount + csr.io.counters.vstoreCount := io.vcore.vstoreCount // --------------------------------------------------------------------------- // Control Status Unit @@ -174,9 +170,7 @@ csr.io.req <> decode(0).io.csr csr.io.rs1 := regfile.io.readData(0) - if (p.enableVector) { - csr.io.vcore.get.undef := io.vcore.get.undef - } + csr.io.vcore.undef := io.vcore.undef // --------------------------------------------------------------------------- // Status @@ -225,35 +219,23 @@ regfile.io.writeData(i).valid := csr0Valid || alu(i).io.rd.valid || bru(i).io.rd.valid || - (if (p.enableVector) { - io.vcore.get.rd(i).valid - } else { false.B }) + io.vcore.rd(i).valid regfile.io.writeData(i).addr := MuxOR(csr0Valid, csr0Addr) | MuxOR(alu(i).io.rd.valid, alu(i).io.rd.addr) | MuxOR(bru(i).io.rd.valid, bru(i).io.rd.addr) | - (if (p.enableVector) { - MuxOR(io.vcore.get.rd(i).valid, io.vcore.get.rd(i).addr) - } else { false.B }) - + MuxOR(io.vcore.rd(i).valid, io.vcore.rd(i).addr) regfile.io.writeData(i).data := MuxOR(csr0Valid, csr0Data) | MuxOR(alu(i).io.rd.valid, alu(i).io.rd.data) | MuxOR(bru(i).io.rd.valid, bru(i).io.rd.data) | - (if (p.enableVector) { - MuxOR(io.vcore.get.rd(i).valid, io.vcore.get.rd(i).data) - } else { false.B }) + MuxOR(io.vcore.rd(i).valid, io.vcore.rd(i).data) - if (p.enableVector) { - assert((csr0Valid +& - alu(i).io.rd.valid +& bru(i).io.rd.valid +& - io.vcore.get.rd(i).valid) <= 1.U) - } else { - assert((csr0Valid +& - alu(i).io.rd.valid +& bru(i).io.rd.valid) <= 1.U) - } + assert((csr0Valid +& + alu(i).io.rd.valid +& bru(i).io.rd.valid +& + io.vcore.rd(i).valid) <= 1.U) } val mluDvuOffset = p.instructionLanes @@ -274,9 +256,12 @@ // --------------------------------------------------------------------------- // Vector Extension - if (p.enableVector) { - io.vcore.get.vinst <> decode.map(_.io.vinst.get) - io.vcore.get.rs := regfile.io.readData + for (i <- 0 until p.instructionLanes) { + io.vcore.vinst(i) <> decode(i).io.vinst + } + + for (i <- 0 until p.instructionLanes * 2) { + io.vcore.rs(i) := regfile.io.readData(i) } // --------------------------------------------------------------------------- @@ -288,9 +273,7 @@ io.dbus <> lsu.io.dbus io.ubus <> lsu.io.ubus - if (p.enableVector) { - io.vldst.get := lsu.io.vldst - } + io.vldst := lsu.io.vldst // --------------------------------------------------------------------------- // Scalar logging interface
diff --git a/tests/verilator_sim/kelvin/core_tb.cc b/tests/verilator_sim/kelvin/core_tb.cc index 9fff817..73396ab 100644 --- a/tests/verilator_sim/kelvin/core_tb.cc +++ b/tests/verilator_sim/kelvin/core_tb.cc
@@ -98,7 +98,6 @@ sc_signal<sc_bv<32> > io_debug_inst2; sc_signal<sc_bv<32> > io_debug_inst3; sc_signal<sc_bv<32> > io_debug_cycles; -#if 1 sc_signal<bool> io_axi0_write_addr_ready; sc_signal<bool> io_axi0_write_addr_valid; sc_signal<sc_bv<32> > io_axi0_write_addr_bits_addr; @@ -120,7 +119,6 @@ sc_signal<sc_bv<2> > io_axi0_read_data_bits_resp; sc_signal<sc_bv<kUncId> > io_axi0_read_data_bits_id; sc_signal<sc_bv<kUncBits> > io_axi0_read_data_bits_data; -#endif // TODO: Disable if no VCore sc_signal<bool> io_axi1_write_addr_ready; sc_signal<bool> io_axi1_write_addr_valid; sc_signal<sc_bv<32> > io_axi1_write_addr_bits_addr; @@ -232,7 +230,6 @@ #define BINDAXI(a) \ core.a(a); \ mif.a(a) -#if 1 BINDAXI(io_axi0_write_addr_ready); BINDAXI(io_axi0_write_addr_valid); BINDAXI(io_axi0_write_addr_bits_addr); @@ -254,7 +251,6 @@ BINDAXI(io_axi0_read_data_bits_resp); BINDAXI(io_axi0_read_data_bits_id); BINDAXI(io_axi0_read_data_bits_data); -#endif // TODO: Disable if no VCore BINDAXI(io_axi1_write_addr_ready); BINDAXI(io_axi1_write_addr_valid); BINDAXI(io_axi1_write_addr_bits_addr);