| commit | 88b0bbde9007e0e52a4dcd8dd8b2c1cf9ef45120 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Sep 02 15:54:02 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Fri Sep 05 10:52:09 2025 -0700 |
| tree | 4778875a6c705ef38994fafc39280d011ef7cd25 | |
| parent | a9ce01c608f8afd9f8f205e2077257ccc3b5339c [diff] |
feat(soc): Add Spi2TLUL bridge and tests This commit introduces a new Chisel module, `Spi2TLUL`, which functions as a bridge between a SPI slave interface and a TileLink UL master interface. This allows an external SPI master to initiate TileLink transactions within the SoC. The bridge includes: - A register map accessible via SPI for configuring TileLink transactions (address, length, command). - A data buffer for staging data for both read and write operations. - Asynchronous queues to handle clock domain crossing between the SPI clock and the main SoC clock. - State machines to manage SPI commands and TileLink transactions for both reads and writes. To support verification, this commit also adds: - A Python-based `SPIMaster` class for cocotb, providing an easy-to-use interface for driving the SPI slave. - A comprehensive cocotb test suite (`test_spi_to_tlul.py`) with tests for: - Register read/write access. - Single and multi-beat TileLink reads. - Single and multi-beat TileLink writes. The necessary BUILD file modifications are included to integrate the new module and its tests into the Chisel and cocotb build systems. Change-Id: Ie1280db53e77cec7b3f734b5bd6d63c8d41b2ca9
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog