tree 4778875a6c705ef38994fafc39280d011ef7cd25
parent a9ce01c608f8afd9f8f205e2077257ccc3b5339c
author Alex Van Damme <atv@google.com> 1756853642 -0700
committer Alex Van Damme <atv@google.com> 1757094729 -0700

feat(soc): Add Spi2TLUL bridge and tests

This commit introduces a new Chisel module, `Spi2TLUL`, which functions as a bridge between a SPI slave interface and a TileLink UL master interface. This allows an external SPI master to initiate TileLink transactions within the SoC.

The bridge includes:
- A register map accessible via SPI for configuring TileLink transactions (address, length, command).
- A data buffer for staging data for both read and write operations.
- Asynchronous queues to handle clock domain crossing between the SPI clock and the main SoC clock.
- State machines to manage SPI commands and TileLink transactions for both reads and writes.

To support verification, this commit also adds:
- A Python-based `SPIMaster` class for cocotb, providing an easy-to-use interface for driving the SPI slave.
- A comprehensive cocotb test suite (`test_spi_to_tlul.py`) with tests for:
  - Register read/write access.
  - Single and multi-beat TileLink reads.
  - Single and multi-beat TileLink writes.

The necessary BUILD file modifications are included to integrate the new module and its tests into the Chisel and cocotb build systems.

Change-Id: Ie1280db53e77cec7b3f734b5bd6d63c8d41b2ca9