)]}'
{
  "commit": "88b0bbde9007e0e52a4dcd8dd8b2c1cf9ef45120",
  "tree": "4778875a6c705ef38994fafc39280d011ef7cd25",
  "parents": [
    "a9ce01c608f8afd9f8f205e2077257ccc3b5339c"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Sep 02 15:54:02 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Fri Sep 05 10:52:09 2025 -0700"
  },
  "message": "feat(soc): Add Spi2TLUL bridge and tests\n\nThis commit introduces a new Chisel module, `Spi2TLUL`, which functions as a bridge between a SPI slave interface and a TileLink UL master interface. This allows an external SPI master to initiate TileLink transactions within the SoC.\n\nThe bridge includes:\n- A register map accessible via SPI for configuring TileLink transactions (address, length, command).\n- A data buffer for staging data for both read and write operations.\n- Asynchronous queues to handle clock domain crossing between the SPI clock and the main SoC clock.\n- State machines to manage SPI commands and TileLink transactions for both reads and writes.\n\nTo support verification, this commit also adds:\n- A Python-based `SPIMaster` class for cocotb, providing an easy-to-use interface for driving the SPI slave.\n- A comprehensive cocotb test suite (`test_spi_to_tlul.py`) with tests for:\n  - Register read/write access.\n  - Single and multi-beat TileLink reads.\n  - Single and multi-beat TileLink writes.\n\nThe necessary BUILD file modifications are included to integrate the new module and its tests into the Chisel and cocotb build systems.\n\nChange-Id: Ie1280db53e77cec7b3f734b5bd6d63c8d41b2ca9\n",
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