| commit | 0004fc32c1b0d4287693d1d0d1febce780730cf0 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Aug 19 13:29:51 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Aug 28 17:09:51 2025 -0700 |
| tree | 2915f8998a98da26677dcaeb2a36e0040a8b65f5 | |
| parent | be106f192e7e77a9038adf577aafa6c2d4e03b6c [diff] |
feat(soc): Add data-driven TileLink-UL crossbar This commit introduces a data-driven TileLink-UL crossbar for the Kelvin SoC. The entire crossbar topology is defined in a single `CrossbarConfig.scala` file, which serves as the single source of truth for hosts, devices, address maps, and connections. The `KelvinXbar.scala` module programmatically generates the crossbar by instantiating and connecting the necessary TileLink primitives (sockets, FIFOs, width bridges) based on the configuration. This approach provides a flexible and maintainable way to manage the SoC's interconnect. Key features: - Centralized configuration in `CrossbarConfig.scala`. - A validator to check for configuration errors, such as overlapping address ranges. - Automatic instantiation of TileLink primitives. - Programmatic address decoding and wiring. - Support for multiple, asynchronous clock domains. - A comprehensive cocotb test suite (`kelvin_xbar_test.py`) that verifies various data paths, including width and clock domain crossings, error responses, and integrity checks. Change-Id: I6b341aadfabcc9c2220c1818246989c35bba8ad5
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog