)]}'
{
  "commit": "0004fc32c1b0d4287693d1d0d1febce780730cf0",
  "tree": "2915f8998a98da26677dcaeb2a36e0040a8b65f5",
  "parents": [
    "be106f192e7e77a9038adf577aafa6c2d4e03b6c"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Aug 19 13:29:51 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Aug 28 17:09:51 2025 -0700"
  },
  "message": "feat(soc): Add data-driven TileLink-UL crossbar\n\nThis commit introduces a data-driven TileLink-UL crossbar for the\nKelvin SoC. The entire crossbar topology is defined in a single\n`CrossbarConfig.scala` file, which serves as the single source of\ntruth for hosts, devices, address maps, and connections.\n\nThe `KelvinXbar.scala` module programmatically generates the crossbar\nby instantiating and connecting the necessary TileLink primitives\n(sockets, FIFOs, width bridges) based on the configuration. This\napproach provides a flexible and maintainable way to manage the SoC\u0027s\ninterconnect.\n\nKey features:\n- Centralized configuration in `CrossbarConfig.scala`.\n- A validator to check for configuration errors, such as overlapping\n  address ranges.\n- Automatic instantiation of TileLink primitives.\n- Programmatic address decoding and wiring.\n- Support for multiple, asynchronous clock domains.\n- A comprehensive cocotb test suite (`kelvin_xbar_test.py`) that\n  verifies various data paths, including width and clock domain\n  crossings, error responses, and integrity checks.\n\nChange-Id: I6b341aadfabcc9c2220c1818246989c35bba8ad5\n",
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