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opensecura / 3p / lowrisc / opentitan / e80889822da73cc8aaed5e7da6823522de95d2e1 / util
  1. 9b38141 [dvsim] Minor fixes to coverage extraction by Srikrishna Iyer · 3 years, 9 months ago
  2. 426ed20 [topgen/pinmux/doc] Autogen target pinout / pinmux connectivity tables by Michael Schaffner · 3 years, 9 months ago
  3. 813df39 [sram_ctrl_ret_aon] Remove en_ifetch chicken bit from retention RAM by Michael Schaffner · 3 years, 9 months ago
  4. 57dc8dc [dv] enhance multi-field in RAL model by Weicai Yang · 3 years, 9 months ago
  5. 7874970 [top] Re-align English Breakfast top level with Earl Grey by Pirmin Vogel · 3 years, 9 months ago
  6. 8d1feca [topgen] Improve matching of prefix when renaming parameters by Pirmin Vogel · 3 years, 9 months ago
  7. b6473e2 [reggen] Disallow internal shadow registers from hardware write. by Timothy Chen · 3 years, 9 months ago
  8. 4e7114e [sram_ctrl] Absorb prim_ram_1p_scr by Michael Schaffner · 3 years, 10 months ago
  9. a0a35a5 Copy all bitstreams into distribution by Philipp Wagner · 3 years, 9 months ago
  10. c58548c [reggen] Minor fix to handle internal shadow registers by Timothy Chen · 3 years, 9 months ago
  11. b93cc6a [util] Added Python script to generate a status report of the DIFs. by Timothy Trippel · 3 years, 9 months ago
  12. 01c56b4 [dv, doc] Replace all 'dv.plan' with testplan by Srikrishna Iyer · 3 years, 9 months ago
  13. 6672f06 Fix the testplan link in dvsim code by Srikrishna Iyer · 3 years, 9 months ago
  14. 87fb9e3 [fpga] Reduce noise for AES SCA by Pirmin Vogel · 3 years, 9 months ago
  15. 5bf9734 [fpga, sw] Enable SCA on ChipWhisperer CW310 FPGA board by Pirmin Vogel · 3 years, 10 months ago
  16. 502a20f [chip_earlgrey_asic/lint] Fix/waive remaining AST-related lint messages by Michael Schaffner · 3 years, 9 months ago
  17. c57e558 [dv] update reg path for async registers by Timothy Chen · 3 years, 9 months ago
  18. a49ceb6 [util, reggen] Support standardized cdc handling for regfile by Timothy Chen · 3 years, 10 months ago
  19. 7d2e994 [dv] Override mem with info in the top hjson for RAL by Weicai Yang · 3 years, 9 months ago
  20. 63c6606 [topgen] Relocate instance check to clarify intent by Timothy Chen · 3 years, 9 months ago
  21. 393a762 [rstmgr / top] Adjust rstmgr / top level connections by Timothy Chen · 3 years, 9 months ago
  22. 465fb62 [dvsim] Fix publish report summary typo by Cindy Chen · 3 years, 9 months ago
  23. 6f5c91e formatter: Expand verible-format allowlist by Lukasz Dalek · 3 years, 9 months ago
  24. 7efbbbd [dvsim] Separate publish report from dvsim flow [PART3] by Cindy Chen · 3 years, 9 months ago
  25. 0bedfa6 [topgen] Add missing memory attributes by Michael Schaffner · 3 years, 9 months ago
  26. ec5301e [topgen] Remove hardcoded ROM memory from template by Michael Schaffner · 3 years, 9 months ago
  27. 9ce30ab [prim_subreg] Make software access type an enum by Philipp Wagner · 3 years, 9 months ago
  28. ab5c149 [topgen] Pass fewer values to clkmgr templates by Rupert Swarbrick · 3 years, 10 months ago
  29. 710e3c9 [clkmgr] Allow multiple hint clocks in a block by Rupert Swarbrick · 3 years, 10 months ago
  30. 5aa249f [topgen] Be explicit about where hint clocks get connected by Rupert Swarbrick · 3 years, 10 months ago
  31. 2094ac8 [topgen] Store set of endpoints in ClockSignal connection by Rupert Swarbrick · 3 years, 10 months ago
  32. ee27c0f [topgen] Use the list from clocks.py to figure out idle signals by Rupert Swarbrick · 3 years, 10 months ago
  33. 0c9cf5c [topgen] Move more logic to clocks.py by Rupert Swarbrick · 3 years, 10 months ago
  34. 3b38e95 [sw/tock] Remove Tock by Jon Flatley · 3 years, 9 months ago
  35. ed81ae1 [otp_ctrl/lc_ctrl] Add MANUF_STATE to HW_CFG and expose through LC TAP by Michael Schaffner · 3 years, 10 months ago
  36. 06d2983 [ast] Add prim_lfsr to ast.core by Jacob Levy · 3 years, 10 months ago
  37. 576cc08 [top, ibex, aon_timer] Connect watchdog bark to NMI by Timothy Chen · 3 years, 9 months ago
  38. 7c3de6e [util] Prep work for shadow reset impelemtation by Timothy Chen · 3 years, 10 months ago
  39. 914bdad [script/dvsim] Separate publish report from dvsim flow [PART2] by Cindy Chen · 3 years, 10 months ago
  40. 2b0155a [rv_core_ibex] Minor clean-up by Timothy Chen · 3 years, 10 months ago
  41. dcc5f9f [ipgen] Initial commit of IP generation tool by Philipp Wagner · 4 years, 2 months ago
  42. 52bce9f [nmi_gen] remove the nmi_gen dummy module by Michael Schaffner · 3 years, 10 months ago
  43. 97fe6a8 [top_englishbreakfast] Use rom_ctrl, not a raw memory instance by Rupert Swarbrick · 3 years, 10 months ago
  44. 127b109 [topgen] Pull the 'clocks' code into a separate class in topgen by Rupert Swarbrick · 3 years, 10 months ago
  45. 9d4ed87 [top] Correct parameter defaults in top_earlgrey by Timothy Chen · 3 years, 10 months ago
  46. 1a5d53a [alert_handler] Make critical alert handler CSRs shadowed regs by Michael Schaffner · 4 years ago
  47. f69b700 [dv] handle multireg with unevenly divided fields by Weicai Yang · 3 years, 10 months ago
  48. 00f6d78 [dv] Use array for multi-reg in RAL model by Weicai Yang · 3 years, 10 months ago
  49. 704bf01 formatter: Expand verible-format-allowlist by Lukasz Dalek · 3 years, 10 months ago
  50. a2675f9 [top] Split long parameter lines in toplevel.sv.tpl by Rupert Swarbrick · 3 years, 10 months ago
  51. b789cf5 [reggen] Add "REG_RESVAL" defines to generated C headers by Rupert Swarbrick · 3 years, 11 months ago
  52. bd46e9c [vendor.py] Enable overriding of upstream.rev by Philipp Wagner · 3 years, 10 months ago
  53. 1d8b960 [top, dv, sw] Various adjustments to accommodate rv_core_ibex peripheral by Timothy Chen · 3 years, 10 months ago
  54. 02e982f [topgen] Updates for declaring memory regions within IPs by Michael Schaffner · 3 years, 10 months ago
  55. 0fd914d [dv/rstmgr] Create dv collateral by Guillermo Maturana · 3 years, 10 months ago
  56. c9f99d8 [util] Add ability to declare parameter level directly from top_earlgrey.hjson by Timothy Chen · 3 years, 10 months ago
  57. 70151fe [keymgr] Add otbn sideload and expand to 384-bit sideload key support by Timothy Chen · 3 years, 10 months ago
  58. 0f6e781 [otbn] fork rsa verify code for 3k version by Felix Miller · 4 years ago
  59. a753390 [xbar/dv] Fix name search issue by Weicai Yang · 3 years, 10 months ago
  60. a06d709 [lc_ctrl/otp_ctrl] Check whether tokens have been provisioned by Michael Schaffner · 3 years, 10 months ago
  61. 27557de [ast] Mostly updates to internal code by Jacob Levy · 3 years, 10 months ago
  62. 78964d7 [lc_ctrl] Fix the cshake byte order in the constants generation script by Michael Schaffner · 3 years, 10 months ago
  63. 31fb03b [check_tool_requirements] Add semver parser for Ninja by Michael Schaffner · 3 years, 10 months ago
  64. 690d732 [rv_dm] Make the RV_DM a comportable module by Michael Schaffner · 3 years, 10 months ago
  65. d0cbfad [reggen] Pair up clock and reset signals by Rupert Swarbrick · 3 years, 10 months ago
  66. da12563 [sw] proof of concept of address translation idea by Timothy Chen · 3 years, 10 months ago
  67. 244a8dd [sensor_ctrl, ast] Preparation for sensor_ctrl d2 by Timothy Chen · 4 years ago
  68. 40a80bb formatter: Expand verible-format-allowlist by Lukasz Dalek · 3 years, 11 months ago
  69. 674628a [tlul] Add byte level handling for integrity by Timothy Chen · 3 years, 10 months ago
  70. 3e3cb48 [top] Integrate rv_core_ibex_peri into earlgrey by Timothy Chen · 3 years, 10 months ago
  71. 82c2181 [otp_ctrl] Add bit remapping option to OTP image generation script by Michael Schaffner · 3 years, 10 months ago
  72. 0b53455 [lc_ctrl/alerts] Fix a typo by Michael Schaffner · 3 years, 10 months ago
  73. 997f1f3 formatter: Replace verible-format.sh script with new version by Lukasz Dalek · 3 years, 11 months ago
  74. 77358fa [tools/dvsim] Fix some VCS flags by Guillermo Maturana · 3 years, 10 months ago
  75. 7cb7f20 [reggen] Generate a single we/re signal per register in reg_top by Rupert Swarbrick · 3 years, 11 months ago
  76. 96761de [top] Make all alerts asynchronous by Michael Schaffner · 3 years, 10 months ago
  77. d562377 [dvsim] Fix GUI mode and launcher creation fixes by Srikrishna Iyer · 3 years, 11 months ago
  78. 7252f17 [reggen] Remove swaccess and hwaccess from Register objects by Rupert Swarbrick · 3 years, 11 months ago
  79. bf0909a [reggen,dv] Don't specify rights for add_reg when constructing RAL by Rupert Swarbrick · 3 years, 11 months ago
  80. b72ccf0 [dv/all] update scoreboard `csr_addrs` accesses by Udi Jonnalagadda · 3 years, 11 months ago
  81. 7bc9c7d [fpv] Fix template by ayann-snps · 3 years, 11 months ago
  82. fe3a0fc [ast / sensor_ctrl] Expand ast alerts to 13 by Timothy Chen · 3 years, 11 months ago
  83. 56544b0 [topgen,clkmgr] De-duplicate clock hint names by Rupert Swarbrick · 3 years, 11 months ago
  84. 57054be [reggen] Simplify reg_top ports if there's exactly one window by Rupert Swarbrick · 3 years, 11 months ago
  85. 635d311 [dvsim] Separate publish report option [PART1] by Cindy Chen · 4 years ago
  86. 50e7af2 Remove rom-ext-manifest-generator.py and related files. by Alphan Ulusoy · 3 years, 11 months ago
  87. 3ec706f [dv/common] update intr_state CSR exclusions by Udi Jonnalagadda · 3 years, 11 months ago
  88. 95f91c1 [topgen] Fix hex chunking code by Rupert Swarbrick · 3 years, 11 months ago
  89. d597758 [script/dvsim] Update output folder by Cindy Chen · 3 years, 11 months ago
  90. da5ed15 [reggen] Optionally expose register interface in reg2hw signal by Rupert Swarbrick · 3 years, 11 months ago
  91. 447835d [rom_ctrl] Remove SkipCheck parameter by Rupert Swarbrick · 3 years, 11 months ago
  92. 49e177c [reggen] Remove hwqe and hwre from Field objects in Python code by Rupert Swarbrick · 4 years ago
  93. c5a68c9 [reggen] Slightly refactor code for hwext register fields by Rupert Swarbrick · 4 years ago
  94. 359c126 [reggen] Make spacing uniform and simplify comments in reg_top by Rupert Swarbrick · 4 years ago
  95. 0f6eeaf [reggen] Tighten up types in reggen and add a mypy lint check by Rupert Swarbrick · 4 years ago
  96. ba0bd32 [reggen] Fix indentation in ip_block.py by Rupert Swarbrick · 3 years, 11 months ago
  97. 1e3deb5 [util/fpga] Add "save to eeprom" feature by Colin O'Flynn · 3 years, 11 months ago
  98. b98898d [reggen] Update reggen to break long lines in struct definition by Michael Schaffner · 4 years ago
  99. 54d11c1 [reggen] Update _SHADOWED naming check to allow for multiregs by Michael Schaffner · 4 years ago
  100. d59fd18 [enthropy_src/rtl] added fw override otp fuse by Michael Schaffner · 4 years ago