- 7a2b15c [top, util] Add quick support for multiple power domain resets by Timothy Chen · 3 years, 7 months ago
- da8885e [sva/keymgr] Fix csr assertion error by Cindy Chen · 3 years, 7 months ago
- 11f0f9a [otp_ctrl] Add option to disable alerts for ECC uncorrectable errors by Michael Schaffner · 3 years, 7 months ago
- 340e623 [bazel] Autogenerate register headers from hjson by Chris Frantz · 3 years, 7 months ago
- 3a2d0bc [top/dv] Add automatic toggle exclusion by Weicai Yang · 3 years, 7 months ago
- 9bfdaab [util] Fix topgen verbosity by Rupert Swarbrick · 3 years, 7 months ago
- bef0c8c [docker] Install python deps in same way as CI and users by Alex Bradbury · 3 years, 7 months ago
- 2479883 [flash_ctrl] Handle invalid software input by Timothy Chen · 3 years, 7 months ago
- c41bfe1 [top] Review and update of clock / reset settings for all modules by Timothy Chen · 3 years, 7 months ago
- fb8a784 [flash, top] Merge flash_phy into flash_ctrl by Timothy Chen · 3 years, 7 months ago
- 05fc3e1 [tool,check_dif_status] Better rep of DIF progress by Srikrishna Iyer · 3 years, 7 months ago
- e42c8f6 [topgen] Add ability to query the blocks in top by Srikrishna Iyer · 3 years, 7 months ago
- b146659 [dv] Update RAL-gen to make all mutli-reg to arrays by Weicai Yang · 3 years, 7 months ago
- 5d83537 [regfile] Refactor cdc handling to the reg level by Timothy Chen · 3 years, 7 months ago
- e03b555 [top] Add support for 'io' in intermodule by Timothy Chen · 3 years, 7 months ago
- a038790 regtool: add support to generate reg const as Rust (.rs) by Chia-Chi Teng · 3 years, 8 months ago
- e83d30f [rstmgr, top] Add support for shadow resets by Timothy Chen · 3 years, 8 months ago
- 695b028 [usb/top] Remove AND gates on non-AON domain and rename 3.3V signal by Michael Schaffner · 3 years, 7 months ago
- cd90fe8 [dif/rv_plic] fix incorrect DIF naming convention by Timothy Trippel · 3 years, 7 months ago
- e9c0624 [dif/entropy_src] fix incorrect DIF naming convention by Timothy Trippel · 3 years, 7 months ago
- 94228dc [ast] Add POKs 3.3V (update) by Jacob Levy · 3 years, 7 months ago
- 6333c28 [xbar/dv] Fix exclusion by Weicai Yang · 3 years, 7 months ago
- 1cca82c [xbar/dv] Remove d_user constraint and exclusion for *_user by Weicai Yang · 3 years, 7 months ago
- c473f70 [aes] Use separate subreg prims for fields of shadowed control reg by Pirmin Vogel · 3 years, 7 months ago
- cf00b9f formatter: Expand verible-format allowlist by Lukasz Dalek · 3 years, 8 months ago
- 05298bd [tools/uvmdvgen] Fix path in testplan inclusion by Guillermo Maturana · 3 years, 7 months ago
- 571ce3d [otp] Allow partitions to automatically determine size by Timothy Chen · 3 years, 8 months ago
- 5d06aac [top, keymgr, kmac] Ensure masking consistency between keymgr/kmac by Timothy Chen · 3 years, 8 months ago
- 21721e3 [dv, xcelium] Fix statement coverage extraction by Srikrishna Iyer · 3 years, 8 months ago
- 9b38141 [dvsim] Minor fixes to coverage extraction by Srikrishna Iyer · 3 years, 8 months ago
- 426ed20 [topgen/pinmux/doc] Autogen target pinout / pinmux connectivity tables by Michael Schaffner · 3 years, 8 months ago
- 813df39 [sram_ctrl_ret_aon] Remove en_ifetch chicken bit from retention RAM by Michael Schaffner · 3 years, 8 months ago
- 57dc8dc [dv] enhance multi-field in RAL model by Weicai Yang · 3 years, 8 months ago
- 7874970 [top] Re-align English Breakfast top level with Earl Grey by Pirmin Vogel · 3 years, 8 months ago
- 8d1feca [topgen] Improve matching of prefix when renaming parameters by Pirmin Vogel · 3 years, 8 months ago
- b6473e2 [reggen] Disallow internal shadow registers from hardware write. by Timothy Chen · 3 years, 8 months ago
- 4e7114e [sram_ctrl] Absorb prim_ram_1p_scr by Michael Schaffner · 3 years, 9 months ago
- a0a35a5 Copy all bitstreams into distribution by Philipp Wagner · 3 years, 8 months ago
- c58548c [reggen] Minor fix to handle internal shadow registers by Timothy Chen · 3 years, 8 months ago
- b93cc6a [util] Added Python script to generate a status report of the DIFs. by Timothy Trippel · 3 years, 8 months ago
- 01c56b4 [dv, doc] Replace all 'dv.plan' with testplan by Srikrishna Iyer · 3 years, 8 months ago
- 6672f06 Fix the testplan link in dvsim code by Srikrishna Iyer · 3 years, 8 months ago
- 87fb9e3 [fpga] Reduce noise for AES SCA by Pirmin Vogel · 3 years, 8 months ago
- 5bf9734 [fpga, sw] Enable SCA on ChipWhisperer CW310 FPGA board by Pirmin Vogel · 3 years, 8 months ago
- 502a20f [chip_earlgrey_asic/lint] Fix/waive remaining AST-related lint messages by Michael Schaffner · 3 years, 8 months ago
- c57e558 [dv] update reg path for async registers by Timothy Chen · 3 years, 8 months ago
- a49ceb6 [util, reggen] Support standardized cdc handling for regfile by Timothy Chen · 3 years, 8 months ago
- 7d2e994 [dv] Override mem with info in the top hjson for RAL by Weicai Yang · 3 years, 8 months ago
- 63c6606 [topgen] Relocate instance check to clarify intent by Timothy Chen · 3 years, 8 months ago
- 393a762 [rstmgr / top] Adjust rstmgr / top level connections by Timothy Chen · 3 years, 8 months ago
- 465fb62 [dvsim] Fix publish report summary typo by Cindy Chen · 3 years, 8 months ago
- 6f5c91e formatter: Expand verible-format allowlist by Lukasz Dalek · 3 years, 8 months ago
- 7efbbbd [dvsim] Separate publish report from dvsim flow [PART3] by Cindy Chen · 3 years, 8 months ago
- 0bedfa6 [topgen] Add missing memory attributes by Michael Schaffner · 3 years, 8 months ago
- ec5301e [topgen] Remove hardcoded ROM memory from template by Michael Schaffner · 3 years, 8 months ago
- 9ce30ab [prim_subreg] Make software access type an enum by Philipp Wagner · 3 years, 8 months ago
- ab5c149 [topgen] Pass fewer values to clkmgr templates by Rupert Swarbrick · 3 years, 8 months ago
- 710e3c9 [clkmgr] Allow multiple hint clocks in a block by Rupert Swarbrick · 3 years, 8 months ago
- 5aa249f [topgen] Be explicit about where hint clocks get connected by Rupert Swarbrick · 3 years, 8 months ago
- 2094ac8 [topgen] Store set of endpoints in ClockSignal connection by Rupert Swarbrick · 3 years, 8 months ago
- ee27c0f [topgen] Use the list from clocks.py to figure out idle signals by Rupert Swarbrick · 3 years, 8 months ago
- 0c9cf5c [topgen] Move more logic to clocks.py by Rupert Swarbrick · 3 years, 8 months ago
- 3b38e95 [sw/tock] Remove Tock by Jon Flatley · 3 years, 8 months ago
- ed81ae1 [otp_ctrl/lc_ctrl] Add MANUF_STATE to HW_CFG and expose through LC TAP by Michael Schaffner · 3 years, 8 months ago
- 06d2983 [ast] Add prim_lfsr to ast.core by Jacob Levy · 3 years, 8 months ago
- 576cc08 [top, ibex, aon_timer] Connect watchdog bark to NMI by Timothy Chen · 3 years, 8 months ago
- 7c3de6e [util] Prep work for shadow reset impelemtation by Timothy Chen · 3 years, 8 months ago
- 914bdad [script/dvsim] Separate publish report from dvsim flow [PART2] by Cindy Chen · 3 years, 8 months ago
- 2b0155a [rv_core_ibex] Minor clean-up by Timothy Chen · 3 years, 8 months ago
- dcc5f9f [ipgen] Initial commit of IP generation tool by Philipp Wagner · 4 years ago
- 52bce9f [nmi_gen] remove the nmi_gen dummy module by Michael Schaffner · 3 years, 8 months ago
- 97fe6a8 [top_englishbreakfast] Use rom_ctrl, not a raw memory instance by Rupert Swarbrick · 3 years, 8 months ago
- 127b109 [topgen] Pull the 'clocks' code into a separate class in topgen by Rupert Swarbrick · 3 years, 8 months ago
- 9d4ed87 [top] Correct parameter defaults in top_earlgrey by Timothy Chen · 3 years, 8 months ago
- 1a5d53a [alert_handler] Make critical alert handler CSRs shadowed regs by Michael Schaffner · 3 years, 10 months ago
- f69b700 [dv] handle multireg with unevenly divided fields by Weicai Yang · 3 years, 8 months ago
- 00f6d78 [dv] Use array for multi-reg in RAL model by Weicai Yang · 3 years, 9 months ago
- 704bf01 formatter: Expand verible-format-allowlist by Lukasz Dalek · 3 years, 8 months ago
- a2675f9 [top] Split long parameter lines in toplevel.sv.tpl by Rupert Swarbrick · 3 years, 8 months ago
- b789cf5 [reggen] Add "REG_RESVAL" defines to generated C headers by Rupert Swarbrick · 3 years, 9 months ago
- bd46e9c [vendor.py] Enable overriding of upstream.rev by Philipp Wagner · 3 years, 8 months ago
- 1d8b960 [top, dv, sw] Various adjustments to accommodate rv_core_ibex peripheral by Timothy Chen · 3 years, 9 months ago
- 02e982f [topgen] Updates for declaring memory regions within IPs by Michael Schaffner · 3 years, 9 months ago
- 0fd914d [dv/rstmgr] Create dv collateral by Guillermo Maturana · 3 years, 9 months ago
- c9f99d8 [util] Add ability to declare parameter level directly from top_earlgrey.hjson by Timothy Chen · 3 years, 9 months ago
- 70151fe [keymgr] Add otbn sideload and expand to 384-bit sideload key support by Timothy Chen · 3 years, 9 months ago
- 0f6e781 [otbn] fork rsa verify code for 3k version by Felix Miller · 3 years, 10 months ago
- a753390 [xbar/dv] Fix name search issue by Weicai Yang · 3 years, 9 months ago
- a06d709 [lc_ctrl/otp_ctrl] Check whether tokens have been provisioned by Michael Schaffner · 3 years, 9 months ago
- 27557de [ast] Mostly updates to internal code by Jacob Levy · 3 years, 9 months ago
- 78964d7 [lc_ctrl] Fix the cshake byte order in the constants generation script by Michael Schaffner · 3 years, 9 months ago
- 31fb03b [check_tool_requirements] Add semver parser for Ninja by Michael Schaffner · 3 years, 9 months ago
- 690d732 [rv_dm] Make the RV_DM a comportable module by Michael Schaffner · 3 years, 9 months ago
- d0cbfad [reggen] Pair up clock and reset signals by Rupert Swarbrick · 3 years, 9 months ago
- da12563 [sw] proof of concept of address translation idea by Timothy Chen · 3 years, 9 months ago
- 244a8dd [sensor_ctrl, ast] Preparation for sensor_ctrl d2 by Timothy Chen · 4 years ago
- 40a80bb formatter: Expand verible-format-allowlist by Lukasz Dalek · 3 years, 9 months ago
- 674628a [tlul] Add byte level handling for integrity by Timothy Chen · 3 years, 9 months ago
- 3e3cb48 [top] Integrate rv_core_ibex_peri into earlgrey by Timothy Chen · 3 years, 9 months ago
- 82c2181 [otp_ctrl] Add bit remapping option to OTP image generation script by Michael Schaffner · 3 years, 9 months ago