- 6211349 [hw,doc] Add human-readable name to all blocks by Andreas Kurth · 2 years ago
- f8500c0 [hw,doc] Add one-paragraph descriptions to all blocks by Andreas Kurth · 2 years ago
- 218294b [hw,doc] Add one-line descriptions to all blocks by Andreas Kurth · 2 years ago
- 2608b59 [reggen] Move prj metadata into main hjson by Michael Schaffner · 2 years ago
- f58cda5 [aes] Rework SecAllowForcingMasks parameter by Pirmin Vogel · 2 years, 7 months ago
- 70a63d4 [aes] Clear START trigger when ignoring it by Pirmin Vogel · 2 years, 11 months ago
- 6a18e34 [top] update transactional modules to use mubi for idle by Timothy Chen · 2 years, 11 months ago
- c34153e [aes] Make IV register readable for software by Pirmin Vogel · 3 years ago
- c8b6231 [aes] Convert Masking and SBoxImpl parameters to Sec parameters by Pirmin Vogel · 3 years ago
- 72f98d6 [aes/doc] Update documentation based on D2S review by Pirmin Vogel · 3 years ago
- 9ac6054 [aes] Add list of countermeasures for D2S sign-off by Pirmin Vogel · 3 years ago
- fa35641 [aes] De-assert idle after a new key becomes ready, flop idle_o by Pirmin Vogel · 3 years ago
- 553759a [aes] Use one-hot encoding for OPERATION field in main control register by Pirmin Vogel · 3 years ago
- 71a675a [aes] Fix REGWEN usage for auxiliary control register by Pirmin Vogel · 3 years ago
- 40203d2 [aes] Fix CSR test exclusions for key, IV and data input registers by Pirmin Vogel · 3 years ago
- 86eaf5e [aes] Add lockable bit to force PRNG reseeding upon touching the key by Pirmin Vogel · 3 years ago
- 60df4fb [aes/rtl] Enable controlling the reseeding rate of the masking PRNG by Pirmin Vogel · 3 years, 1 month ago
- 1762693 [doc] List common bus integrity CM in all block Hjsons by Michael Schaffner · 3 years, 1 month ago
- 673acae [aes/rtl] Span permutation inside masking PRNG across all LFSRs by Pirmin Vogel · 3 years, 3 months ago
- 0427b0d [aes] Improve rendering of register table in docs by Philipp Wagner · 3 years, 3 months ago
- 992f933 [aes] Add support for key sideload by Pirmin Vogel · 3 years, 5 months ago
- c473f70 [aes] Use separate subreg prims for fields of shadowed control reg by Pirmin Vogel · 3 years, 5 months ago
- 5aa249f [topgen] Be explicit about where hint clocks get connected by Rupert Swarbrick · 3 years, 6 months ago
- d0cbfad [reggen] Pair up clock and reset signals by Rupert Swarbrick · 3 years, 7 months ago
- 2f0c420 [aes] Wire up bus integrity alert by Michael Schaffner · 3 years, 8 months ago
- 116ecac [aes] Use separate permutation for clearing second share of masked regs by Pirmin Vogel · 3 years, 10 months ago
- 4091ef7 [aes/doc] Add missing reset values for key, IV and data registers by Pirmin Vogel · 3 years, 10 months ago
- 7ec403a [aes] Specify missing reset values for shadowed control register by Pirmin Vogel · 3 years, 10 months ago
- 46339bb [aes] Doc clearing sequence upon reset and align STATUS reg reset value by Pirmin Vogel · 3 years, 10 months ago
- 4ac0a9d [alerts] Fully connect alert async on parameters by Michael Schaffner · 3 years, 11 months ago
- 6c83129 [reggen/comport] Syntax for multiple interfaces in a peripheral by Rupert Swarbrick · 4 years ago
- 95cea45 [aes] Interface CSRNG through EDN by Pirmin Vogel · 3 years, 11 months ago
- 144ca84 [aes] Add life cycle escalation signal by Pirmin Vogel · 4 years ago
- e9fd2bf [aes] Use sparse encodings for additional control signals by Pirmin Vogel · 4 years ago
- 6f70ed9 [aes] Use sparse encodings for handshake signals by Pirmin Vogel · 4 years ago
- d31b0cc [aes] Drive random netlist constants from top_*_rnd_cnst_pkg.sv by Pirmin Vogel · 4 years ago
- e6ca872 [aes] Enable domain-oriented masking by Pirmin Vogel · 4 years ago
- 650bd04 [dv/alert] update shadow_reg alert naming in DV by Cindy Chen · 4 years ago
- fd3708a [aes] Protect round counter against fault injection by Pirmin Vogel · 4 years ago
- 4c22cf2 [aes] Align alert naming and signaling with latest guidance by Pirmin Vogel · 4 years ago
- 275dd04 [aes] Use sparse encodings for MUX selector signals by Pirmin Vogel · 4 years ago
- 26d59d5 [aes] Add status bit indicating lost output data, fix scoreboard by Pirmin Vogel · 4 years ago
- bc40da4 [aes] Simplify clearing functionality by Pirmin Vogel · 4 years ago
- bdb63e9 [aes] Add missing reset value for START trigger by Pirmin Vogel · 4 years ago
- bbb1e16 [aes] Add missing CSR exclusion for ALERT_RECOVERABLE status bit by Pirmin Vogel · 4 years ago
- c90e0c5 [aes] Use sparse encodings for FSMs, trigger alert for invalid states by Pirmin Vogel · 4 years ago
- d22acd9 [aes] Add reset to data, IV, state and key registers by Pirmin Vogel · 4 years, 1 month ago
- 62f79b8 [aes] Parameterize LFSR default seeds and perms by Pirmin Vogel · 4 years, 2 months ago
- 92e9ebb [aes] Use fresh, random intermediate masks in "noreuse" Canright S-Box by Pirmin Vogel · 4 years, 2 months ago
- 998dc7d [aes/doc] Clarify that SW must poll the Status Reg after sending a trigger by Pirmin Vogel · 4 years, 2 months ago
- 20ae79e [top] Turn on aes masking by Timothy Chen · 4 years, 3 months ago
- 4429c36 [aes] Add parameter to allow forcing all-zero masks during SCA analysis by Pirmin Vogel · 4 years, 4 months ago
- 0799dba [aes] Add initial version of PRNG for cipher core masking by Pirmin Vogel · 4 years, 4 months ago
- ca70653 [aes] Add module parameters to hjson by Pirmin Vogel · 4 years, 4 months ago
- d5407d5 [dv/shadow_reg] update sequence for storage error by Cindy Chen · 4 years, 5 months ago
- 3dc24fc [aes] Add second alert signal by Pirmin Vogel · 4 years, 6 months ago
- ded9da4 [aes] Provide the initial key in two shares for security hardening by Pirmin Vogel · 4 years, 5 months ago
- d8f8e3e [aes] Add support for CFB-128 and OFB modes by Pirmin Vogel · 4 years, 6 months ago
- 42610c0 [aes] Clear all reg status trackers on writes to control reg by Pirmin Vogel · 4 years, 6 months ago
- be4bcb7 [aes] Add shadow CTRL register, interface with alert handler by Pirmin Vogel · 4 years, 9 months ago
- a2d411d [aes] Add idle hint signal for clkmgr by Pirmin Vogel · 4 years, 6 months ago
- 22cb74d [aes] Clarify documentation by Pirmin Vogel · 4 years, 7 months ago
- f2eb1d5 [aes/dv] Adapt CSR test exclusions by Pirmin Vogel · 4 years, 9 months ago
- 96386a1 [aes] Clear internal registers with pseudo-random data by Pirmin Vogel · 4 years, 10 months ago
- 94671dd [aes] Add support for CBC and CTR modes by Pirmin Vogel · 5 years ago
- c3811a0 [dv] Chip CSR tests with automated exclusions by Srikrishna Iyer · 4 years, 11 months ago
- 2c0e975 [aes] Add MANUAL_OPERATION bit to control register by Pirmin Vogel · 5 years ago
- 6f10562 [aes/rtl] Rework naming and use of cipher operation signal by Pirmin Vogel · 5 years ago
- 0d99156 [aes/doc] Clarify interaction with CSRs by Pirmin Vogel · 5 years ago
- 7b5bedf [aes/rtl] Make rw/hro fields of CTRL reg observable to software by Pirmin Vogel · 5 years ago
- edf3786 [aes] Correct reset value and meaning of IDLE bit in status register by Pirmin Vogel · 5 years ago
- 15b0749 [aes/doc] Clarify that the order of multireg accesses does not matter by Pirmin Vogel · 5 years ago
- 76463db [aes] Make the trigger register write-only for software by Pirmin Vogel · 5 years ago
- 64a0af5 [aes] Ignore writes to control register when not idle by Pirmin Vogel · 5 years ago
- f53657c [aes] Ignore writes to key register when not idle by Pirmin Vogel · 5 years ago
- 9107f84 [aes] Allow hardware to clear input data and key registers by Pirmin Vogel · 5 years ago
- 202f1f2 [aes/doc] Minor updates and clarifications by Greg Chadwick · 5 years ago
- 973273f [aes] Fix .hjson by Pirmin Vogel · 5 years ago
- a9acdce [hw/ip] Move configuration files by Tobias Wölfel · 5 years ago[Renamed from hw/ip/aes/doc/aes.hjson]
- a17fb6f [doc] remove non-ASCII characters by Scott Johnson · 5 years ago
- dff3bd8 [aes/rtl] Add key and output clear bits to trigger reg by Pirmin Vogel · 5 years ago
- a6413a0 [aes] Overwrite invalid key length values by Pirmin Vogel · 5 years ago
- 99f0989 [aes] Add AES module by Pirmin Vogel · 5 years ago