blob: 50ddac7e869e0f785f18c39b10376f1447aef149 [file] [log] [blame]
Michael Schaffner3d55aa02019-10-24 08:30:11 -07001From 393329b704d63a6fa150e9d4eb54c81dec7edae3 Mon Sep 17 00:00:00 2001
2From: Michael Schaffner <msf@google.com>
3Date: Thu, 17 Oct 2019 15:52:49 -0700
4Subject: [PATCH 3/9] [lint/cleanup] Name blocks, align blocking structure
5
6---
7 src/dm_csrs.sv | 9 +++++----
8 src/dm_mem.sv | 16 +++++++++-------
9 src/dm_pkg.sv | 2 +-
10 src/dm_sba.sv | 6 +++---
11 src/dm_top.sv | 2 +-
12 src/dmi_cdc.sv | 3 ++-
13 src/dmi_jtag.sv | 10 ++++++----
14 src/dmi_jtag_tap.sv | 21 +++++++++++----------
15 8 files changed, 38 insertions(+), 31 deletions(-)
16
17diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv
18index 808a95d..3253173 100644
19--- a/src/dm_csrs.sv
20+++ b/src/dm_csrs.sv
21@@ -102,7 +102,7 @@ module dm_csrs #(
22 logic [32-1:0] halted_flat3;
23
24 // haltsum0
25- always_comb begin
26+ always_comb begin : p_haltsum0
27 halted = '0;
28 halted[NrHarts-1:0] = halted_i;
29 halted_reshaped0 = halted;
30@@ -433,8 +433,9 @@ module dm_csrs #(
31 end
32
33 // update data registers
34- if (data_valid_i)
35+ if (data_valid_i) begin
36 data_d = data_i;
37+ end
38
39 // set the havereset flag when we did a ndmreset
40 if (ndmreset_o) begin
41@@ -482,7 +483,7 @@ module dm_csrs #(
42 end
43
44 // output multiplexer
45- always_comb begin
46+ always_comb begin : p_outmux
47 selected_hart = hartsel_o[HartSelLen-1:0];
48 // default assignment
49 haltreq_o = '0;
50@@ -599,4 +600,4 @@ module dm_csrs #(
51 `endif
52 //pragma translate_on
53
54-endmodule
55+endmodule : dm_csrs
56diff --git a/src/dm_mem.sv b/src/dm_mem.sv
57index 1ecc878..12057f3 100644
58--- a/src/dm_mem.sv
59+++ b/src/dm_mem.sv
60@@ -110,7 +110,7 @@ module dm_mem #(
61 state_e state_d, state_q;
62
63 // hart ctrl queue
64- always_comb begin
65+ always_comb begin : p_hart_ctrl_queue
66 cmderror_valid_o = 1'b0;
67 cmderror_o = dm::CmdErrNone;
68 state_d = state_q;
69@@ -142,15 +142,17 @@ module dm_mem #(
70 cmdbusy_o = 1'b1;
71 go = 1'b1;
72 // the thread is now executing the command, track its state
73- if (going)
74+ if (going) begin
75 state_d = CmdExecuting;
76+ end
77 end
78
79 Resume: begin
80 cmdbusy_o = 1'b1;
81 resume = 1'b1;
82- if (resuming_o[hartsel_i])
83+ if (resuming_o[hartsel_i]) begin
84 state_d = Idle;
85+ end
86 end
87
88 CmdExecuting: begin
89@@ -177,7 +179,7 @@ module dm_mem #(
90 end
91
92 // read/write logic
93- always_comb begin
94+ always_comb begin : p_rw_logic
95 automatic logic [63:0] data_bits;
96
97 halted_d = halted_q;
98@@ -292,7 +294,7 @@ module dm_mem #(
99 data_o = data_bits;
100 end
101
102- always_comb begin : abstract_cmd_rom
103+ always_comb begin : p_abstract_cmd_rom
104 // this abstract command is currently unsupported
105 unsupported_command = 1'b0;
106 // default memory
107@@ -437,7 +439,7 @@ module dm_mem #(
108 assign fwd_rom_d = (addr_i[DbgAddressBits-1:0] >= dm::HaltAddress[DbgAddressBits-1:0]) ?
109 1'b1 : 1'b0;
110
111- always_ff @(posedge clk_i or negedge rst_ni) begin
112+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
113 if (!rst_ni) begin
114 fwd_rom_q <= 1'b0;
115 rdata_q <= '0;
116@@ -463,4 +465,4 @@ module dm_mem #(
117 end
118 end
119
120-endmodule
121+endmodule : dm_mem
122diff --git a/src/dm_pkg.sv b/src/dm_pkg.sv
123index 49e77be..341e9ab 100644
124--- a/src/dm_pkg.sv
125+++ b/src/dm_pkg.sv
126@@ -383,4 +383,4 @@ package dm;
127 return 32'h00000000;
128 endfunction
129
130-endpackage
131+endpackage : dm
132diff --git a/src/dm_sba.sv b/src/dm_sba.sv
133index fa9d401..12b1951 100644
134--- a/src/dm_sba.sv
135+++ b/src/dm_sba.sv
136@@ -63,7 +63,7 @@ module dm_sba #(
137
138 assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;
139
140- always_comb begin
141+ always_comb begin : p_fsm
142 req = 1'b0;
143 address = sbaddress_i;
144 we = 1'b0;
145@@ -142,7 +142,7 @@ module dm_sba #(
146 // further error handling should go here ...
147 end
148
149- always_ff @(posedge clk_i or negedge rst_ni) begin
150+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
151 if (!rst_ni) begin
152 state_q <= Idle;
153 end else begin
154@@ -169,4 +169,4 @@ module dm_sba #(
155 `endif
156 //pragma translate_on
157
158-endmodule
159+endmodule : dm_sba
160diff --git a/src/dm_top.sv b/src/dm_top.sv
161index 03ac112..6c7fa49 100644
162--- a/src/dm_top.sv
163+++ b/src/dm_top.sv
164@@ -219,4 +219,4 @@ module dm_top #(
165 end
166 `endif
167
168-endmodule
169+endmodule : dm_top
170diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
171index ba856df..4665c91 100644
172--- a/src/dmi_cdc.sv
173+++ b/src/dmi_cdc.sv
174@@ -69,4 +69,5 @@ module dmi_cdc (
175 .dst_valid_o ( jtag_dmi_valid_o ),
176 .dst_ready_i ( jtag_dmi_ready_i )
177 );
178-endmodule
179+
180+endmodule : dmi_cdc
181diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
182index 083ed59..5642dc1 100644
183--- a/src/dmi_jtag.sv
184+++ b/src/dmi_jtag.sv
185@@ -88,7 +88,7 @@ module dmi_jtag #(
186 logic error_dmi_busy;
187 dmi_error_e error_d, error_q;
188
189- always_comb begin
190+ always_comb begin : p_fsm
191 error_dmi_busy = 1'b0;
192 // default assignments
193 state_d = state_q;
194@@ -170,7 +170,7 @@ module dmi_jtag #(
195 // shift register
196 assign dmi_tdo = dr_q[0];
197
198- always_comb begin
199+ always_comb begin : p_shift
200 dr_d = dr_q;
201
202 if (capture_dr) begin
203@@ -185,7 +185,9 @@ module dmi_jtag #(
204 end
205
206 if (shift_dr) begin
207- if (dmi_access) dr_d = {dmi_tdi, dr_q[$bits(dr_q)-1:1]};
208+ if (dmi_access) begin
209+ dr_d = {dmi_tdi, dr_q[$bits(dr_q)-1:1]};
210+ end
211 end
212
213 if (test_logic_reset) begin
214@@ -259,4 +261,4 @@ module dmi_jtag #(
215 .core_dmi_valid_i ( dmi_resp_valid_i )
216 );
217
218-endmodule
219+endmodule : dmi_jtag
220diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv
221index 19d876f..bd447f6 100644
222--- a/src/dmi_jtag_tap.sv
223+++ b/src/dmi_jtag_tap.sv
224@@ -88,7 +88,7 @@ module dmi_jtag_tap #(
225 ir_reg_e jtag_ir_d, jtag_ir_q; // IR register -> this gets captured from shift register upon update_ir
226 logic capture_ir, shift_ir, pause_ir, update_ir;
227
228- always_comb begin
229+ always_comb begin : p_jtag
230 jtag_ir_shift_d = jtag_ir_shift_q;
231 jtag_ir_d = jtag_ir_q;
232
233@@ -114,7 +114,7 @@ module dmi_jtag_tap #(
234 end
235 end
236
237- always_ff @(posedge tck_i, negedge trst_ni) begin
238+ always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
239 if (!trst_ni) begin
240 jtag_ir_shift_q <= '0;
241 jtag_ir_q <= IDCODE;
242@@ -138,7 +138,7 @@ module dmi_jtag_tap #(
243
244 assign dmi_reset_o = dtmcs_q.dmireset;
245
246- always_comb begin
247+ always_comb begin : p_tap_dr
248 idcode_d = idcode_q;
249 bypass_d = bypass_q;
250 dtmcs_d = dtmcs_q;
251@@ -175,7 +175,7 @@ module dmi_jtag_tap #(
252 // ----------------
253 // Data reg select
254 // ----------------
255- always_comb begin
256+ always_comb begin : p_data_reg_sel
257 dmi_access_o = 1'b0;
258 dtmcs_select_o = 1'b0;
259 idcode_select = 1'b0;
260@@ -195,7 +195,7 @@ module dmi_jtag_tap #(
261 // ----------------
262 logic tdo_mux;
263
264- always_comb begin
265+ always_comb begin : p_out_sel
266 // we are shifting out the IR register
267 if (shift_ir) begin
268 tdo_mux = jtag_ir_shift_q[0];
269@@ -210,7 +210,9 @@ module dmi_jtag_tap #(
270 end
271 end
272
273+ // ----------------
274 // DFT
275+ // ----------------
276 logic tck_n, tck_ni;
277
278 cluster_clock_inverter i_tck_inv (
279@@ -226,7 +228,7 @@ module dmi_jtag_tap #(
280 );
281
282 // TDO changes state at negative edge of TCK
283- always_ff @(posedge tck_n, negedge trst_ni) begin
284+ always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
285 if (!trst_ni) begin
286 td_o <= 1'b0;
287 tdo_oe_o <= 1'b0;
288@@ -239,7 +241,7 @@ module dmi_jtag_tap #(
289 // TAP FSM
290 // ----------------
291 // Determination of next state; purely combinatorial
292- always_comb begin
293+ always_comb begin : p_tap_fsm
294 test_logic_reset_o = 1'b0;
295
296 capture_dr_o = 1'b0;
297@@ -326,8 +328,7 @@ module dmi_jtag_tap #(
298 endcase
299 end
300
301-
302- always_ff @(posedge tck_i or negedge trst_ni) begin
303+ always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
304 if (!trst_ni) begin
305 tap_state_q <= RunTestIdle;
306 idcode_q <= IdcodeValue;
307@@ -341,4 +342,4 @@ module dmi_jtag_tap #(
308 end
309 end
310
311-endmodule
312+endmodule : dmi_jtag_tap
313--
Michael Schaffner051ce492019-10-29 10:50:02 -07003142.24.0.rc0.303.g954a862665-goog
Michael Schaffner3d55aa02019-10-24 08:30:11 -0700315