blob: 50ddac7e869e0f785f18c39b10376f1447aef149 [file] [log] [blame]
From 393329b704d63a6fa150e9d4eb54c81dec7edae3 Mon Sep 17 00:00:00 2001
From: Michael Schaffner <msf@google.com>
Date: Thu, 17 Oct 2019 15:52:49 -0700
Subject: [PATCH 3/9] [lint/cleanup] Name blocks, align blocking structure
---
src/dm_csrs.sv | 9 +++++----
src/dm_mem.sv | 16 +++++++++-------
src/dm_pkg.sv | 2 +-
src/dm_sba.sv | 6 +++---
src/dm_top.sv | 2 +-
src/dmi_cdc.sv | 3 ++-
src/dmi_jtag.sv | 10 ++++++----
src/dmi_jtag_tap.sv | 21 +++++++++++----------
8 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv
index 808a95d..3253173 100644
--- a/src/dm_csrs.sv
+++ b/src/dm_csrs.sv
@@ -102,7 +102,7 @@ module dm_csrs #(
logic [32-1:0] halted_flat3;
// haltsum0
- always_comb begin
+ always_comb begin : p_haltsum0
halted = '0;
halted[NrHarts-1:0] = halted_i;
halted_reshaped0 = halted;
@@ -433,8 +433,9 @@ module dm_csrs #(
end
// update data registers
- if (data_valid_i)
+ if (data_valid_i) begin
data_d = data_i;
+ end
// set the havereset flag when we did a ndmreset
if (ndmreset_o) begin
@@ -482,7 +483,7 @@ module dm_csrs #(
end
// output multiplexer
- always_comb begin
+ always_comb begin : p_outmux
selected_hart = hartsel_o[HartSelLen-1:0];
// default assignment
haltreq_o = '0;
@@ -599,4 +600,4 @@ module dm_csrs #(
`endif
//pragma translate_on
-endmodule
+endmodule : dm_csrs
diff --git a/src/dm_mem.sv b/src/dm_mem.sv
index 1ecc878..12057f3 100644
--- a/src/dm_mem.sv
+++ b/src/dm_mem.sv
@@ -110,7 +110,7 @@ module dm_mem #(
state_e state_d, state_q;
// hart ctrl queue
- always_comb begin
+ always_comb begin : p_hart_ctrl_queue
cmderror_valid_o = 1'b0;
cmderror_o = dm::CmdErrNone;
state_d = state_q;
@@ -142,15 +142,17 @@ module dm_mem #(
cmdbusy_o = 1'b1;
go = 1'b1;
// the thread is now executing the command, track its state
- if (going)
+ if (going) begin
state_d = CmdExecuting;
+ end
end
Resume: begin
cmdbusy_o = 1'b1;
resume = 1'b1;
- if (resuming_o[hartsel_i])
+ if (resuming_o[hartsel_i]) begin
state_d = Idle;
+ end
end
CmdExecuting: begin
@@ -177,7 +179,7 @@ module dm_mem #(
end
// read/write logic
- always_comb begin
+ always_comb begin : p_rw_logic
automatic logic [63:0] data_bits;
halted_d = halted_q;
@@ -292,7 +294,7 @@ module dm_mem #(
data_o = data_bits;
end
- always_comb begin : abstract_cmd_rom
+ always_comb begin : p_abstract_cmd_rom
// this abstract command is currently unsupported
unsupported_command = 1'b0;
// default memory
@@ -437,7 +439,7 @@ module dm_mem #(
assign fwd_rom_d = (addr_i[DbgAddressBits-1:0] >= dm::HaltAddress[DbgAddressBits-1:0]) ?
1'b1 : 1'b0;
- always_ff @(posedge clk_i or negedge rst_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
fwd_rom_q <= 1'b0;
rdata_q <= '0;
@@ -463,4 +465,4 @@ module dm_mem #(
end
end
-endmodule
+endmodule : dm_mem
diff --git a/src/dm_pkg.sv b/src/dm_pkg.sv
index 49e77be..341e9ab 100644
--- a/src/dm_pkg.sv
+++ b/src/dm_pkg.sv
@@ -383,4 +383,4 @@ package dm;
return 32'h00000000;
endfunction
-endpackage
+endpackage : dm
diff --git a/src/dm_sba.sv b/src/dm_sba.sv
index fa9d401..12b1951 100644
--- a/src/dm_sba.sv
+++ b/src/dm_sba.sv
@@ -63,7 +63,7 @@ module dm_sba #(
assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;
- always_comb begin
+ always_comb begin : p_fsm
req = 1'b0;
address = sbaddress_i;
we = 1'b0;
@@ -142,7 +142,7 @@ module dm_sba #(
// further error handling should go here ...
end
- always_ff @(posedge clk_i or negedge rst_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
state_q <= Idle;
end else begin
@@ -169,4 +169,4 @@ module dm_sba #(
`endif
//pragma translate_on
-endmodule
+endmodule : dm_sba
diff --git a/src/dm_top.sv b/src/dm_top.sv
index 03ac112..6c7fa49 100644
--- a/src/dm_top.sv
+++ b/src/dm_top.sv
@@ -219,4 +219,4 @@ module dm_top #(
end
`endif
-endmodule
+endmodule : dm_top
diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv
index ba856df..4665c91 100644
--- a/src/dmi_cdc.sv
+++ b/src/dmi_cdc.sv
@@ -69,4 +69,5 @@ module dmi_cdc (
.dst_valid_o ( jtag_dmi_valid_o ),
.dst_ready_i ( jtag_dmi_ready_i )
);
-endmodule
+
+endmodule : dmi_cdc
diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
index 083ed59..5642dc1 100644
--- a/src/dmi_jtag.sv
+++ b/src/dmi_jtag.sv
@@ -88,7 +88,7 @@ module dmi_jtag #(
logic error_dmi_busy;
dmi_error_e error_d, error_q;
- always_comb begin
+ always_comb begin : p_fsm
error_dmi_busy = 1'b0;
// default assignments
state_d = state_q;
@@ -170,7 +170,7 @@ module dmi_jtag #(
// shift register
assign dmi_tdo = dr_q[0];
- always_comb begin
+ always_comb begin : p_shift
dr_d = dr_q;
if (capture_dr) begin
@@ -185,7 +185,9 @@ module dmi_jtag #(
end
if (shift_dr) begin
- if (dmi_access) dr_d = {dmi_tdi, dr_q[$bits(dr_q)-1:1]};
+ if (dmi_access) begin
+ dr_d = {dmi_tdi, dr_q[$bits(dr_q)-1:1]};
+ end
end
if (test_logic_reset) begin
@@ -259,4 +261,4 @@ module dmi_jtag #(
.core_dmi_valid_i ( dmi_resp_valid_i )
);
-endmodule
+endmodule : dmi_jtag
diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv
index 19d876f..bd447f6 100644
--- a/src/dmi_jtag_tap.sv
+++ b/src/dmi_jtag_tap.sv
@@ -88,7 +88,7 @@ module dmi_jtag_tap #(
ir_reg_e jtag_ir_d, jtag_ir_q; // IR register -> this gets captured from shift register upon update_ir
logic capture_ir, shift_ir, pause_ir, update_ir;
- always_comb begin
+ always_comb begin : p_jtag
jtag_ir_shift_d = jtag_ir_shift_q;
jtag_ir_d = jtag_ir_q;
@@ -114,7 +114,7 @@ module dmi_jtag_tap #(
end
end
- always_ff @(posedge tck_i, negedge trst_ni) begin
+ always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
if (!trst_ni) begin
jtag_ir_shift_q <= '0;
jtag_ir_q <= IDCODE;
@@ -138,7 +138,7 @@ module dmi_jtag_tap #(
assign dmi_reset_o = dtmcs_q.dmireset;
- always_comb begin
+ always_comb begin : p_tap_dr
idcode_d = idcode_q;
bypass_d = bypass_q;
dtmcs_d = dtmcs_q;
@@ -175,7 +175,7 @@ module dmi_jtag_tap #(
// ----------------
// Data reg select
// ----------------
- always_comb begin
+ always_comb begin : p_data_reg_sel
dmi_access_o = 1'b0;
dtmcs_select_o = 1'b0;
idcode_select = 1'b0;
@@ -195,7 +195,7 @@ module dmi_jtag_tap #(
// ----------------
logic tdo_mux;
- always_comb begin
+ always_comb begin : p_out_sel
// we are shifting out the IR register
if (shift_ir) begin
tdo_mux = jtag_ir_shift_q[0];
@@ -210,7 +210,9 @@ module dmi_jtag_tap #(
end
end
+ // ----------------
// DFT
+ // ----------------
logic tck_n, tck_ni;
cluster_clock_inverter i_tck_inv (
@@ -226,7 +228,7 @@ module dmi_jtag_tap #(
);
// TDO changes state at negative edge of TCK
- always_ff @(posedge tck_n, negedge trst_ni) begin
+ always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
if (!trst_ni) begin
td_o <= 1'b0;
tdo_oe_o <= 1'b0;
@@ -239,7 +241,7 @@ module dmi_jtag_tap #(
// TAP FSM
// ----------------
// Determination of next state; purely combinatorial
- always_comb begin
+ always_comb begin : p_tap_fsm
test_logic_reset_o = 1'b0;
capture_dr_o = 1'b0;
@@ -326,8 +328,7 @@ module dmi_jtag_tap #(
endcase
end
-
- always_ff @(posedge tck_i or negedge trst_ni) begin
+ always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
if (!trst_ni) begin
tap_state_q <= RunTestIdle;
idcode_q <= IdcodeValue;
@@ -341,4 +342,4 @@ module dmi_jtag_tap #(
end
end
-endmodule
+endmodule : dmi_jtag_tap
--
2.24.0.rc0.303.g954a862665-goog