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opensecura / 3p / lowrisc / opentitan / a387503a9f7a2a08be8abcc9aaa6fd12aceb5b81 / . / hw / top_earlgrey / data / xbar_peri.hjson
blob: a5f9269c4cd915cc6769dad33da3f1f5fde4fd93 [file] [log] [blame]
Sam Elliott45fb1c62020-06-02 18:18:54 +0100[diff] [blame]1// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]4{ name: "peri",
5 type: "xbar",
6 clock_primary: "clk_peri_i", // Main clock, used in sockets
7 reset_primary: "rst_peri_ni", // Main reset, used in sockets
8
9 nodes: [
10 { name: "main",
11 type: "host",
12 clock: "clk_peri_i",
13 reset: "rst_peri_ni",
14 xbar: "true",
15 pipeline: "false"
16
17 },
Timothy Chen2971a1e2021-01-21 16:00:01 -0800[diff] [blame]18 { name: "uart0",
19 type: "device",
20 clock: "clk_peri_i",
21 reset: "rst_peri_ni",
22 pipeline: "false"
23 },
24 { name: "uart1",
25 type: "device",
26 clock: "clk_peri_i",
27 reset: "rst_peri_ni",
28 pipeline: "false"
29 },
30 { name: "uart2",
31 type: "device",
32 clock: "clk_peri_i",
33 reset: "rst_peri_ni",
34 pipeline: "false"
35 },
36 { name: "uart3",
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]37 type: "device",
38 clock: "clk_peri_i",
39 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]40 pipeline: "false"
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]41 },
Timothy Chenb0f55772021-02-01 15:43:47 -0800[diff] [blame]42 { name: "i2c0",
43 type: "device",
44 clock: "clk_peri_i",
45 reset: "rst_peri_ni",
46 pipeline: "false"
47 },
48 { name: "i2c1",
49 type: "device",
50 clock: "clk_peri_i",
51 reset: "rst_peri_ni",
52 pipeline: "false"
53 },
54 { name: "i2c2",
55 type: "device",
56 clock: "clk_peri_i",
57 reset: "rst_peri_ni",
58 pipeline: "false"
59 },
60 { name: "pattgen",
61 type: "device",
62 clock: "clk_peri_i",
63 reset: "rst_peri_ni",
64 pipeline: "false"
65 },
Martin Lueker-Boden0d63fe02021-03-10 17:30:37 -0800[diff] [blame]66 { name: "pwm_aon",
67 type: "device",
68 clock: "clk_peri_i",
69 reset: "rst_peri_ni",
70 pipeline: "false"
71 },
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]72 { name: "gpio",
73 type: "device",
74 clock: "clk_peri_i",
75 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]76 pipeline: "false"
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]77 },
78 { name: "spi_device",
79 type: "device",
80 clock: "clk_peri_i",
81 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]82 pipeline: "false"
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]83 },
Michael Schaffnerdbd087e2021-02-12 17:58:30 -0800[diff] [blame]84 { name: "spi_host0",
85 type: "device",
86 clock: "clk_peri_i",
87 reset: "rst_peri_ni",
88 pipeline: "false"
89 },
90 { name: "spi_host1",
91 type: "device",
92 clock: "clk_peri_i",
93 reset: "rst_peri_ni",
94 pipeline: "false"
95 },
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]96 { name: "rv_timer",
97 type: "device",
98 clock: "clk_peri_i",
99 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]100 pipeline: "false"
Pirmin Vogelea91b302020-01-14 18:53:01 +0000[diff] [blame]101 },
102 { name: "usbdev",
103 type: "device",
104 clock: "clk_peri_i",
105 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]106 pipeline: "false"
Timothy Chen163050b2020-04-13 23:29:29 -0700[diff] [blame]107 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]108 { name: "pwrmgr_aon",
Timothy Chen163050b2020-04-13 23:29:29 -0700[diff] [blame]109 type: "device",
110 clock: "clk_peri_i",
111 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]112 pipeline: "false"
Timothy Chenc59f7012020-04-16 19:11:42 -0700[diff] [blame]113 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]114 { name: "rstmgr_aon",
Timothy Chenc59f7012020-04-16 19:11:42 -0700[diff] [blame]115 type: "device",
116 clock: "clk_peri_i",
117 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]118 pipeline: "false"
Timothy Chenf56c1b52020-04-28 17:00:43 -0700[diff] [blame]119 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]120 { name: "clkmgr_aon",
Timothy Chenf56c1b52020-04-28 17:00:43 -0700[diff] [blame]121 type: "device",
122 clock: "clk_peri_i",
123 reset: "rst_peri_ni",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]124 pipeline: "false"
Timothy Chen2c9e1a92020-06-29 15:03:25 -0700[diff] [blame]125 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]126 { name: "pinmux_aon",
127 type: "device",
128 clock: "clk_peri_i",
129 reset: "rst_peri_ni",
130 pipeline: "false"
131 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]132 { name: "ram_ret_aon",
Timothy Chen2c9e1a92020-06-29 15:03:25 -0700[diff] [blame]133 type: "device",
134 clock: "clk_peri_i",
135 reset: "rst_peri_ni",
136 pipeline: "false",
137 },
Michael Schaffner8b0b5b12021-07-08 12:28:10 -0700[diff] [blame]138 { name: "otp_ctrl.core",
139 type: "device",
140 clock: "clk_peri_i",
141 reset: "rst_peri_ni",
142 pipeline: "false"
143 },
144 { name: "otp_ctrl.prim",
Michael Schaffner5ae4a232020-10-06 19:03:43 -0700[diff] [blame]145 type: "device",
146 clock: "clk_peri_i",
147 reset: "rst_peri_ni",
Michael Schaffner60aa10e2020-12-07 19:39:08 -0800[diff] [blame]148 pipeline: "false"
149 },
150 { name: "lc_ctrl",
151 type: "device",
152 clock: "clk_peri_i",
153 reset: "rst_peri_ni",
154 pipeline: "false"
Michael Schaffner5ae4a232020-10-06 19:03:43 -0700[diff] [blame]155 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]156 { name: "sensor_ctrl_aon",
Timothy Chendde68052020-08-05 16:29:35 -0700[diff] [blame]157 type: "device",
158 clock: "clk_peri_i",
159 reset: "rst_peri_ni",
160 pipeline: "false",
161 },
Michael Schaffnerbe5cb9c2020-11-19 19:53:47 -0800[diff] [blame]162 { name: "alert_handler",
163 type: "device",
164 clock: "clk_peri_i",
165 reset: "rst_peri_ni",
166 pipeline: "false",
167 },
Timothy Chen92b526e2021-02-01 21:23:42 -0800[diff] [blame]168 { name: "sram_ctrl_ret_aon",
Michael Schaffnerbd9a3542020-12-21 13:08:32 -0800[diff] [blame]169 type: "device",
170 clock: "clk_peri_i",
171 reset: "rst_peri_ni",
172 pipeline: "false"
173 },
Timothy Chen2b8ef762021-02-16 14:44:55 -0800[diff] [blame]174 { name: "aon_timer_aon",
Michael Schaffnerbe5cb9c2020-11-19 19:53:47 -0800[diff] [blame]175 type: "device",
176 clock: "clk_peri_i",
177 reset: "rst_peri_ni",
178 pipeline: "false",
Timothy Chen6f98f352021-03-10 16:27:29 -0800[diff] [blame]179 },
Michael Schaffnere029a682021-04-06 16:21:30 -0700[diff] [blame]180 { name: "sysrst_ctrl_aon",
181 type: "device",
182 clock: "clk_peri_i",
183 reset: "rst_peri_ni",
184 pipeline: "false",
185 }
Timothy Chen6f98f352021-03-10 16:27:29 -0800[diff] [blame]186 { name: "adc_ctrl_aon",
187 type: "device",
188 clock: "clk_peri_i",
189 reset: "rst_peri_ni",
190 pipeline: "false",
Michael Schaffnerbe5cb9c2020-11-19 19:53:47 -0800[diff] [blame]191 }
Timothy Chen94432212021-03-01 22:29:18 -0800[diff] [blame]192 { name: "ast",
Timothy Cheneba7f492020-08-26 17:12:08 -0700[diff] [blame]193 type: "device",
194 clock: "clk_peri_i",
195 reset: "rst_peri_ni",
196 pipeline: "false",
Timothy Cheneba7f492020-08-26 17:12:08 -0700[diff] [blame]197 },
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]198 ],
199 connections: {
Michael Schaffner8b0b5b12021-07-08 12:28:10 -0700[diff] [blame]200 main: [
201 "uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen",
202 "gpio", "spi_device", "spi_host0", "spi_host1", "rv_timer", "usbdev",
203 "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon", "ram_ret_aon",
204 "otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl", "sensor_ctrl_aon",
205 "alert_handler", "ast", "sram_ctrl_ret_aon", "aon_timer_aon", "adc_ctrl_aon",
206 "sysrst_ctrl_aon", "pwm_aon"
207 ],
Eunchan Kim0523f6b2019-12-17 13:53:11 -0800[diff] [blame]208 },
209}