[top] Top level updates
- add extra uarts
- align memory addresses
- update software for uart0
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] update unittest
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] revert flash size for now
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Fix concat for software consistency
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] update unittest for plic
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] update new location
Signed-off-by: Timothy Chen <timothytim@google.com>
[uart] exclude reads to status
- non-dedicated uarts showed failures likely due to 0'd inputs
Signed-off-by: Timothy Chen <timothytim@google.com>
[uart] exclude check on rx_idle only
Signed-off-by: Timothy Chen <timothytim@google.com>
[uart] update tag type
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index ca98be4..0cad49e 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -15,7 +15,25 @@
pipeline: "false"
},
- { name: "uart",
+ { name: "uart0",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "uart1",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "uart2",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "uart3",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
@@ -123,7 +141,8 @@
},
],
connections: {
- main: ["uart", "gpio", "spi_device", "rv_timer", "usbdev", "pwrmgr", "rstmgr", "clkmgr",
+ main: ["uart0", "uart1", "uart2", "uart3",
+ "gpio", "spi_device", "rv_timer", "usbdev", "pwrmgr", "rstmgr", "clkmgr",
"ram_ret", "otp_ctrl", "lc_ctrl", "sensor_ctrl", "alert_handler", "nmi_gen",
"ast_wrapper", "sram_ctrl_ret"],
},
