[top] Top level updates
- add extra uarts
- align memory addresses
- update software for uart0
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] update unittest
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] revert flash size for now
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Fix concat for software consistency
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] update unittest for plic
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] update new location
Signed-off-by: Timothy Chen <timothytim@google.com>
[uart] exclude reads to status
- non-dedicated uarts showed failures likely due to 0'd inputs
Signed-off-by: Timothy Chen <timothytim@google.com>
[uart] exclude check on rx_idle only
Signed-off-by: Timothy Chen <timothytim@google.com>
[uart] update tag type
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 75180eb..d10af0e 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -400,7 +400,7 @@
module:
[
{
- name: uart
+ name: uart0
type: uart
clock_srcs:
{
@@ -551,10 +551,490 @@
type: req_rsp
act: rsp
name: tl
- inst_name: uart
+ inst_name: uart0
width: 1
default: ""
- top_signame: uart_tl
+ top_signame: uart0_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: uart1
+ type: uart
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40010000
+ clock_reset_export: []
+ clock_group: secure
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_io_div4_secure
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list:
+ [
+ {
+ name: rx
+ width: 1
+ type: input
+ }
+ ]
+ available_output_list:
+ [
+ {
+ name: tx
+ width: 1
+ type: output
+ }
+ ]
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: uart1
+ width: 1
+ default: ""
+ top_signame: uart1_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: uart2
+ type: uart
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40020000
+ clock_reset_export: []
+ clock_group: secure
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_io_div4_secure
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list:
+ [
+ {
+ name: rx
+ width: 1
+ type: input
+ }
+ ]
+ available_output_list:
+ [
+ {
+ name: tx
+ width: 1
+ type: output
+ }
+ ]
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: uart2
+ width: 1
+ default: ""
+ top_signame: uart2_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: uart3
+ type: uart
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ reset_connections:
+ {
+ rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40030000
+ clock_reset_export: []
+ clock_group: secure
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_io_div4_secure
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list:
+ [
+ {
+ name: rx
+ width: 1
+ type: input
+ }
+ ]
+ available_output_list:
+ [
+ {
+ name: tx
+ width: 1
+ type: output
+ }
+ ]
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ }
+ {
+ name: rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: uart3
+ width: 1
+ default: ""
+ top_signame: uart3_tl
index: -1
}
]
@@ -5314,7 +5794,7 @@
}
domain: Aon
type: ram_1p_scr
- base_addr: 0x18000000
+ base_addr: 0x40520000
size: 0x1000
byte_write: "true"
inter_signal_list:
@@ -5750,9 +6230,21 @@
[
main.tl_sram_ctrl_main
]
- uart.tl:
+ uart0.tl:
[
- peri.tl_uart
+ peri.tl_uart0
+ ]
+ uart1.tl:
+ [
+ peri.tl_uart1
+ ]
+ uart2.tl:
+ [
+ peri.tl_uart2
+ ]
+ uart3.tl:
+ [
+ peri.tl_uart3
]
gpio.tl:
[
@@ -6040,16 +6532,12 @@
addr_range:
[
{
- base_addr: 0x18000000
- size_byte: 0x1000
- }
- {
base_addr: 0x40000000
size_byte: 0x421000
}
{
base_addr: 0x40500000
- size_byte: 0x20000
+ size_byte: 0x21000
}
]
}
@@ -6598,7 +7086,10 @@
{
main:
[
- uart
+ uart0
+ uart1
+ uart2
+ uart3
gpio
spi_device
rv_timer
@@ -6630,7 +7121,7 @@
pipeline_byp: "true"
}
{
- name: uart
+ name: uart0
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -6648,6 +7139,60 @@
pipeline_byp: "true"
}
{
+ name: uart1
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40010000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: uart2
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40020000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: uart3
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40030000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
name: gpio
type: device
clock: clk_peri_i
@@ -6783,7 +7328,7 @@
addr_range:
[
{
- base_addr: 0x18000000
+ base_addr: 0x40520000
size_byte: 0x1000
}
]
@@ -6936,13 +7481,49 @@
{
struct: tl
type: req_rsp
- name: tl_uart
+ name: tl_uart0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: uart_tl
+ top_signame: uart0_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_uart1
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: uart1_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_uart2
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: uart2_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_uart3
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: uart3_tl
index: -1
}
{
@@ -7131,8 +7712,11 @@
]
interrupt_module:
[
+ uart0
+ uart1
+ uart2
+ uart3
gpio
- uart
spi_device
flash_ctrl
hmac
@@ -7152,6 +7736,422 @@
interrupt:
[
{
+ name: uart0_tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart0_rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ module_name: uart0
+ }
+ {
+ name: uart1_tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart1_rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ module_name: uart1
+ }
+ {
+ name: uart2_tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart2_rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ module_name: uart2
+ }
+ {
+ name: uart3_tx_watermark
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_rx_watermark
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_tx_empty
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_rx_overflow
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_rx_frame_err
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_rx_break_err
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_rx_timeout
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
+ name: uart3_rx_parity_err
+ width: 1
+ bits: "7"
+ bitinfo:
+ [
+ 128
+ 1
+ 7
+ ]
+ type: interrupt
+ module_name: uart3
+ }
+ {
name: gpio_gpio
width: 32
bits: 31:0
@@ -7165,110 +8165,6 @@
module_name: gpio
}
{
- name: uart_tx_watermark
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_rx_watermark
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_tx_empty
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_rx_overflow
- width: 1
- bits: "3"
- bitinfo:
- [
- 8
- 1
- 3
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_rx_frame_err
- width: 1
- bits: "4"
- bitinfo:
- [
- 16
- 1
- 4
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_rx_break_err
- width: 1
- bits: "5"
- bitinfo:
- [
- 32
- 1
- 5
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_rx_timeout
- width: 1
- bits: "6"
- bitinfo:
- [
- 64
- 1
- 6
- ]
- type: interrupt
- module_name: uart
- }
- {
- name: uart_rx_parity_err
- width: 1
- bits: "7"
- bitinfo:
- [
- 128
- 1
- 7
- ]
- type: interrupt
- module_name: uart
- }
- {
name: spi_device_rxf
width: 1
bits: "0"
@@ -8331,7 +9227,7 @@
]
}
{
- name: uart
+ name: uart0
pad:
[
ChA[0..1]
@@ -8347,8 +9243,10 @@
]
mio_modules:
[
- uart
gpio
+ uart1
+ uart2
+ uart3
]
nc_modules:
[
@@ -8412,10 +9310,10 @@
]
}
{
- name: uart_rx
+ name: uart0_rx
width: 1
type: input
- module_name: uart
+ module_name: uart0
pad:
[
{
@@ -8425,10 +9323,10 @@
]
}
{
- name: uart_tx
+ name: uart0_tx
width: 1
type: output
- module_name: uart
+ module_name: uart0
pad:
[
{
@@ -8555,8 +9453,48 @@
]
}
]
- inputs: []
- outputs: []
+ inputs:
+ [
+ {
+ name: uart1_rx
+ width: 1
+ type: input
+ module_name: uart1
+ }
+ {
+ name: uart2_rx
+ width: 1
+ type: input
+ module_name: uart2
+ }
+ {
+ name: uart3_rx
+ width: 1
+ type: input
+ module_name: uart3
+ }
+ ]
+ outputs:
+ [
+ {
+ name: uart1_tx
+ width: 1
+ type: output
+ module_name: uart1
+ }
+ {
+ name: uart2_tx
+ width: 1
+ type: output
+ module_name: uart2
+ }
+ {
+ name: uart3_tx
+ width: 1
+ type: output
+ module_name: uart3
+ }
+ ]
inouts:
[
{
@@ -8674,10 +9612,46 @@
type: req_rsp
act: rsp
name: tl
- inst_name: uart
+ inst_name: uart0
width: 1
default: ""
- top_signame: uart_tl
+ top_signame: uart0_tl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: uart1
+ width: 1
+ default: ""
+ top_signame: uart1_tl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: uart2
+ width: 1
+ default: ""
+ top_signame: uart2_tl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: uart3
+ width: 1
+ default: ""
+ top_signame: uart3_tl
index: -1
}
{
@@ -11078,13 +12052,49 @@
{
struct: tl
type: req_rsp
- name: tl_uart
+ name: tl_uart0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: uart_tl
+ top_signame: uart0_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_uart1
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: uart1_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_uart2
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: uart2_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_uart3
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: uart3_tl
index: -1
}
{
@@ -12281,7 +13291,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: uart_tl_req
+ signame: uart0_tl_req
width: 1
type: req_rsp
default: ""
@@ -12289,7 +13299,55 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: uart_tl_rsp
+ signame: uart0_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
+ signame: uart1_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: uart1_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
+ signame: uart2_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: uart2_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
+ signame: uart3_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: uart3_tl_rsp
width: 1
type: req_rsp
default: ""
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index fd90aff..7fb9c3c 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -201,7 +201,7 @@
// generated: A module is templated and generated as part of topgen
// top_only: A module is not templated but is specific to 'top_*' instead of 'ip'
module: [
- { name: "uart", // instance name
+ { name: "uart0", // instance name
type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
// and `hw/ip/{type}`
@@ -216,6 +216,51 @@
reset_connections: {rst_ni: "sys_io_div4"},
base_addr: "0x40000000",
},
+ { name: "uart1", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "sys_io_div4"},
+ base_addr: "0x40010000",
+ },
+ { name: "uart2", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "sys_io_div4"},
+ base_addr: "0x40020000",
+ },
+ { name: "uart3", // instance name
+ type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
+ // and `hw/ip/{type}`
+
+ // clock connections defines the port to top level clock connection
+ // the ip.hjson will declare the clock port names
+ // If none are defined at ip.hjson, clk_i is used by default
+ clock_srcs: {clk_i: "io_div4"},
+
+ // reset connections defines the port to top level reset connection
+ // the ip.hjson will declare the reset port names
+ // If none are defined at ip.hjson, rst_ni is used by default
+ reset_connections: {rst_ni: "sys_io_div4"},
+ base_addr: "0x40030000",
+ },
{ name: "gpio",
type: "gpio",
clock_srcs: {clk_i: "io_div4"},
@@ -491,7 +536,7 @@
reset_connections: {rst_ni: "sys_io_div4"},
domain: "Aon",
type: "ram_1p_scr",
- base_addr: "0x18000000",
+ base_addr: "0x40520000",
size: "0x1000",
byte_write: "true",
inter_signal_list: [
@@ -718,7 +763,8 @@
// If interrupt is not defined, it uses the order from the module list
// and include every modules.
// first item goes to LSB of the interrupt source
- interrupt_module: ["gpio", "uart", "spi_device", "flash_ctrl",
+ interrupt_module: ["uart0", "uart1", "uart2", "uart3",
+ "gpio", "spi_device", "flash_ctrl",
"hmac", "alert_handler", "nmi_gen", "usbdev", "pwrmgr",
"otbn", "keymgr", "kmac", "otp_ctrl", "csrng", "edn0", "edn1",
"entropy_src"]
@@ -755,7 +801,7 @@
dio_modules: [
{ name: "spi_device", pad: ["ChB[0..3]"] },
//{ name: "uart.tx", pad: ["ChA[0]"]},
- { name: "uart", pad: ["ChA[0..1]"]},
+ { name: "uart0", pad: ["ChA[0..1]"]},
// { name: "dio_module.signal_input", pad: ["ChA[31]"] }
{ name: "usbdev", pad: ["ChC[0..8]"]},
],
@@ -765,7 +811,7 @@
// between the modules and the IO PADS.
// If `mio_modules` aren't defined, it uses all remaining modules from
// module list except defined in `dio_modules`.
- mio_modules: ["uart", "gpio"]
+ mio_modules: ["gpio", "uart1", "uart2", "uart3", ]
// If any module isn't defined in above two lists, its inputs will be tied
// to 0, and the output/OE signals will be floating (or connected to
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 180a808..3383d3a 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -671,19 +671,19 @@
// Pinmux connections
% if num_mio_outputs + num_mio_inouts != 0:
assign mio_d2p = {
- % for sig in top["pinmux"]["inouts"] + top["pinmux"]["outputs"]:
+ % for sig in list(reversed(top["pinmux"]["inouts"] + top["pinmux"]["outputs"])):
cio_${sig["name"]}_d2p${"" if loop.last else ","}
% endfor
};
assign mio_d2p_en = {
- % for sig in top["pinmux"]["inouts"] + top["pinmux"]["outputs"]:
+ % for sig in list(reversed(top["pinmux"]["inouts"] + top["pinmux"]["outputs"])):
cio_${sig["name"]}_en_d2p${"" if loop.last else ","}
% endfor
};
% endif
% if num_mio_inputs + num_mio_inouts != 0:
assign {
- % for sig in top["pinmux"]["inouts"] + top["pinmux"]["inputs"]:
+ % for sig in list(reversed(top["pinmux"]["inouts"] + top["pinmux"]["inputs"])):
cio_${sig["name"]}_p2d${"" if loop.last else ","}
% endfor
} = mio_p2d;
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index ca98be4..0cad49e 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -15,7 +15,25 @@
pipeline: "false"
},
- { name: "uart",
+ { name: "uart0",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "uart1",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "uart2",
+ type: "device",
+ clock: "clk_peri_i",
+ reset: "rst_peri_ni",
+ pipeline: "false"
+ },
+ { name: "uart3",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
@@ -123,7 +141,8 @@
},
],
connections: {
- main: ["uart", "gpio", "spi_device", "rv_timer", "usbdev", "pwrmgr", "rstmgr", "clkmgr",
+ main: ["uart0", "uart1", "uart2", "uart3",
+ "gpio", "spi_device", "rv_timer", "usbdev", "pwrmgr", "rstmgr", "clkmgr",
"ram_ret", "otp_ctrl", "lc_ctrl", "sensor_ctrl", "alert_handler", "nmi_gen",
"ast_wrapper", "sram_ctrl_ret"],
},
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 29ebc19..11fee16 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -51,7 +51,10 @@
tl_if otbn_tl_if(clk_main, rst_n);
tl_if keymgr_tl_if(clk_main, rst_n);
tl_if sram_ctrl_main_tl_if(clk_main, rst_n);
-tl_if uart_tl_if(clk_io_div4, rst_n);
+tl_if uart0_tl_if(clk_io_div4, rst_n);
+tl_if uart1_tl_if(clk_io_div4, rst_n);
+tl_if uart2_tl_if(clk_io_div4, rst_n);
+tl_if uart3_tl_if(clk_io_div4, rst_n);
tl_if gpio_tl_if(clk_io_div4, rst_n);
tl_if spi_device_tl_if(clk_io_div4, rst_n);
tl_if rv_timer_tl_if(clk_io_div4, rst_n);
@@ -113,7 +116,10 @@
`DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl)
`DRIVE_CHIP_TL_DEVICE_IF(keymgr, keymgr, tl)
`DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main, sram_ctrl_main, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(uart, uart, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart0, uart0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart1, uart1, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart2, uart2, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart3, uart3, tl)
`DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl)
`DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl)
`DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index fdf8181..92716bb 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -61,9 +61,18 @@
'{"sram_ctrl_main", '{
'{32'h411c0000, 32'h411c0fff}
}},
- '{"uart", '{
+ '{"uart0", '{
'{32'h40000000, 32'h40000fff}
}},
+ '{"uart1", '{
+ '{32'h40010000, 32'h40010fff}
+ }},
+ '{"uart2", '{
+ '{32'h40020000, 32'h40020fff}
+ }},
+ '{"uart3", '{
+ '{32'h40030000, 32'h40030fff}
+ }},
'{"gpio", '{
'{32'h40040000, 32'h40040fff}
}},
@@ -86,7 +95,7 @@
'{32'h40420000, 32'h40420fff}
}},
'{"ram_ret", '{
- '{32'h18000000, 32'h18000fff}
+ '{32'h40520000, 32'h40520fff}
}},
'{"otp_ctrl", '{
'{32'h40130000, 32'h40133fff}
@@ -123,7 +132,10 @@
"debug_mem",
"ram_main",
"eflash",
- "uart",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
"gpio",
"spi_device",
"rv_timer",
@@ -158,7 +170,10 @@
"rom",
"ram_main",
"eflash",
- "uart",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
"gpio",
"spi_device",
"rv_timer",
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
index 805451f..0010d16 100644
--- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -88,13 +88,13 @@
{ name: "NMioPeriphIn",
desc: "Number of muxed peripheral inputs",
type: "int",
- default: "32",
+ default: "35",
local: "true"
},
{ name: "NMioPeriphOut",
desc: "Number of muxed peripheral outputs",
type: "int",
- default: "32",
+ default: "35",
local: "true"
},
{ name: "NMioPads",
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
index 6460644..8926840 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -7,8 +7,8 @@
package pinmux_reg_pkg;
// Param list
- parameter int NMioPeriphIn = 32;
- parameter int NMioPeriphOut = 32;
+ parameter int NMioPeriphIn = 35;
+ parameter int NMioPeriphOut = 35;
parameter int NMioPads = 32;
parameter int NDioPads = 15;
parameter int NWkupDetect = 8;
@@ -80,7 +80,7 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- pinmux_reg2hw_periph_insel_mreg_t [31:0] periph_insel; // [660:469]
+ pinmux_reg2hw_periph_insel_mreg_t [34:0] periph_insel; // [678:469]
pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [468:277]
pinmux_reg2hw_mio_out_sleep_val_mreg_t [31:0] mio_out_sleep_val; // [276:213]
pinmux_reg2hw_dio_out_sleep_val_mreg_t [14:0] dio_out_sleep_val; // [212:168]
@@ -179,7 +179,7 @@
4'b 1111, // index[ 4] PINMUX_PERIPH_INSEL_3
4'b 1111, // index[ 5] PINMUX_PERIPH_INSEL_4
4'b 1111, // index[ 6] PINMUX_PERIPH_INSEL_5
- 4'b 0011, // index[ 7] PINMUX_PERIPH_INSEL_6
+ 4'b 1111, // index[ 7] PINMUX_PERIPH_INSEL_6
4'b 1111, // index[ 8] PINMUX_MIO_OUTSEL_0
4'b 1111, // index[ 9] PINMUX_MIO_OUTSEL_1
4'b 1111, // index[10] PINMUX_MIO_OUTSEL_2
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index e5a80d6..f959fc5 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -170,6 +170,15 @@
logic [5:0] periph_insel_6_in_31_qs;
logic [5:0] periph_insel_6_in_31_wd;
logic periph_insel_6_in_31_we;
+ logic [5:0] periph_insel_6_in_32_qs;
+ logic [5:0] periph_insel_6_in_32_wd;
+ logic periph_insel_6_in_32_we;
+ logic [5:0] periph_insel_6_in_33_qs;
+ logic [5:0] periph_insel_6_in_33_wd;
+ logic periph_insel_6_in_33_we;
+ logic [5:0] periph_insel_6_in_34_qs;
+ logic [5:0] periph_insel_6_in_34_wd;
+ logic periph_insel_6_in_34_we;
logic [5:0] mio_outsel_0_out_0_qs;
logic [5:0] mio_outsel_0_out_0_wd;
logic mio_outsel_0_out_0_we;
@@ -1481,6 +1490,84 @@
);
+ // F[in_32]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel_6_in_32 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel_6_in_32_we & regen_qs),
+ .wd (periph_insel_6_in_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[32].q ),
+
+ // to register interface (read)
+ .qs (periph_insel_6_in_32_qs)
+ );
+
+
+ // F[in_33]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel_6_in_33 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel_6_in_33_we & regen_qs),
+ .wd (periph_insel_6_in_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[33].q ),
+
+ // to register interface (read)
+ .qs (periph_insel_6_in_33_qs)
+ );
+
+
+ // F[in_34]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel_6_in_34 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel_6_in_34_we & regen_qs),
+ .wd (periph_insel_6_in_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[34].q ),
+
+ // to register interface (read)
+ .qs (periph_insel_6_in_34_qs)
+ );
+
+
// Subregister 0 of Multireg mio_outsel
@@ -5027,6 +5114,15 @@
assign periph_insel_6_in_31_we = addr_hit[7] & reg_we & ~wr_err;
assign periph_insel_6_in_31_wd = reg_wdata[11:6];
+ assign periph_insel_6_in_32_we = addr_hit[7] & reg_we & ~wr_err;
+ assign periph_insel_6_in_32_wd = reg_wdata[17:12];
+
+ assign periph_insel_6_in_33_we = addr_hit[7] & reg_we & ~wr_err;
+ assign periph_insel_6_in_33_wd = reg_wdata[23:18];
+
+ assign periph_insel_6_in_34_we = addr_hit[7] & reg_we & ~wr_err;
+ assign periph_insel_6_in_34_wd = reg_wdata[29:24];
+
assign mio_outsel_0_out_0_we = addr_hit[8] & reg_we & ~wr_err;
assign mio_outsel_0_out_0_wd = reg_wdata[5:0];
@@ -5514,6 +5610,9 @@
addr_hit[7]: begin
reg_rdata_next[5:0] = periph_insel_6_in_30_qs;
reg_rdata_next[11:6] = periph_insel_6_in_31_qs;
+ reg_rdata_next[17:12] = periph_insel_6_in_32_qs;
+ reg_rdata_next[23:18] = periph_insel_6_in_33_qs;
+ reg_rdata_next[29:24] = periph_insel_6_in_34_qs;
end
addr_hit[8]: begin
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
index 7659895..86ab76b 100644
--- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@
{ name: "NumSrc",
desc: "Number of interrupt sources",
type: "int",
- default: "99",
+ default: "123",
local: "true"
},
{ name: "NumTarget",
@@ -861,7 +861,199 @@
{ bits: "1:0" }
],
}
- { skipto: "512" }
+ { name: "PRIO99",
+ desc: "Interrupt Source 99 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO100",
+ desc: "Interrupt Source 100 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO101",
+ desc: "Interrupt Source 101 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO102",
+ desc: "Interrupt Source 102 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO103",
+ desc: "Interrupt Source 103 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO104",
+ desc: "Interrupt Source 104 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO105",
+ desc: "Interrupt Source 105 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO106",
+ desc: "Interrupt Source 106 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO107",
+ desc: "Interrupt Source 107 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO108",
+ desc: "Interrupt Source 108 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO109",
+ desc: "Interrupt Source 109 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO110",
+ desc: "Interrupt Source 110 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO111",
+ desc: "Interrupt Source 111 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO112",
+ desc: "Interrupt Source 112 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO113",
+ desc: "Interrupt Source 113 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO114",
+ desc: "Interrupt Source 114 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO115",
+ desc: "Interrupt Source 115 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO116",
+ desc: "Interrupt Source 116 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO117",
+ desc: "Interrupt Source 117 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO118",
+ desc: "Interrupt Source 118 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO119",
+ desc: "Interrupt Source 119 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO120",
+ desc: "Interrupt Source 120 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO121",
+ desc: "Interrupt Source 121 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO122",
+ desc: "Interrupt Source 122 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { skipto: "768" }
{ multireg: {
name: "IE0",
desc: "Interrupt Enable for Target 0",
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index 5e45d1f..f03bf33 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -193,11 +193,35 @@
assign prio[96] = reg2hw.prio96.q;
assign prio[97] = reg2hw.prio97.q;
assign prio[98] = reg2hw.prio98.q;
+ assign prio[99] = reg2hw.prio99.q;
+ assign prio[100] = reg2hw.prio100.q;
+ assign prio[101] = reg2hw.prio101.q;
+ assign prio[102] = reg2hw.prio102.q;
+ assign prio[103] = reg2hw.prio103.q;
+ assign prio[104] = reg2hw.prio104.q;
+ assign prio[105] = reg2hw.prio105.q;
+ assign prio[106] = reg2hw.prio106.q;
+ assign prio[107] = reg2hw.prio107.q;
+ assign prio[108] = reg2hw.prio108.q;
+ assign prio[109] = reg2hw.prio109.q;
+ assign prio[110] = reg2hw.prio110.q;
+ assign prio[111] = reg2hw.prio111.q;
+ assign prio[112] = reg2hw.prio112.q;
+ assign prio[113] = reg2hw.prio113.q;
+ assign prio[114] = reg2hw.prio114.q;
+ assign prio[115] = reg2hw.prio115.q;
+ assign prio[116] = reg2hw.prio116.q;
+ assign prio[117] = reg2hw.prio117.q;
+ assign prio[118] = reg2hw.prio118.q;
+ assign prio[119] = reg2hw.prio119.q;
+ assign prio[120] = reg2hw.prio120.q;
+ assign prio[121] = reg2hw.prio121.q;
+ assign prio[122] = reg2hw.prio122.q;
//////////////////////
// Interrupt Enable //
//////////////////////
- for (genvar s = 0; s < 99; s++) begin : gen_ie0
+ for (genvar s = 0; s < 123; s++) begin : gen_ie0
assign ie[0][s] = reg2hw.ie0[s].q;
end
@@ -223,7 +247,7 @@
////////
// IP //
////////
- for (genvar s = 0; s < 99; s++) begin : gen_ip
+ for (genvar s = 0; s < 123; s++) begin : gen_ip
assign hw2reg.ip[s].de = 1'b1; // Always write
assign hw2reg.ip[s].d = ip[s];
end
@@ -231,7 +255,7 @@
///////////////////////////////////
// Detection:: 0: Level, 1: Edge //
///////////////////////////////////
- for (genvar s = 0; s < 99; s++) begin : gen_le
+ for (genvar s = 0; s < 123; s++) begin : gen_le
assign le[s] = reg2hw.le[s].q;
end
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
index bf7827a..3eb1881 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,7 +7,7 @@
package rv_plic_reg_pkg;
// Param list
- parameter int NumSrc = 99;
+ parameter int NumSrc = 123;
parameter int NumTarget = 1;
parameter int PrioWidth = 2;
@@ -418,6 +418,102 @@
} rv_plic_reg2hw_prio98_reg_t;
typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio99_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio100_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio101_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio102_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio103_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio104_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio105_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio106_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio107_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio108_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio109_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio110_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio111_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio112_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio113_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio114_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio115_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio116_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio117_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio118_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio119_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio120_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio121_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio122_reg_t;
+
+ typedef struct packed {
logic q;
} rv_plic_reg2hw_ie0_mreg_t;
@@ -450,107 +546,131 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- rv_plic_reg2hw_le_mreg_t [98:0] le; // [407:309]
- rv_plic_reg2hw_prio0_reg_t prio0; // [308:307]
- rv_plic_reg2hw_prio1_reg_t prio1; // [306:305]
- rv_plic_reg2hw_prio2_reg_t prio2; // [304:303]
- rv_plic_reg2hw_prio3_reg_t prio3; // [302:301]
- rv_plic_reg2hw_prio4_reg_t prio4; // [300:299]
- rv_plic_reg2hw_prio5_reg_t prio5; // [298:297]
- rv_plic_reg2hw_prio6_reg_t prio6; // [296:295]
- rv_plic_reg2hw_prio7_reg_t prio7; // [294:293]
- rv_plic_reg2hw_prio8_reg_t prio8; // [292:291]
- rv_plic_reg2hw_prio9_reg_t prio9; // [290:289]
- rv_plic_reg2hw_prio10_reg_t prio10; // [288:287]
- rv_plic_reg2hw_prio11_reg_t prio11; // [286:285]
- rv_plic_reg2hw_prio12_reg_t prio12; // [284:283]
- rv_plic_reg2hw_prio13_reg_t prio13; // [282:281]
- rv_plic_reg2hw_prio14_reg_t prio14; // [280:279]
- rv_plic_reg2hw_prio15_reg_t prio15; // [278:277]
- rv_plic_reg2hw_prio16_reg_t prio16; // [276:275]
- rv_plic_reg2hw_prio17_reg_t prio17; // [274:273]
- rv_plic_reg2hw_prio18_reg_t prio18; // [272:271]
- rv_plic_reg2hw_prio19_reg_t prio19; // [270:269]
- rv_plic_reg2hw_prio20_reg_t prio20; // [268:267]
- rv_plic_reg2hw_prio21_reg_t prio21; // [266:265]
- rv_plic_reg2hw_prio22_reg_t prio22; // [264:263]
- rv_plic_reg2hw_prio23_reg_t prio23; // [262:261]
- rv_plic_reg2hw_prio24_reg_t prio24; // [260:259]
- rv_plic_reg2hw_prio25_reg_t prio25; // [258:257]
- rv_plic_reg2hw_prio26_reg_t prio26; // [256:255]
- rv_plic_reg2hw_prio27_reg_t prio27; // [254:253]
- rv_plic_reg2hw_prio28_reg_t prio28; // [252:251]
- rv_plic_reg2hw_prio29_reg_t prio29; // [250:249]
- rv_plic_reg2hw_prio30_reg_t prio30; // [248:247]
- rv_plic_reg2hw_prio31_reg_t prio31; // [246:245]
- rv_plic_reg2hw_prio32_reg_t prio32; // [244:243]
- rv_plic_reg2hw_prio33_reg_t prio33; // [242:241]
- rv_plic_reg2hw_prio34_reg_t prio34; // [240:239]
- rv_plic_reg2hw_prio35_reg_t prio35; // [238:237]
- rv_plic_reg2hw_prio36_reg_t prio36; // [236:235]
- rv_plic_reg2hw_prio37_reg_t prio37; // [234:233]
- rv_plic_reg2hw_prio38_reg_t prio38; // [232:231]
- rv_plic_reg2hw_prio39_reg_t prio39; // [230:229]
- rv_plic_reg2hw_prio40_reg_t prio40; // [228:227]
- rv_plic_reg2hw_prio41_reg_t prio41; // [226:225]
- rv_plic_reg2hw_prio42_reg_t prio42; // [224:223]
- rv_plic_reg2hw_prio43_reg_t prio43; // [222:221]
- rv_plic_reg2hw_prio44_reg_t prio44; // [220:219]
- rv_plic_reg2hw_prio45_reg_t prio45; // [218:217]
- rv_plic_reg2hw_prio46_reg_t prio46; // [216:215]
- rv_plic_reg2hw_prio47_reg_t prio47; // [214:213]
- rv_plic_reg2hw_prio48_reg_t prio48; // [212:211]
- rv_plic_reg2hw_prio49_reg_t prio49; // [210:209]
- rv_plic_reg2hw_prio50_reg_t prio50; // [208:207]
- rv_plic_reg2hw_prio51_reg_t prio51; // [206:205]
- rv_plic_reg2hw_prio52_reg_t prio52; // [204:203]
- rv_plic_reg2hw_prio53_reg_t prio53; // [202:201]
- rv_plic_reg2hw_prio54_reg_t prio54; // [200:199]
- rv_plic_reg2hw_prio55_reg_t prio55; // [198:197]
- rv_plic_reg2hw_prio56_reg_t prio56; // [196:195]
- rv_plic_reg2hw_prio57_reg_t prio57; // [194:193]
- rv_plic_reg2hw_prio58_reg_t prio58; // [192:191]
- rv_plic_reg2hw_prio59_reg_t prio59; // [190:189]
- rv_plic_reg2hw_prio60_reg_t prio60; // [188:187]
- rv_plic_reg2hw_prio61_reg_t prio61; // [186:185]
- rv_plic_reg2hw_prio62_reg_t prio62; // [184:183]
- rv_plic_reg2hw_prio63_reg_t prio63; // [182:181]
- rv_plic_reg2hw_prio64_reg_t prio64; // [180:179]
- rv_plic_reg2hw_prio65_reg_t prio65; // [178:177]
- rv_plic_reg2hw_prio66_reg_t prio66; // [176:175]
- rv_plic_reg2hw_prio67_reg_t prio67; // [174:173]
- rv_plic_reg2hw_prio68_reg_t prio68; // [172:171]
- rv_plic_reg2hw_prio69_reg_t prio69; // [170:169]
- rv_plic_reg2hw_prio70_reg_t prio70; // [168:167]
- rv_plic_reg2hw_prio71_reg_t prio71; // [166:165]
- rv_plic_reg2hw_prio72_reg_t prio72; // [164:163]
- rv_plic_reg2hw_prio73_reg_t prio73; // [162:161]
- rv_plic_reg2hw_prio74_reg_t prio74; // [160:159]
- rv_plic_reg2hw_prio75_reg_t prio75; // [158:157]
- rv_plic_reg2hw_prio76_reg_t prio76; // [156:155]
- rv_plic_reg2hw_prio77_reg_t prio77; // [154:153]
- rv_plic_reg2hw_prio78_reg_t prio78; // [152:151]
- rv_plic_reg2hw_prio79_reg_t prio79; // [150:149]
- rv_plic_reg2hw_prio80_reg_t prio80; // [148:147]
- rv_plic_reg2hw_prio81_reg_t prio81; // [146:145]
- rv_plic_reg2hw_prio82_reg_t prio82; // [144:143]
- rv_plic_reg2hw_prio83_reg_t prio83; // [142:141]
- rv_plic_reg2hw_prio84_reg_t prio84; // [140:139]
- rv_plic_reg2hw_prio85_reg_t prio85; // [138:137]
- rv_plic_reg2hw_prio86_reg_t prio86; // [136:135]
- rv_plic_reg2hw_prio87_reg_t prio87; // [134:133]
- rv_plic_reg2hw_prio88_reg_t prio88; // [132:131]
- rv_plic_reg2hw_prio89_reg_t prio89; // [130:129]
- rv_plic_reg2hw_prio90_reg_t prio90; // [128:127]
- rv_plic_reg2hw_prio91_reg_t prio91; // [126:125]
- rv_plic_reg2hw_prio92_reg_t prio92; // [124:123]
- rv_plic_reg2hw_prio93_reg_t prio93; // [122:121]
- rv_plic_reg2hw_prio94_reg_t prio94; // [120:119]
- rv_plic_reg2hw_prio95_reg_t prio95; // [118:117]
- rv_plic_reg2hw_prio96_reg_t prio96; // [116:115]
- rv_plic_reg2hw_prio97_reg_t prio97; // [114:113]
- rv_plic_reg2hw_prio98_reg_t prio98; // [112:111]
- rv_plic_reg2hw_ie0_mreg_t [98:0] ie0; // [110:12]
+ rv_plic_reg2hw_le_mreg_t [122:0] le; // [503:381]
+ rv_plic_reg2hw_prio0_reg_t prio0; // [380:379]
+ rv_plic_reg2hw_prio1_reg_t prio1; // [378:377]
+ rv_plic_reg2hw_prio2_reg_t prio2; // [376:375]
+ rv_plic_reg2hw_prio3_reg_t prio3; // [374:373]
+ rv_plic_reg2hw_prio4_reg_t prio4; // [372:371]
+ rv_plic_reg2hw_prio5_reg_t prio5; // [370:369]
+ rv_plic_reg2hw_prio6_reg_t prio6; // [368:367]
+ rv_plic_reg2hw_prio7_reg_t prio7; // [366:365]
+ rv_plic_reg2hw_prio8_reg_t prio8; // [364:363]
+ rv_plic_reg2hw_prio9_reg_t prio9; // [362:361]
+ rv_plic_reg2hw_prio10_reg_t prio10; // [360:359]
+ rv_plic_reg2hw_prio11_reg_t prio11; // [358:357]
+ rv_plic_reg2hw_prio12_reg_t prio12; // [356:355]
+ rv_plic_reg2hw_prio13_reg_t prio13; // [354:353]
+ rv_plic_reg2hw_prio14_reg_t prio14; // [352:351]
+ rv_plic_reg2hw_prio15_reg_t prio15; // [350:349]
+ rv_plic_reg2hw_prio16_reg_t prio16; // [348:347]
+ rv_plic_reg2hw_prio17_reg_t prio17; // [346:345]
+ rv_plic_reg2hw_prio18_reg_t prio18; // [344:343]
+ rv_plic_reg2hw_prio19_reg_t prio19; // [342:341]
+ rv_plic_reg2hw_prio20_reg_t prio20; // [340:339]
+ rv_plic_reg2hw_prio21_reg_t prio21; // [338:337]
+ rv_plic_reg2hw_prio22_reg_t prio22; // [336:335]
+ rv_plic_reg2hw_prio23_reg_t prio23; // [334:333]
+ rv_plic_reg2hw_prio24_reg_t prio24; // [332:331]
+ rv_plic_reg2hw_prio25_reg_t prio25; // [330:329]
+ rv_plic_reg2hw_prio26_reg_t prio26; // [328:327]
+ rv_plic_reg2hw_prio27_reg_t prio27; // [326:325]
+ rv_plic_reg2hw_prio28_reg_t prio28; // [324:323]
+ rv_plic_reg2hw_prio29_reg_t prio29; // [322:321]
+ rv_plic_reg2hw_prio30_reg_t prio30; // [320:319]
+ rv_plic_reg2hw_prio31_reg_t prio31; // [318:317]
+ rv_plic_reg2hw_prio32_reg_t prio32; // [316:315]
+ rv_plic_reg2hw_prio33_reg_t prio33; // [314:313]
+ rv_plic_reg2hw_prio34_reg_t prio34; // [312:311]
+ rv_plic_reg2hw_prio35_reg_t prio35; // [310:309]
+ rv_plic_reg2hw_prio36_reg_t prio36; // [308:307]
+ rv_plic_reg2hw_prio37_reg_t prio37; // [306:305]
+ rv_plic_reg2hw_prio38_reg_t prio38; // [304:303]
+ rv_plic_reg2hw_prio39_reg_t prio39; // [302:301]
+ rv_plic_reg2hw_prio40_reg_t prio40; // [300:299]
+ rv_plic_reg2hw_prio41_reg_t prio41; // [298:297]
+ rv_plic_reg2hw_prio42_reg_t prio42; // [296:295]
+ rv_plic_reg2hw_prio43_reg_t prio43; // [294:293]
+ rv_plic_reg2hw_prio44_reg_t prio44; // [292:291]
+ rv_plic_reg2hw_prio45_reg_t prio45; // [290:289]
+ rv_plic_reg2hw_prio46_reg_t prio46; // [288:287]
+ rv_plic_reg2hw_prio47_reg_t prio47; // [286:285]
+ rv_plic_reg2hw_prio48_reg_t prio48; // [284:283]
+ rv_plic_reg2hw_prio49_reg_t prio49; // [282:281]
+ rv_plic_reg2hw_prio50_reg_t prio50; // [280:279]
+ rv_plic_reg2hw_prio51_reg_t prio51; // [278:277]
+ rv_plic_reg2hw_prio52_reg_t prio52; // [276:275]
+ rv_plic_reg2hw_prio53_reg_t prio53; // [274:273]
+ rv_plic_reg2hw_prio54_reg_t prio54; // [272:271]
+ rv_plic_reg2hw_prio55_reg_t prio55; // [270:269]
+ rv_plic_reg2hw_prio56_reg_t prio56; // [268:267]
+ rv_plic_reg2hw_prio57_reg_t prio57; // [266:265]
+ rv_plic_reg2hw_prio58_reg_t prio58; // [264:263]
+ rv_plic_reg2hw_prio59_reg_t prio59; // [262:261]
+ rv_plic_reg2hw_prio60_reg_t prio60; // [260:259]
+ rv_plic_reg2hw_prio61_reg_t prio61; // [258:257]
+ rv_plic_reg2hw_prio62_reg_t prio62; // [256:255]
+ rv_plic_reg2hw_prio63_reg_t prio63; // [254:253]
+ rv_plic_reg2hw_prio64_reg_t prio64; // [252:251]
+ rv_plic_reg2hw_prio65_reg_t prio65; // [250:249]
+ rv_plic_reg2hw_prio66_reg_t prio66; // [248:247]
+ rv_plic_reg2hw_prio67_reg_t prio67; // [246:245]
+ rv_plic_reg2hw_prio68_reg_t prio68; // [244:243]
+ rv_plic_reg2hw_prio69_reg_t prio69; // [242:241]
+ rv_plic_reg2hw_prio70_reg_t prio70; // [240:239]
+ rv_plic_reg2hw_prio71_reg_t prio71; // [238:237]
+ rv_plic_reg2hw_prio72_reg_t prio72; // [236:235]
+ rv_plic_reg2hw_prio73_reg_t prio73; // [234:233]
+ rv_plic_reg2hw_prio74_reg_t prio74; // [232:231]
+ rv_plic_reg2hw_prio75_reg_t prio75; // [230:229]
+ rv_plic_reg2hw_prio76_reg_t prio76; // [228:227]
+ rv_plic_reg2hw_prio77_reg_t prio77; // [226:225]
+ rv_plic_reg2hw_prio78_reg_t prio78; // [224:223]
+ rv_plic_reg2hw_prio79_reg_t prio79; // [222:221]
+ rv_plic_reg2hw_prio80_reg_t prio80; // [220:219]
+ rv_plic_reg2hw_prio81_reg_t prio81; // [218:217]
+ rv_plic_reg2hw_prio82_reg_t prio82; // [216:215]
+ rv_plic_reg2hw_prio83_reg_t prio83; // [214:213]
+ rv_plic_reg2hw_prio84_reg_t prio84; // [212:211]
+ rv_plic_reg2hw_prio85_reg_t prio85; // [210:209]
+ rv_plic_reg2hw_prio86_reg_t prio86; // [208:207]
+ rv_plic_reg2hw_prio87_reg_t prio87; // [206:205]
+ rv_plic_reg2hw_prio88_reg_t prio88; // [204:203]
+ rv_plic_reg2hw_prio89_reg_t prio89; // [202:201]
+ rv_plic_reg2hw_prio90_reg_t prio90; // [200:199]
+ rv_plic_reg2hw_prio91_reg_t prio91; // [198:197]
+ rv_plic_reg2hw_prio92_reg_t prio92; // [196:195]
+ rv_plic_reg2hw_prio93_reg_t prio93; // [194:193]
+ rv_plic_reg2hw_prio94_reg_t prio94; // [192:191]
+ rv_plic_reg2hw_prio95_reg_t prio95; // [190:189]
+ rv_plic_reg2hw_prio96_reg_t prio96; // [188:187]
+ rv_plic_reg2hw_prio97_reg_t prio97; // [186:185]
+ rv_plic_reg2hw_prio98_reg_t prio98; // [184:183]
+ rv_plic_reg2hw_prio99_reg_t prio99; // [182:181]
+ rv_plic_reg2hw_prio100_reg_t prio100; // [180:179]
+ rv_plic_reg2hw_prio101_reg_t prio101; // [178:177]
+ rv_plic_reg2hw_prio102_reg_t prio102; // [176:175]
+ rv_plic_reg2hw_prio103_reg_t prio103; // [174:173]
+ rv_plic_reg2hw_prio104_reg_t prio104; // [172:171]
+ rv_plic_reg2hw_prio105_reg_t prio105; // [170:169]
+ rv_plic_reg2hw_prio106_reg_t prio106; // [168:167]
+ rv_plic_reg2hw_prio107_reg_t prio107; // [166:165]
+ rv_plic_reg2hw_prio108_reg_t prio108; // [164:163]
+ rv_plic_reg2hw_prio109_reg_t prio109; // [162:161]
+ rv_plic_reg2hw_prio110_reg_t prio110; // [160:159]
+ rv_plic_reg2hw_prio111_reg_t prio111; // [158:157]
+ rv_plic_reg2hw_prio112_reg_t prio112; // [156:155]
+ rv_plic_reg2hw_prio113_reg_t prio113; // [154:153]
+ rv_plic_reg2hw_prio114_reg_t prio114; // [152:151]
+ rv_plic_reg2hw_prio115_reg_t prio115; // [150:149]
+ rv_plic_reg2hw_prio116_reg_t prio116; // [148:147]
+ rv_plic_reg2hw_prio117_reg_t prio117; // [146:145]
+ rv_plic_reg2hw_prio118_reg_t prio118; // [144:143]
+ rv_plic_reg2hw_prio119_reg_t prio119; // [142:141]
+ rv_plic_reg2hw_prio120_reg_t prio120; // [140:139]
+ rv_plic_reg2hw_prio121_reg_t prio121; // [138:137]
+ rv_plic_reg2hw_prio122_reg_t prio122; // [136:135]
+ rv_plic_reg2hw_ie0_mreg_t [122:0] ie0; // [134:12]
rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:10]
rv_plic_reg2hw_cc0_reg_t cc0; // [9:1]
rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
@@ -560,7 +680,7 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- rv_plic_hw2reg_ip_mreg_t [98:0] ip; // [204:7]
+ rv_plic_hw2reg_ip_mreg_t [122:0] ip; // [252:7]
rv_plic_hw2reg_cc0_reg_t cc0; // [6:0]
} rv_plic_hw2reg_t;
@@ -672,13 +792,37 @@
parameter logic [BlockAw-1:0] RV_PLIC_PRIO96_OFFSET = 10'h 1a0;
parameter logic [BlockAw-1:0] RV_PLIC_PRIO97_OFFSET = 10'h 1a4;
parameter logic [BlockAw-1:0] RV_PLIC_PRIO98_OFFSET = 10'h 1a8;
- parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 10'h 200;
- parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 10'h 204;
- parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 10'h 208;
- parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 10'h 20c;
- parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 210;
- parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 10'h 214;
- parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 10'h 218;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO99_OFFSET = 10'h 1ac;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO100_OFFSET = 10'h 1b0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO101_OFFSET = 10'h 1b4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO102_OFFSET = 10'h 1b8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO103_OFFSET = 10'h 1bc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO104_OFFSET = 10'h 1c0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO105_OFFSET = 10'h 1c4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO106_OFFSET = 10'h 1c8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO107_OFFSET = 10'h 1cc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO108_OFFSET = 10'h 1d0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO109_OFFSET = 10'h 1d4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO110_OFFSET = 10'h 1d8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO111_OFFSET = 10'h 1dc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO112_OFFSET = 10'h 1e0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO113_OFFSET = 10'h 1e4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO114_OFFSET = 10'h 1e8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO115_OFFSET = 10'h 1ec;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO116_OFFSET = 10'h 1f0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO117_OFFSET = 10'h 1f4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO118_OFFSET = 10'h 1f8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO119_OFFSET = 10'h 1fc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO120_OFFSET = 10'h 200;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO121_OFFSET = 10'h 204;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO122_OFFSET = 10'h 208;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 10'h 300;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 10'h 304;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 10'h 308;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 10'h 30c;
+ parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 310;
+ parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 10'h 314;
+ parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 10'h 318;
// Register Index
@@ -790,6 +934,30 @@
RV_PLIC_PRIO96,
RV_PLIC_PRIO97,
RV_PLIC_PRIO98,
+ RV_PLIC_PRIO99,
+ RV_PLIC_PRIO100,
+ RV_PLIC_PRIO101,
+ RV_PLIC_PRIO102,
+ RV_PLIC_PRIO103,
+ RV_PLIC_PRIO104,
+ RV_PLIC_PRIO105,
+ RV_PLIC_PRIO106,
+ RV_PLIC_PRIO107,
+ RV_PLIC_PRIO108,
+ RV_PLIC_PRIO109,
+ RV_PLIC_PRIO110,
+ RV_PLIC_PRIO111,
+ RV_PLIC_PRIO112,
+ RV_PLIC_PRIO113,
+ RV_PLIC_PRIO114,
+ RV_PLIC_PRIO115,
+ RV_PLIC_PRIO116,
+ RV_PLIC_PRIO117,
+ RV_PLIC_PRIO118,
+ RV_PLIC_PRIO119,
+ RV_PLIC_PRIO120,
+ RV_PLIC_PRIO121,
+ RV_PLIC_PRIO122,
RV_PLIC_IE0_0,
RV_PLIC_IE0_1,
RV_PLIC_IE0_2,
@@ -800,15 +968,15 @@
} rv_plic_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] RV_PLIC_PERMIT [114] = '{
+ parameter logic [3:0] RV_PLIC_PERMIT [138] = '{
4'b 1111, // index[ 0] RV_PLIC_IP_0
4'b 1111, // index[ 1] RV_PLIC_IP_1
4'b 1111, // index[ 2] RV_PLIC_IP_2
- 4'b 0001, // index[ 3] RV_PLIC_IP_3
+ 4'b 1111, // index[ 3] RV_PLIC_IP_3
4'b 1111, // index[ 4] RV_PLIC_LE_0
4'b 1111, // index[ 5] RV_PLIC_LE_1
4'b 1111, // index[ 6] RV_PLIC_LE_2
- 4'b 0001, // index[ 7] RV_PLIC_LE_3
+ 4'b 1111, // index[ 7] RV_PLIC_LE_3
4'b 0001, // index[ 8] RV_PLIC_PRIO0
4'b 0001, // index[ 9] RV_PLIC_PRIO1
4'b 0001, // index[ 10] RV_PLIC_PRIO2
@@ -908,13 +1076,37 @@
4'b 0001, // index[104] RV_PLIC_PRIO96
4'b 0001, // index[105] RV_PLIC_PRIO97
4'b 0001, // index[106] RV_PLIC_PRIO98
- 4'b 1111, // index[107] RV_PLIC_IE0_0
- 4'b 1111, // index[108] RV_PLIC_IE0_1
- 4'b 1111, // index[109] RV_PLIC_IE0_2
- 4'b 0001, // index[110] RV_PLIC_IE0_3
- 4'b 0001, // index[111] RV_PLIC_THRESHOLD0
- 4'b 0001, // index[112] RV_PLIC_CC0
- 4'b 0001 // index[113] RV_PLIC_MSIP0
+ 4'b 0001, // index[107] RV_PLIC_PRIO99
+ 4'b 0001, // index[108] RV_PLIC_PRIO100
+ 4'b 0001, // index[109] RV_PLIC_PRIO101
+ 4'b 0001, // index[110] RV_PLIC_PRIO102
+ 4'b 0001, // index[111] RV_PLIC_PRIO103
+ 4'b 0001, // index[112] RV_PLIC_PRIO104
+ 4'b 0001, // index[113] RV_PLIC_PRIO105
+ 4'b 0001, // index[114] RV_PLIC_PRIO106
+ 4'b 0001, // index[115] RV_PLIC_PRIO107
+ 4'b 0001, // index[116] RV_PLIC_PRIO108
+ 4'b 0001, // index[117] RV_PLIC_PRIO109
+ 4'b 0001, // index[118] RV_PLIC_PRIO110
+ 4'b 0001, // index[119] RV_PLIC_PRIO111
+ 4'b 0001, // index[120] RV_PLIC_PRIO112
+ 4'b 0001, // index[121] RV_PLIC_PRIO113
+ 4'b 0001, // index[122] RV_PLIC_PRIO114
+ 4'b 0001, // index[123] RV_PLIC_PRIO115
+ 4'b 0001, // index[124] RV_PLIC_PRIO116
+ 4'b 0001, // index[125] RV_PLIC_PRIO117
+ 4'b 0001, // index[126] RV_PLIC_PRIO118
+ 4'b 0001, // index[127] RV_PLIC_PRIO119
+ 4'b 0001, // index[128] RV_PLIC_PRIO120
+ 4'b 0001, // index[129] RV_PLIC_PRIO121
+ 4'b 0001, // index[130] RV_PLIC_PRIO122
+ 4'b 1111, // index[131] RV_PLIC_IE0_0
+ 4'b 1111, // index[132] RV_PLIC_IE0_1
+ 4'b 1111, // index[133] RV_PLIC_IE0_2
+ 4'b 1111, // index[134] RV_PLIC_IE0_3
+ 4'b 0001, // index[135] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[136] RV_PLIC_CC0
+ 4'b 0001 // index[137] RV_PLIC_MSIP0
};
endpackage
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index 7779c2a..d085332 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -170,6 +170,30 @@
logic ip_3_p_96_qs;
logic ip_3_p_97_qs;
logic ip_3_p_98_qs;
+ logic ip_3_p_99_qs;
+ logic ip_3_p_100_qs;
+ logic ip_3_p_101_qs;
+ logic ip_3_p_102_qs;
+ logic ip_3_p_103_qs;
+ logic ip_3_p_104_qs;
+ logic ip_3_p_105_qs;
+ logic ip_3_p_106_qs;
+ logic ip_3_p_107_qs;
+ logic ip_3_p_108_qs;
+ logic ip_3_p_109_qs;
+ logic ip_3_p_110_qs;
+ logic ip_3_p_111_qs;
+ logic ip_3_p_112_qs;
+ logic ip_3_p_113_qs;
+ logic ip_3_p_114_qs;
+ logic ip_3_p_115_qs;
+ logic ip_3_p_116_qs;
+ logic ip_3_p_117_qs;
+ logic ip_3_p_118_qs;
+ logic ip_3_p_119_qs;
+ logic ip_3_p_120_qs;
+ logic ip_3_p_121_qs;
+ logic ip_3_p_122_qs;
logic le_0_le_0_qs;
logic le_0_le_0_wd;
logic le_0_le_0_we;
@@ -467,6 +491,78 @@
logic le_3_le_98_qs;
logic le_3_le_98_wd;
logic le_3_le_98_we;
+ logic le_3_le_99_qs;
+ logic le_3_le_99_wd;
+ logic le_3_le_99_we;
+ logic le_3_le_100_qs;
+ logic le_3_le_100_wd;
+ logic le_3_le_100_we;
+ logic le_3_le_101_qs;
+ logic le_3_le_101_wd;
+ logic le_3_le_101_we;
+ logic le_3_le_102_qs;
+ logic le_3_le_102_wd;
+ logic le_3_le_102_we;
+ logic le_3_le_103_qs;
+ logic le_3_le_103_wd;
+ logic le_3_le_103_we;
+ logic le_3_le_104_qs;
+ logic le_3_le_104_wd;
+ logic le_3_le_104_we;
+ logic le_3_le_105_qs;
+ logic le_3_le_105_wd;
+ logic le_3_le_105_we;
+ logic le_3_le_106_qs;
+ logic le_3_le_106_wd;
+ logic le_3_le_106_we;
+ logic le_3_le_107_qs;
+ logic le_3_le_107_wd;
+ logic le_3_le_107_we;
+ logic le_3_le_108_qs;
+ logic le_3_le_108_wd;
+ logic le_3_le_108_we;
+ logic le_3_le_109_qs;
+ logic le_3_le_109_wd;
+ logic le_3_le_109_we;
+ logic le_3_le_110_qs;
+ logic le_3_le_110_wd;
+ logic le_3_le_110_we;
+ logic le_3_le_111_qs;
+ logic le_3_le_111_wd;
+ logic le_3_le_111_we;
+ logic le_3_le_112_qs;
+ logic le_3_le_112_wd;
+ logic le_3_le_112_we;
+ logic le_3_le_113_qs;
+ logic le_3_le_113_wd;
+ logic le_3_le_113_we;
+ logic le_3_le_114_qs;
+ logic le_3_le_114_wd;
+ logic le_3_le_114_we;
+ logic le_3_le_115_qs;
+ logic le_3_le_115_wd;
+ logic le_3_le_115_we;
+ logic le_3_le_116_qs;
+ logic le_3_le_116_wd;
+ logic le_3_le_116_we;
+ logic le_3_le_117_qs;
+ logic le_3_le_117_wd;
+ logic le_3_le_117_we;
+ logic le_3_le_118_qs;
+ logic le_3_le_118_wd;
+ logic le_3_le_118_we;
+ logic le_3_le_119_qs;
+ logic le_3_le_119_wd;
+ logic le_3_le_119_we;
+ logic le_3_le_120_qs;
+ logic le_3_le_120_wd;
+ logic le_3_le_120_we;
+ logic le_3_le_121_qs;
+ logic le_3_le_121_wd;
+ logic le_3_le_121_we;
+ logic le_3_le_122_qs;
+ logic le_3_le_122_wd;
+ logic le_3_le_122_we;
logic [1:0] prio0_qs;
logic [1:0] prio0_wd;
logic prio0_we;
@@ -764,6 +860,78 @@
logic [1:0] prio98_qs;
logic [1:0] prio98_wd;
logic prio98_we;
+ logic [1:0] prio99_qs;
+ logic [1:0] prio99_wd;
+ logic prio99_we;
+ logic [1:0] prio100_qs;
+ logic [1:0] prio100_wd;
+ logic prio100_we;
+ logic [1:0] prio101_qs;
+ logic [1:0] prio101_wd;
+ logic prio101_we;
+ logic [1:0] prio102_qs;
+ logic [1:0] prio102_wd;
+ logic prio102_we;
+ logic [1:0] prio103_qs;
+ logic [1:0] prio103_wd;
+ logic prio103_we;
+ logic [1:0] prio104_qs;
+ logic [1:0] prio104_wd;
+ logic prio104_we;
+ logic [1:0] prio105_qs;
+ logic [1:0] prio105_wd;
+ logic prio105_we;
+ logic [1:0] prio106_qs;
+ logic [1:0] prio106_wd;
+ logic prio106_we;
+ logic [1:0] prio107_qs;
+ logic [1:0] prio107_wd;
+ logic prio107_we;
+ logic [1:0] prio108_qs;
+ logic [1:0] prio108_wd;
+ logic prio108_we;
+ logic [1:0] prio109_qs;
+ logic [1:0] prio109_wd;
+ logic prio109_we;
+ logic [1:0] prio110_qs;
+ logic [1:0] prio110_wd;
+ logic prio110_we;
+ logic [1:0] prio111_qs;
+ logic [1:0] prio111_wd;
+ logic prio111_we;
+ logic [1:0] prio112_qs;
+ logic [1:0] prio112_wd;
+ logic prio112_we;
+ logic [1:0] prio113_qs;
+ logic [1:0] prio113_wd;
+ logic prio113_we;
+ logic [1:0] prio114_qs;
+ logic [1:0] prio114_wd;
+ logic prio114_we;
+ logic [1:0] prio115_qs;
+ logic [1:0] prio115_wd;
+ logic prio115_we;
+ logic [1:0] prio116_qs;
+ logic [1:0] prio116_wd;
+ logic prio116_we;
+ logic [1:0] prio117_qs;
+ logic [1:0] prio117_wd;
+ logic prio117_we;
+ logic [1:0] prio118_qs;
+ logic [1:0] prio118_wd;
+ logic prio118_we;
+ logic [1:0] prio119_qs;
+ logic [1:0] prio119_wd;
+ logic prio119_we;
+ logic [1:0] prio120_qs;
+ logic [1:0] prio120_wd;
+ logic prio120_we;
+ logic [1:0] prio121_qs;
+ logic [1:0] prio121_wd;
+ logic prio121_we;
+ logic [1:0] prio122_qs;
+ logic [1:0] prio122_wd;
+ logic prio122_we;
logic ie0_0_e_0_qs;
logic ie0_0_e_0_wd;
logic ie0_0_e_0_we;
@@ -1061,6 +1229,78 @@
logic ie0_3_e_98_qs;
logic ie0_3_e_98_wd;
logic ie0_3_e_98_we;
+ logic ie0_3_e_99_qs;
+ logic ie0_3_e_99_wd;
+ logic ie0_3_e_99_we;
+ logic ie0_3_e_100_qs;
+ logic ie0_3_e_100_wd;
+ logic ie0_3_e_100_we;
+ logic ie0_3_e_101_qs;
+ logic ie0_3_e_101_wd;
+ logic ie0_3_e_101_we;
+ logic ie0_3_e_102_qs;
+ logic ie0_3_e_102_wd;
+ logic ie0_3_e_102_we;
+ logic ie0_3_e_103_qs;
+ logic ie0_3_e_103_wd;
+ logic ie0_3_e_103_we;
+ logic ie0_3_e_104_qs;
+ logic ie0_3_e_104_wd;
+ logic ie0_3_e_104_we;
+ logic ie0_3_e_105_qs;
+ logic ie0_3_e_105_wd;
+ logic ie0_3_e_105_we;
+ logic ie0_3_e_106_qs;
+ logic ie0_3_e_106_wd;
+ logic ie0_3_e_106_we;
+ logic ie0_3_e_107_qs;
+ logic ie0_3_e_107_wd;
+ logic ie0_3_e_107_we;
+ logic ie0_3_e_108_qs;
+ logic ie0_3_e_108_wd;
+ logic ie0_3_e_108_we;
+ logic ie0_3_e_109_qs;
+ logic ie0_3_e_109_wd;
+ logic ie0_3_e_109_we;
+ logic ie0_3_e_110_qs;
+ logic ie0_3_e_110_wd;
+ logic ie0_3_e_110_we;
+ logic ie0_3_e_111_qs;
+ logic ie0_3_e_111_wd;
+ logic ie0_3_e_111_we;
+ logic ie0_3_e_112_qs;
+ logic ie0_3_e_112_wd;
+ logic ie0_3_e_112_we;
+ logic ie0_3_e_113_qs;
+ logic ie0_3_e_113_wd;
+ logic ie0_3_e_113_we;
+ logic ie0_3_e_114_qs;
+ logic ie0_3_e_114_wd;
+ logic ie0_3_e_114_we;
+ logic ie0_3_e_115_qs;
+ logic ie0_3_e_115_wd;
+ logic ie0_3_e_115_we;
+ logic ie0_3_e_116_qs;
+ logic ie0_3_e_116_wd;
+ logic ie0_3_e_116_we;
+ logic ie0_3_e_117_qs;
+ logic ie0_3_e_117_wd;
+ logic ie0_3_e_117_we;
+ logic ie0_3_e_118_qs;
+ logic ie0_3_e_118_wd;
+ logic ie0_3_e_118_we;
+ logic ie0_3_e_119_qs;
+ logic ie0_3_e_119_wd;
+ logic ie0_3_e_119_we;
+ logic ie0_3_e_120_qs;
+ logic ie0_3_e_120_wd;
+ logic ie0_3_e_120_we;
+ logic ie0_3_e_121_qs;
+ logic ie0_3_e_121_wd;
+ logic ie0_3_e_121_we;
+ logic ie0_3_e_122_qs;
+ logic ie0_3_e_122_wd;
+ logic ie0_3_e_122_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
logic threshold0_we;
@@ -3561,6 +3801,606 @@
);
+ // F[p_99]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_99 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[99].de),
+ .d (hw2reg.ip[99].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_99_qs)
+ );
+
+
+ // F[p_100]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_100 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[100].de),
+ .d (hw2reg.ip[100].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_100_qs)
+ );
+
+
+ // F[p_101]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_101 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[101].de),
+ .d (hw2reg.ip[101].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_101_qs)
+ );
+
+
+ // F[p_102]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_102 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[102].de),
+ .d (hw2reg.ip[102].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_102_qs)
+ );
+
+
+ // F[p_103]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_103 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[103].de),
+ .d (hw2reg.ip[103].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_103_qs)
+ );
+
+
+ // F[p_104]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_104 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[104].de),
+ .d (hw2reg.ip[104].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_104_qs)
+ );
+
+
+ // F[p_105]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_105 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[105].de),
+ .d (hw2reg.ip[105].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_105_qs)
+ );
+
+
+ // F[p_106]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_106 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[106].de),
+ .d (hw2reg.ip[106].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_106_qs)
+ );
+
+
+ // F[p_107]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_107 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[107].de),
+ .d (hw2reg.ip[107].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_107_qs)
+ );
+
+
+ // F[p_108]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_108 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[108].de),
+ .d (hw2reg.ip[108].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_108_qs)
+ );
+
+
+ // F[p_109]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_109 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[109].de),
+ .d (hw2reg.ip[109].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_109_qs)
+ );
+
+
+ // F[p_110]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_110 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[110].de),
+ .d (hw2reg.ip[110].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_110_qs)
+ );
+
+
+ // F[p_111]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_111 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[111].de),
+ .d (hw2reg.ip[111].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_111_qs)
+ );
+
+
+ // F[p_112]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_112 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[112].de),
+ .d (hw2reg.ip[112].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_112_qs)
+ );
+
+
+ // F[p_113]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_113 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[113].de),
+ .d (hw2reg.ip[113].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_113_qs)
+ );
+
+
+ // F[p_114]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_114 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[114].de),
+ .d (hw2reg.ip[114].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_114_qs)
+ );
+
+
+ // F[p_115]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_115 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[115].de),
+ .d (hw2reg.ip[115].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_115_qs)
+ );
+
+
+ // F[p_116]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_116 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[116].de),
+ .d (hw2reg.ip[116].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_116_qs)
+ );
+
+
+ // F[p_117]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_117 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[117].de),
+ .d (hw2reg.ip[117].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_117_qs)
+ );
+
+
+ // F[p_118]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_118 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[118].de),
+ .d (hw2reg.ip[118].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_118_qs)
+ );
+
+
+ // F[p_119]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_119 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[119].de),
+ .d (hw2reg.ip[119].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_119_qs)
+ );
+
+
+ // F[p_120]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_120 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[120].de),
+ .d (hw2reg.ip[120].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_120_qs)
+ );
+
+
+ // F[p_121]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_121 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[121].de),
+ .d (hw2reg.ip[121].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_121_qs)
+ );
+
+
+ // F[p_122]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_122 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[122].de),
+ .d (hw2reg.ip[122].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_122_qs)
+ );
+
+
// Subregister 0 of Multireg le
@@ -6149,6 +6989,630 @@
);
+ // F[le_99]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_99 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_99_we),
+ .wd (le_3_le_99_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[99].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_99_qs)
+ );
+
+
+ // F[le_100]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_100 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_100_we),
+ .wd (le_3_le_100_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[100].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_100_qs)
+ );
+
+
+ // F[le_101]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_101 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_101_we),
+ .wd (le_3_le_101_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[101].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_101_qs)
+ );
+
+
+ // F[le_102]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_102 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_102_we),
+ .wd (le_3_le_102_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[102].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_102_qs)
+ );
+
+
+ // F[le_103]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_103 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_103_we),
+ .wd (le_3_le_103_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[103].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_103_qs)
+ );
+
+
+ // F[le_104]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_104 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_104_we),
+ .wd (le_3_le_104_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[104].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_104_qs)
+ );
+
+
+ // F[le_105]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_105 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_105_we),
+ .wd (le_3_le_105_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[105].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_105_qs)
+ );
+
+
+ // F[le_106]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_106 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_106_we),
+ .wd (le_3_le_106_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[106].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_106_qs)
+ );
+
+
+ // F[le_107]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_107 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_107_we),
+ .wd (le_3_le_107_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[107].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_107_qs)
+ );
+
+
+ // F[le_108]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_108 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_108_we),
+ .wd (le_3_le_108_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[108].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_108_qs)
+ );
+
+
+ // F[le_109]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_109 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_109_we),
+ .wd (le_3_le_109_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[109].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_109_qs)
+ );
+
+
+ // F[le_110]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_110 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_110_we),
+ .wd (le_3_le_110_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[110].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_110_qs)
+ );
+
+
+ // F[le_111]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_111 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_111_we),
+ .wd (le_3_le_111_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[111].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_111_qs)
+ );
+
+
+ // F[le_112]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_112 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_112_we),
+ .wd (le_3_le_112_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[112].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_112_qs)
+ );
+
+
+ // F[le_113]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_113 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_113_we),
+ .wd (le_3_le_113_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[113].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_113_qs)
+ );
+
+
+ // F[le_114]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_114 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_114_we),
+ .wd (le_3_le_114_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[114].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_114_qs)
+ );
+
+
+ // F[le_115]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_115 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_115_we),
+ .wd (le_3_le_115_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[115].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_115_qs)
+ );
+
+
+ // F[le_116]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_116 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_116_we),
+ .wd (le_3_le_116_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[116].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_116_qs)
+ );
+
+
+ // F[le_117]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_117 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_117_we),
+ .wd (le_3_le_117_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[117].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_117_qs)
+ );
+
+
+ // F[le_118]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_118 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_118_we),
+ .wd (le_3_le_118_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[118].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_118_qs)
+ );
+
+
+ // F[le_119]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_119 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_119_we),
+ .wd (le_3_le_119_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[119].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_119_qs)
+ );
+
+
+ // F[le_120]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_120 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_120_we),
+ .wd (le_3_le_120_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[120].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_120_qs)
+ );
+
+
+ // F[le_121]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_121 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_121_we),
+ .wd (le_3_le_121_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[121].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_121_qs)
+ );
+
+
+ // F[le_122]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_122 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_122_we),
+ .wd (le_3_le_122_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[122].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_122_qs)
+ );
+
+
// R[prio0]: V(False)
@@ -8823,6 +10287,654 @@
);
+ // R[prio99]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio99 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio99_we),
+ .wd (prio99_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio99.q ),
+
+ // to register interface (read)
+ .qs (prio99_qs)
+ );
+
+
+ // R[prio100]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio100 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio100_we),
+ .wd (prio100_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio100.q ),
+
+ // to register interface (read)
+ .qs (prio100_qs)
+ );
+
+
+ // R[prio101]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio101 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio101_we),
+ .wd (prio101_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio101.q ),
+
+ // to register interface (read)
+ .qs (prio101_qs)
+ );
+
+
+ // R[prio102]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio102 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio102_we),
+ .wd (prio102_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio102.q ),
+
+ // to register interface (read)
+ .qs (prio102_qs)
+ );
+
+
+ // R[prio103]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio103 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio103_we),
+ .wd (prio103_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio103.q ),
+
+ // to register interface (read)
+ .qs (prio103_qs)
+ );
+
+
+ // R[prio104]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio104 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio104_we),
+ .wd (prio104_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio104.q ),
+
+ // to register interface (read)
+ .qs (prio104_qs)
+ );
+
+
+ // R[prio105]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio105 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio105_we),
+ .wd (prio105_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio105.q ),
+
+ // to register interface (read)
+ .qs (prio105_qs)
+ );
+
+
+ // R[prio106]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio106 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio106_we),
+ .wd (prio106_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio106.q ),
+
+ // to register interface (read)
+ .qs (prio106_qs)
+ );
+
+
+ // R[prio107]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio107 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio107_we),
+ .wd (prio107_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio107.q ),
+
+ // to register interface (read)
+ .qs (prio107_qs)
+ );
+
+
+ // R[prio108]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio108 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio108_we),
+ .wd (prio108_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio108.q ),
+
+ // to register interface (read)
+ .qs (prio108_qs)
+ );
+
+
+ // R[prio109]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio109 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio109_we),
+ .wd (prio109_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio109.q ),
+
+ // to register interface (read)
+ .qs (prio109_qs)
+ );
+
+
+ // R[prio110]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio110 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio110_we),
+ .wd (prio110_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio110.q ),
+
+ // to register interface (read)
+ .qs (prio110_qs)
+ );
+
+
+ // R[prio111]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio111 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio111_we),
+ .wd (prio111_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio111.q ),
+
+ // to register interface (read)
+ .qs (prio111_qs)
+ );
+
+
+ // R[prio112]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio112 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio112_we),
+ .wd (prio112_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio112.q ),
+
+ // to register interface (read)
+ .qs (prio112_qs)
+ );
+
+
+ // R[prio113]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio113 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio113_we),
+ .wd (prio113_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio113.q ),
+
+ // to register interface (read)
+ .qs (prio113_qs)
+ );
+
+
+ // R[prio114]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio114 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio114_we),
+ .wd (prio114_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio114.q ),
+
+ // to register interface (read)
+ .qs (prio114_qs)
+ );
+
+
+ // R[prio115]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio115 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio115_we),
+ .wd (prio115_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio115.q ),
+
+ // to register interface (read)
+ .qs (prio115_qs)
+ );
+
+
+ // R[prio116]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio116 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio116_we),
+ .wd (prio116_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio116.q ),
+
+ // to register interface (read)
+ .qs (prio116_qs)
+ );
+
+
+ // R[prio117]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio117 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio117_we),
+ .wd (prio117_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio117.q ),
+
+ // to register interface (read)
+ .qs (prio117_qs)
+ );
+
+
+ // R[prio118]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio118 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio118_we),
+ .wd (prio118_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio118.q ),
+
+ // to register interface (read)
+ .qs (prio118_qs)
+ );
+
+
+ // R[prio119]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio119 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio119_we),
+ .wd (prio119_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio119.q ),
+
+ // to register interface (read)
+ .qs (prio119_qs)
+ );
+
+
+ // R[prio120]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio120 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio120_we),
+ .wd (prio120_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio120.q ),
+
+ // to register interface (read)
+ .qs (prio120_qs)
+ );
+
+
+ // R[prio121]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio121 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio121_we),
+ .wd (prio121_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio121.q ),
+
+ // to register interface (read)
+ .qs (prio121_qs)
+ );
+
+
+ // R[prio122]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio122 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio122_we),
+ .wd (prio122_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio122.q ),
+
+ // to register interface (read)
+ .qs (prio122_qs)
+ );
+
+
// Subregister 0 of Multireg ie0
// R[ie0_0]: V(False)
@@ -11410,6 +13522,630 @@
);
+ // F[e_99]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_99 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_99_we),
+ .wd (ie0_3_e_99_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[99].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_99_qs)
+ );
+
+
+ // F[e_100]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_100 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_100_we),
+ .wd (ie0_3_e_100_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[100].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_100_qs)
+ );
+
+
+ // F[e_101]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_101 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_101_we),
+ .wd (ie0_3_e_101_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[101].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_101_qs)
+ );
+
+
+ // F[e_102]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_102 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_102_we),
+ .wd (ie0_3_e_102_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[102].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_102_qs)
+ );
+
+
+ // F[e_103]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_103 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_103_we),
+ .wd (ie0_3_e_103_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[103].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_103_qs)
+ );
+
+
+ // F[e_104]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_104 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_104_we),
+ .wd (ie0_3_e_104_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[104].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_104_qs)
+ );
+
+
+ // F[e_105]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_105 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_105_we),
+ .wd (ie0_3_e_105_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[105].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_105_qs)
+ );
+
+
+ // F[e_106]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_106 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_106_we),
+ .wd (ie0_3_e_106_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[106].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_106_qs)
+ );
+
+
+ // F[e_107]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_107 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_107_we),
+ .wd (ie0_3_e_107_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[107].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_107_qs)
+ );
+
+
+ // F[e_108]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_108 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_108_we),
+ .wd (ie0_3_e_108_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[108].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_108_qs)
+ );
+
+
+ // F[e_109]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_109 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_109_we),
+ .wd (ie0_3_e_109_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[109].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_109_qs)
+ );
+
+
+ // F[e_110]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_110 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_110_we),
+ .wd (ie0_3_e_110_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[110].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_110_qs)
+ );
+
+
+ // F[e_111]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_111 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_111_we),
+ .wd (ie0_3_e_111_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[111].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_111_qs)
+ );
+
+
+ // F[e_112]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_112 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_112_we),
+ .wd (ie0_3_e_112_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[112].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_112_qs)
+ );
+
+
+ // F[e_113]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_113 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_113_we),
+ .wd (ie0_3_e_113_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[113].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_113_qs)
+ );
+
+
+ // F[e_114]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_114 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_114_we),
+ .wd (ie0_3_e_114_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[114].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_114_qs)
+ );
+
+
+ // F[e_115]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_115 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_115_we),
+ .wd (ie0_3_e_115_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[115].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_115_qs)
+ );
+
+
+ // F[e_116]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_116 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_116_we),
+ .wd (ie0_3_e_116_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[116].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_116_qs)
+ );
+
+
+ // F[e_117]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_117 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_117_we),
+ .wd (ie0_3_e_117_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[117].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_117_qs)
+ );
+
+
+ // F[e_118]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_118 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_118_we),
+ .wd (ie0_3_e_118_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[118].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_118_qs)
+ );
+
+
+ // F[e_119]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_119 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_119_we),
+ .wd (ie0_3_e_119_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[119].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_119_qs)
+ );
+
+
+ // F[e_120]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_120 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_120_we),
+ .wd (ie0_3_e_120_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[120].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_120_qs)
+ );
+
+
+ // F[e_121]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_121 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_121_we),
+ .wd (ie0_3_e_121_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[121].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_121_qs)
+ );
+
+
+ // F[e_122]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_122 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_122_we),
+ .wd (ie0_3_e_122_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[122].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_122_qs)
+ );
+
+
// R[threshold0]: V(False)
@@ -11483,7 +14219,7 @@
- logic [113:0] addr_hit;
+ logic [137:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == RV_PLIC_IP_0_OFFSET);
@@ -11593,13 +14329,37 @@
addr_hit[104] = (reg_addr == RV_PLIC_PRIO96_OFFSET);
addr_hit[105] = (reg_addr == RV_PLIC_PRIO97_OFFSET);
addr_hit[106] = (reg_addr == RV_PLIC_PRIO98_OFFSET);
- addr_hit[107] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
- addr_hit[108] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
- addr_hit[109] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
- addr_hit[110] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
- addr_hit[111] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
- addr_hit[112] = (reg_addr == RV_PLIC_CC0_OFFSET);
- addr_hit[113] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+ addr_hit[107] = (reg_addr == RV_PLIC_PRIO99_OFFSET);
+ addr_hit[108] = (reg_addr == RV_PLIC_PRIO100_OFFSET);
+ addr_hit[109] = (reg_addr == RV_PLIC_PRIO101_OFFSET);
+ addr_hit[110] = (reg_addr == RV_PLIC_PRIO102_OFFSET);
+ addr_hit[111] = (reg_addr == RV_PLIC_PRIO103_OFFSET);
+ addr_hit[112] = (reg_addr == RV_PLIC_PRIO104_OFFSET);
+ addr_hit[113] = (reg_addr == RV_PLIC_PRIO105_OFFSET);
+ addr_hit[114] = (reg_addr == RV_PLIC_PRIO106_OFFSET);
+ addr_hit[115] = (reg_addr == RV_PLIC_PRIO107_OFFSET);
+ addr_hit[116] = (reg_addr == RV_PLIC_PRIO108_OFFSET);
+ addr_hit[117] = (reg_addr == RV_PLIC_PRIO109_OFFSET);
+ addr_hit[118] = (reg_addr == RV_PLIC_PRIO110_OFFSET);
+ addr_hit[119] = (reg_addr == RV_PLIC_PRIO111_OFFSET);
+ addr_hit[120] = (reg_addr == RV_PLIC_PRIO112_OFFSET);
+ addr_hit[121] = (reg_addr == RV_PLIC_PRIO113_OFFSET);
+ addr_hit[122] = (reg_addr == RV_PLIC_PRIO114_OFFSET);
+ addr_hit[123] = (reg_addr == RV_PLIC_PRIO115_OFFSET);
+ addr_hit[124] = (reg_addr == RV_PLIC_PRIO116_OFFSET);
+ addr_hit[125] = (reg_addr == RV_PLIC_PRIO117_OFFSET);
+ addr_hit[126] = (reg_addr == RV_PLIC_PRIO118_OFFSET);
+ addr_hit[127] = (reg_addr == RV_PLIC_PRIO119_OFFSET);
+ addr_hit[128] = (reg_addr == RV_PLIC_PRIO120_OFFSET);
+ addr_hit[129] = (reg_addr == RV_PLIC_PRIO121_OFFSET);
+ addr_hit[130] = (reg_addr == RV_PLIC_PRIO122_OFFSET);
+ addr_hit[131] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
+ addr_hit[132] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
+ addr_hit[133] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
+ addr_hit[134] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
+ addr_hit[135] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+ addr_hit[136] = (reg_addr == RV_PLIC_CC0_OFFSET);
+ addr_hit[137] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -11721,6 +14481,30 @@
if (addr_hit[111] && reg_we && (RV_PLIC_PERMIT[111] != (RV_PLIC_PERMIT[111] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[112] && reg_we && (RV_PLIC_PERMIT[112] != (RV_PLIC_PERMIT[112] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[113] && reg_we && (RV_PLIC_PERMIT[113] != (RV_PLIC_PERMIT[113] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[114] && reg_we && (RV_PLIC_PERMIT[114] != (RV_PLIC_PERMIT[114] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[115] && reg_we && (RV_PLIC_PERMIT[115] != (RV_PLIC_PERMIT[115] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[116] && reg_we && (RV_PLIC_PERMIT[116] != (RV_PLIC_PERMIT[116] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[117] && reg_we && (RV_PLIC_PERMIT[117] != (RV_PLIC_PERMIT[117] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[118] && reg_we && (RV_PLIC_PERMIT[118] != (RV_PLIC_PERMIT[118] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[119] && reg_we && (RV_PLIC_PERMIT[119] != (RV_PLIC_PERMIT[119] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[120] && reg_we && (RV_PLIC_PERMIT[120] != (RV_PLIC_PERMIT[120] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[121] && reg_we && (RV_PLIC_PERMIT[121] != (RV_PLIC_PERMIT[121] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[122] && reg_we && (RV_PLIC_PERMIT[122] != (RV_PLIC_PERMIT[122] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[123] && reg_we && (RV_PLIC_PERMIT[123] != (RV_PLIC_PERMIT[123] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[124] && reg_we && (RV_PLIC_PERMIT[124] != (RV_PLIC_PERMIT[124] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[125] && reg_we && (RV_PLIC_PERMIT[125] != (RV_PLIC_PERMIT[125] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[126] && reg_we && (RV_PLIC_PERMIT[126] != (RV_PLIC_PERMIT[126] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[127] && reg_we && (RV_PLIC_PERMIT[127] != (RV_PLIC_PERMIT[127] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[128] && reg_we && (RV_PLIC_PERMIT[128] != (RV_PLIC_PERMIT[128] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[129] && reg_we && (RV_PLIC_PERMIT[129] != (RV_PLIC_PERMIT[129] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[130] && reg_we && (RV_PLIC_PERMIT[130] != (RV_PLIC_PERMIT[130] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[131] && reg_we && (RV_PLIC_PERMIT[131] != (RV_PLIC_PERMIT[131] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[132] && reg_we && (RV_PLIC_PERMIT[132] != (RV_PLIC_PERMIT[132] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[133] && reg_we && (RV_PLIC_PERMIT[133] != (RV_PLIC_PERMIT[133] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[134] && reg_we && (RV_PLIC_PERMIT[134] != (RV_PLIC_PERMIT[134] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[135] && reg_we && (RV_PLIC_PERMIT[135] != (RV_PLIC_PERMIT[135] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[136] && reg_we && (RV_PLIC_PERMIT[136] != (RV_PLIC_PERMIT[136] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[137] && reg_we && (RV_PLIC_PERMIT[137] != (RV_PLIC_PERMIT[137] & reg_be))) wr_err = 1'b1 ;
end
@@ -11822,6 +14606,30 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
assign le_0_le_0_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_0_wd = reg_wdata[0];
@@ -12119,6 +14927,78 @@
assign le_3_le_98_we = addr_hit[7] & reg_we & ~wr_err;
assign le_3_le_98_wd = reg_wdata[2];
+ assign le_3_le_99_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_99_wd = reg_wdata[3];
+
+ assign le_3_le_100_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_100_wd = reg_wdata[4];
+
+ assign le_3_le_101_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_101_wd = reg_wdata[5];
+
+ assign le_3_le_102_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_102_wd = reg_wdata[6];
+
+ assign le_3_le_103_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_103_wd = reg_wdata[7];
+
+ assign le_3_le_104_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_104_wd = reg_wdata[8];
+
+ assign le_3_le_105_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_105_wd = reg_wdata[9];
+
+ assign le_3_le_106_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_106_wd = reg_wdata[10];
+
+ assign le_3_le_107_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_107_wd = reg_wdata[11];
+
+ assign le_3_le_108_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_108_wd = reg_wdata[12];
+
+ assign le_3_le_109_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_109_wd = reg_wdata[13];
+
+ assign le_3_le_110_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_110_wd = reg_wdata[14];
+
+ assign le_3_le_111_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_111_wd = reg_wdata[15];
+
+ assign le_3_le_112_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_112_wd = reg_wdata[16];
+
+ assign le_3_le_113_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_113_wd = reg_wdata[17];
+
+ assign le_3_le_114_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_114_wd = reg_wdata[18];
+
+ assign le_3_le_115_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_115_wd = reg_wdata[19];
+
+ assign le_3_le_116_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_116_wd = reg_wdata[20];
+
+ assign le_3_le_117_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_117_wd = reg_wdata[21];
+
+ assign le_3_le_118_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_118_wd = reg_wdata[22];
+
+ assign le_3_le_119_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_119_wd = reg_wdata[23];
+
+ assign le_3_le_120_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_120_wd = reg_wdata[24];
+
+ assign le_3_le_121_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_121_wd = reg_wdata[25];
+
+ assign le_3_le_122_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_122_wd = reg_wdata[26];
+
assign prio0_we = addr_hit[8] & reg_we & ~wr_err;
assign prio0_wd = reg_wdata[1:0];
@@ -12416,311 +15296,455 @@
assign prio98_we = addr_hit[106] & reg_we & ~wr_err;
assign prio98_wd = reg_wdata[1:0];
- assign ie0_0_e_0_we = addr_hit[107] & reg_we & ~wr_err;
+ assign prio99_we = addr_hit[107] & reg_we & ~wr_err;
+ assign prio99_wd = reg_wdata[1:0];
+
+ assign prio100_we = addr_hit[108] & reg_we & ~wr_err;
+ assign prio100_wd = reg_wdata[1:0];
+
+ assign prio101_we = addr_hit[109] & reg_we & ~wr_err;
+ assign prio101_wd = reg_wdata[1:0];
+
+ assign prio102_we = addr_hit[110] & reg_we & ~wr_err;
+ assign prio102_wd = reg_wdata[1:0];
+
+ assign prio103_we = addr_hit[111] & reg_we & ~wr_err;
+ assign prio103_wd = reg_wdata[1:0];
+
+ assign prio104_we = addr_hit[112] & reg_we & ~wr_err;
+ assign prio104_wd = reg_wdata[1:0];
+
+ assign prio105_we = addr_hit[113] & reg_we & ~wr_err;
+ assign prio105_wd = reg_wdata[1:0];
+
+ assign prio106_we = addr_hit[114] & reg_we & ~wr_err;
+ assign prio106_wd = reg_wdata[1:0];
+
+ assign prio107_we = addr_hit[115] & reg_we & ~wr_err;
+ assign prio107_wd = reg_wdata[1:0];
+
+ assign prio108_we = addr_hit[116] & reg_we & ~wr_err;
+ assign prio108_wd = reg_wdata[1:0];
+
+ assign prio109_we = addr_hit[117] & reg_we & ~wr_err;
+ assign prio109_wd = reg_wdata[1:0];
+
+ assign prio110_we = addr_hit[118] & reg_we & ~wr_err;
+ assign prio110_wd = reg_wdata[1:0];
+
+ assign prio111_we = addr_hit[119] & reg_we & ~wr_err;
+ assign prio111_wd = reg_wdata[1:0];
+
+ assign prio112_we = addr_hit[120] & reg_we & ~wr_err;
+ assign prio112_wd = reg_wdata[1:0];
+
+ assign prio113_we = addr_hit[121] & reg_we & ~wr_err;
+ assign prio113_wd = reg_wdata[1:0];
+
+ assign prio114_we = addr_hit[122] & reg_we & ~wr_err;
+ assign prio114_wd = reg_wdata[1:0];
+
+ assign prio115_we = addr_hit[123] & reg_we & ~wr_err;
+ assign prio115_wd = reg_wdata[1:0];
+
+ assign prio116_we = addr_hit[124] & reg_we & ~wr_err;
+ assign prio116_wd = reg_wdata[1:0];
+
+ assign prio117_we = addr_hit[125] & reg_we & ~wr_err;
+ assign prio117_wd = reg_wdata[1:0];
+
+ assign prio118_we = addr_hit[126] & reg_we & ~wr_err;
+ assign prio118_wd = reg_wdata[1:0];
+
+ assign prio119_we = addr_hit[127] & reg_we & ~wr_err;
+ assign prio119_wd = reg_wdata[1:0];
+
+ assign prio120_we = addr_hit[128] & reg_we & ~wr_err;
+ assign prio120_wd = reg_wdata[1:0];
+
+ assign prio121_we = addr_hit[129] & reg_we & ~wr_err;
+ assign prio121_wd = reg_wdata[1:0];
+
+ assign prio122_we = addr_hit[130] & reg_we & ~wr_err;
+ assign prio122_wd = reg_wdata[1:0];
+
+ assign ie0_0_e_0_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_0_wd = reg_wdata[0];
- assign ie0_0_e_1_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_1_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_1_wd = reg_wdata[1];
- assign ie0_0_e_2_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_2_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_2_wd = reg_wdata[2];
- assign ie0_0_e_3_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_3_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_3_wd = reg_wdata[3];
- assign ie0_0_e_4_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_4_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_4_wd = reg_wdata[4];
- assign ie0_0_e_5_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_5_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_5_wd = reg_wdata[5];
- assign ie0_0_e_6_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_6_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_6_wd = reg_wdata[6];
- assign ie0_0_e_7_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_7_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_7_wd = reg_wdata[7];
- assign ie0_0_e_8_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_8_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_8_wd = reg_wdata[8];
- assign ie0_0_e_9_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_9_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_9_wd = reg_wdata[9];
- assign ie0_0_e_10_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_10_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_10_wd = reg_wdata[10];
- assign ie0_0_e_11_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_11_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_11_wd = reg_wdata[11];
- assign ie0_0_e_12_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_12_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_12_wd = reg_wdata[12];
- assign ie0_0_e_13_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_13_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_13_wd = reg_wdata[13];
- assign ie0_0_e_14_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_14_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_14_wd = reg_wdata[14];
- assign ie0_0_e_15_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_15_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_15_wd = reg_wdata[15];
- assign ie0_0_e_16_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_16_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_16_wd = reg_wdata[16];
- assign ie0_0_e_17_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_17_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_17_wd = reg_wdata[17];
- assign ie0_0_e_18_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_18_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_18_wd = reg_wdata[18];
- assign ie0_0_e_19_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_19_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_19_wd = reg_wdata[19];
- assign ie0_0_e_20_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_20_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_20_wd = reg_wdata[20];
- assign ie0_0_e_21_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_21_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_21_wd = reg_wdata[21];
- assign ie0_0_e_22_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_22_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_22_wd = reg_wdata[22];
- assign ie0_0_e_23_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_23_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_23_wd = reg_wdata[23];
- assign ie0_0_e_24_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_24_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_24_wd = reg_wdata[24];
- assign ie0_0_e_25_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_25_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_25_wd = reg_wdata[25];
- assign ie0_0_e_26_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_26_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_26_wd = reg_wdata[26];
- assign ie0_0_e_27_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_27_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_27_wd = reg_wdata[27];
- assign ie0_0_e_28_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_28_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_28_wd = reg_wdata[28];
- assign ie0_0_e_29_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_29_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_29_wd = reg_wdata[29];
- assign ie0_0_e_30_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_30_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_30_wd = reg_wdata[30];
- assign ie0_0_e_31_we = addr_hit[107] & reg_we & ~wr_err;
+ assign ie0_0_e_31_we = addr_hit[131] & reg_we & ~wr_err;
assign ie0_0_e_31_wd = reg_wdata[31];
- assign ie0_1_e_32_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_32_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_32_wd = reg_wdata[0];
- assign ie0_1_e_33_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_33_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_33_wd = reg_wdata[1];
- assign ie0_1_e_34_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_34_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_34_wd = reg_wdata[2];
- assign ie0_1_e_35_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_35_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_35_wd = reg_wdata[3];
- assign ie0_1_e_36_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_36_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_36_wd = reg_wdata[4];
- assign ie0_1_e_37_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_37_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_37_wd = reg_wdata[5];
- assign ie0_1_e_38_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_38_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_38_wd = reg_wdata[6];
- assign ie0_1_e_39_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_39_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_39_wd = reg_wdata[7];
- assign ie0_1_e_40_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_40_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_40_wd = reg_wdata[8];
- assign ie0_1_e_41_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_41_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_41_wd = reg_wdata[9];
- assign ie0_1_e_42_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_42_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_42_wd = reg_wdata[10];
- assign ie0_1_e_43_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_43_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_43_wd = reg_wdata[11];
- assign ie0_1_e_44_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_44_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_44_wd = reg_wdata[12];
- assign ie0_1_e_45_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_45_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_45_wd = reg_wdata[13];
- assign ie0_1_e_46_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_46_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_46_wd = reg_wdata[14];
- assign ie0_1_e_47_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_47_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_47_wd = reg_wdata[15];
- assign ie0_1_e_48_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_48_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_48_wd = reg_wdata[16];
- assign ie0_1_e_49_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_49_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_49_wd = reg_wdata[17];
- assign ie0_1_e_50_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_50_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_50_wd = reg_wdata[18];
- assign ie0_1_e_51_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_51_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_51_wd = reg_wdata[19];
- assign ie0_1_e_52_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_52_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_52_wd = reg_wdata[20];
- assign ie0_1_e_53_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_53_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_53_wd = reg_wdata[21];
- assign ie0_1_e_54_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_54_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_54_wd = reg_wdata[22];
- assign ie0_1_e_55_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_55_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_55_wd = reg_wdata[23];
- assign ie0_1_e_56_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_56_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_56_wd = reg_wdata[24];
- assign ie0_1_e_57_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_57_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_57_wd = reg_wdata[25];
- assign ie0_1_e_58_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_58_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_58_wd = reg_wdata[26];
- assign ie0_1_e_59_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_59_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_59_wd = reg_wdata[27];
- assign ie0_1_e_60_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_60_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_60_wd = reg_wdata[28];
- assign ie0_1_e_61_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_61_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_61_wd = reg_wdata[29];
- assign ie0_1_e_62_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_62_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_62_wd = reg_wdata[30];
- assign ie0_1_e_63_we = addr_hit[108] & reg_we & ~wr_err;
+ assign ie0_1_e_63_we = addr_hit[132] & reg_we & ~wr_err;
assign ie0_1_e_63_wd = reg_wdata[31];
- assign ie0_2_e_64_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_64_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_64_wd = reg_wdata[0];
- assign ie0_2_e_65_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_65_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_65_wd = reg_wdata[1];
- assign ie0_2_e_66_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_66_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_66_wd = reg_wdata[2];
- assign ie0_2_e_67_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_67_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_67_wd = reg_wdata[3];
- assign ie0_2_e_68_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_68_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_68_wd = reg_wdata[4];
- assign ie0_2_e_69_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_69_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_69_wd = reg_wdata[5];
- assign ie0_2_e_70_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_70_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_70_wd = reg_wdata[6];
- assign ie0_2_e_71_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_71_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_71_wd = reg_wdata[7];
- assign ie0_2_e_72_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_72_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_72_wd = reg_wdata[8];
- assign ie0_2_e_73_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_73_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_73_wd = reg_wdata[9];
- assign ie0_2_e_74_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_74_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_74_wd = reg_wdata[10];
- assign ie0_2_e_75_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_75_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_75_wd = reg_wdata[11];
- assign ie0_2_e_76_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_76_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_76_wd = reg_wdata[12];
- assign ie0_2_e_77_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_77_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_77_wd = reg_wdata[13];
- assign ie0_2_e_78_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_78_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_78_wd = reg_wdata[14];
- assign ie0_2_e_79_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_79_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_79_wd = reg_wdata[15];
- assign ie0_2_e_80_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_80_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_80_wd = reg_wdata[16];
- assign ie0_2_e_81_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_81_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_81_wd = reg_wdata[17];
- assign ie0_2_e_82_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_82_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_82_wd = reg_wdata[18];
- assign ie0_2_e_83_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_83_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_83_wd = reg_wdata[19];
- assign ie0_2_e_84_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_84_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_84_wd = reg_wdata[20];
- assign ie0_2_e_85_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_85_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_85_wd = reg_wdata[21];
- assign ie0_2_e_86_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_86_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_86_wd = reg_wdata[22];
- assign ie0_2_e_87_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_87_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_87_wd = reg_wdata[23];
- assign ie0_2_e_88_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_88_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_88_wd = reg_wdata[24];
- assign ie0_2_e_89_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_89_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_89_wd = reg_wdata[25];
- assign ie0_2_e_90_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_90_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_90_wd = reg_wdata[26];
- assign ie0_2_e_91_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_91_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_91_wd = reg_wdata[27];
- assign ie0_2_e_92_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_92_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_92_wd = reg_wdata[28];
- assign ie0_2_e_93_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_93_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_93_wd = reg_wdata[29];
- assign ie0_2_e_94_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_94_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_94_wd = reg_wdata[30];
- assign ie0_2_e_95_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_95_we = addr_hit[133] & reg_we & ~wr_err;
assign ie0_2_e_95_wd = reg_wdata[31];
- assign ie0_3_e_96_we = addr_hit[110] & reg_we & ~wr_err;
+ assign ie0_3_e_96_we = addr_hit[134] & reg_we & ~wr_err;
assign ie0_3_e_96_wd = reg_wdata[0];
- assign ie0_3_e_97_we = addr_hit[110] & reg_we & ~wr_err;
+ assign ie0_3_e_97_we = addr_hit[134] & reg_we & ~wr_err;
assign ie0_3_e_97_wd = reg_wdata[1];
- assign ie0_3_e_98_we = addr_hit[110] & reg_we & ~wr_err;
+ assign ie0_3_e_98_we = addr_hit[134] & reg_we & ~wr_err;
assign ie0_3_e_98_wd = reg_wdata[2];
- assign threshold0_we = addr_hit[111] & reg_we & ~wr_err;
+ assign ie0_3_e_99_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_99_wd = reg_wdata[3];
+
+ assign ie0_3_e_100_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_100_wd = reg_wdata[4];
+
+ assign ie0_3_e_101_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_101_wd = reg_wdata[5];
+
+ assign ie0_3_e_102_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_102_wd = reg_wdata[6];
+
+ assign ie0_3_e_103_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_103_wd = reg_wdata[7];
+
+ assign ie0_3_e_104_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_104_wd = reg_wdata[8];
+
+ assign ie0_3_e_105_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_105_wd = reg_wdata[9];
+
+ assign ie0_3_e_106_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_106_wd = reg_wdata[10];
+
+ assign ie0_3_e_107_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_107_wd = reg_wdata[11];
+
+ assign ie0_3_e_108_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_108_wd = reg_wdata[12];
+
+ assign ie0_3_e_109_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_109_wd = reg_wdata[13];
+
+ assign ie0_3_e_110_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_110_wd = reg_wdata[14];
+
+ assign ie0_3_e_111_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_111_wd = reg_wdata[15];
+
+ assign ie0_3_e_112_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_112_wd = reg_wdata[16];
+
+ assign ie0_3_e_113_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_113_wd = reg_wdata[17];
+
+ assign ie0_3_e_114_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_114_wd = reg_wdata[18];
+
+ assign ie0_3_e_115_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_115_wd = reg_wdata[19];
+
+ assign ie0_3_e_116_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_116_wd = reg_wdata[20];
+
+ assign ie0_3_e_117_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_117_wd = reg_wdata[21];
+
+ assign ie0_3_e_118_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_118_wd = reg_wdata[22];
+
+ assign ie0_3_e_119_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_119_wd = reg_wdata[23];
+
+ assign ie0_3_e_120_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_120_wd = reg_wdata[24];
+
+ assign ie0_3_e_121_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_121_wd = reg_wdata[25];
+
+ assign ie0_3_e_122_we = addr_hit[134] & reg_we & ~wr_err;
+ assign ie0_3_e_122_wd = reg_wdata[26];
+
+ assign threshold0_we = addr_hit[135] & reg_we & ~wr_err;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_we = addr_hit[112] & reg_we & ~wr_err;
+ assign cc0_we = addr_hit[136] & reg_we & ~wr_err;
assign cc0_wd = reg_wdata[6:0];
- assign cc0_re = addr_hit[112] && reg_re;
+ assign cc0_re = addr_hit[136] && reg_re;
- assign msip0_we = addr_hit[113] & reg_we & ~wr_err;
+ assign msip0_we = addr_hit[137] & reg_we & ~wr_err;
assign msip0_wd = reg_wdata[0];
// Read data return
@@ -12836,6 +15860,30 @@
reg_rdata_next[0] = ip_3_p_96_qs;
reg_rdata_next[1] = ip_3_p_97_qs;
reg_rdata_next[2] = ip_3_p_98_qs;
+ reg_rdata_next[3] = ip_3_p_99_qs;
+ reg_rdata_next[4] = ip_3_p_100_qs;
+ reg_rdata_next[5] = ip_3_p_101_qs;
+ reg_rdata_next[6] = ip_3_p_102_qs;
+ reg_rdata_next[7] = ip_3_p_103_qs;
+ reg_rdata_next[8] = ip_3_p_104_qs;
+ reg_rdata_next[9] = ip_3_p_105_qs;
+ reg_rdata_next[10] = ip_3_p_106_qs;
+ reg_rdata_next[11] = ip_3_p_107_qs;
+ reg_rdata_next[12] = ip_3_p_108_qs;
+ reg_rdata_next[13] = ip_3_p_109_qs;
+ reg_rdata_next[14] = ip_3_p_110_qs;
+ reg_rdata_next[15] = ip_3_p_111_qs;
+ reg_rdata_next[16] = ip_3_p_112_qs;
+ reg_rdata_next[17] = ip_3_p_113_qs;
+ reg_rdata_next[18] = ip_3_p_114_qs;
+ reg_rdata_next[19] = ip_3_p_115_qs;
+ reg_rdata_next[20] = ip_3_p_116_qs;
+ reg_rdata_next[21] = ip_3_p_117_qs;
+ reg_rdata_next[22] = ip_3_p_118_qs;
+ reg_rdata_next[23] = ip_3_p_119_qs;
+ reg_rdata_next[24] = ip_3_p_120_qs;
+ reg_rdata_next[25] = ip_3_p_121_qs;
+ reg_rdata_next[26] = ip_3_p_122_qs;
end
addr_hit[4]: begin
@@ -12947,6 +15995,30 @@
reg_rdata_next[0] = le_3_le_96_qs;
reg_rdata_next[1] = le_3_le_97_qs;
reg_rdata_next[2] = le_3_le_98_qs;
+ reg_rdata_next[3] = le_3_le_99_qs;
+ reg_rdata_next[4] = le_3_le_100_qs;
+ reg_rdata_next[5] = le_3_le_101_qs;
+ reg_rdata_next[6] = le_3_le_102_qs;
+ reg_rdata_next[7] = le_3_le_103_qs;
+ reg_rdata_next[8] = le_3_le_104_qs;
+ reg_rdata_next[9] = le_3_le_105_qs;
+ reg_rdata_next[10] = le_3_le_106_qs;
+ reg_rdata_next[11] = le_3_le_107_qs;
+ reg_rdata_next[12] = le_3_le_108_qs;
+ reg_rdata_next[13] = le_3_le_109_qs;
+ reg_rdata_next[14] = le_3_le_110_qs;
+ reg_rdata_next[15] = le_3_le_111_qs;
+ reg_rdata_next[16] = le_3_le_112_qs;
+ reg_rdata_next[17] = le_3_le_113_qs;
+ reg_rdata_next[18] = le_3_le_114_qs;
+ reg_rdata_next[19] = le_3_le_115_qs;
+ reg_rdata_next[20] = le_3_le_116_qs;
+ reg_rdata_next[21] = le_3_le_117_qs;
+ reg_rdata_next[22] = le_3_le_118_qs;
+ reg_rdata_next[23] = le_3_le_119_qs;
+ reg_rdata_next[24] = le_3_le_120_qs;
+ reg_rdata_next[25] = le_3_le_121_qs;
+ reg_rdata_next[26] = le_3_le_122_qs;
end
addr_hit[8]: begin
@@ -13346,6 +16418,102 @@
end
addr_hit[107]: begin
+ reg_rdata_next[1:0] = prio99_qs;
+ end
+
+ addr_hit[108]: begin
+ reg_rdata_next[1:0] = prio100_qs;
+ end
+
+ addr_hit[109]: begin
+ reg_rdata_next[1:0] = prio101_qs;
+ end
+
+ addr_hit[110]: begin
+ reg_rdata_next[1:0] = prio102_qs;
+ end
+
+ addr_hit[111]: begin
+ reg_rdata_next[1:0] = prio103_qs;
+ end
+
+ addr_hit[112]: begin
+ reg_rdata_next[1:0] = prio104_qs;
+ end
+
+ addr_hit[113]: begin
+ reg_rdata_next[1:0] = prio105_qs;
+ end
+
+ addr_hit[114]: begin
+ reg_rdata_next[1:0] = prio106_qs;
+ end
+
+ addr_hit[115]: begin
+ reg_rdata_next[1:0] = prio107_qs;
+ end
+
+ addr_hit[116]: begin
+ reg_rdata_next[1:0] = prio108_qs;
+ end
+
+ addr_hit[117]: begin
+ reg_rdata_next[1:0] = prio109_qs;
+ end
+
+ addr_hit[118]: begin
+ reg_rdata_next[1:0] = prio110_qs;
+ end
+
+ addr_hit[119]: begin
+ reg_rdata_next[1:0] = prio111_qs;
+ end
+
+ addr_hit[120]: begin
+ reg_rdata_next[1:0] = prio112_qs;
+ end
+
+ addr_hit[121]: begin
+ reg_rdata_next[1:0] = prio113_qs;
+ end
+
+ addr_hit[122]: begin
+ reg_rdata_next[1:0] = prio114_qs;
+ end
+
+ addr_hit[123]: begin
+ reg_rdata_next[1:0] = prio115_qs;
+ end
+
+ addr_hit[124]: begin
+ reg_rdata_next[1:0] = prio116_qs;
+ end
+
+ addr_hit[125]: begin
+ reg_rdata_next[1:0] = prio117_qs;
+ end
+
+ addr_hit[126]: begin
+ reg_rdata_next[1:0] = prio118_qs;
+ end
+
+ addr_hit[127]: begin
+ reg_rdata_next[1:0] = prio119_qs;
+ end
+
+ addr_hit[128]: begin
+ reg_rdata_next[1:0] = prio120_qs;
+ end
+
+ addr_hit[129]: begin
+ reg_rdata_next[1:0] = prio121_qs;
+ end
+
+ addr_hit[130]: begin
+ reg_rdata_next[1:0] = prio122_qs;
+ end
+
+ addr_hit[131]: begin
reg_rdata_next[0] = ie0_0_e_0_qs;
reg_rdata_next[1] = ie0_0_e_1_qs;
reg_rdata_next[2] = ie0_0_e_2_qs;
@@ -13380,7 +16548,7 @@
reg_rdata_next[31] = ie0_0_e_31_qs;
end
- addr_hit[108]: begin
+ addr_hit[132]: begin
reg_rdata_next[0] = ie0_1_e_32_qs;
reg_rdata_next[1] = ie0_1_e_33_qs;
reg_rdata_next[2] = ie0_1_e_34_qs;
@@ -13415,7 +16583,7 @@
reg_rdata_next[31] = ie0_1_e_63_qs;
end
- addr_hit[109]: begin
+ addr_hit[133]: begin
reg_rdata_next[0] = ie0_2_e_64_qs;
reg_rdata_next[1] = ie0_2_e_65_qs;
reg_rdata_next[2] = ie0_2_e_66_qs;
@@ -13450,21 +16618,45 @@
reg_rdata_next[31] = ie0_2_e_95_qs;
end
- addr_hit[110]: begin
+ addr_hit[134]: begin
reg_rdata_next[0] = ie0_3_e_96_qs;
reg_rdata_next[1] = ie0_3_e_97_qs;
reg_rdata_next[2] = ie0_3_e_98_qs;
+ reg_rdata_next[3] = ie0_3_e_99_qs;
+ reg_rdata_next[4] = ie0_3_e_100_qs;
+ reg_rdata_next[5] = ie0_3_e_101_qs;
+ reg_rdata_next[6] = ie0_3_e_102_qs;
+ reg_rdata_next[7] = ie0_3_e_103_qs;
+ reg_rdata_next[8] = ie0_3_e_104_qs;
+ reg_rdata_next[9] = ie0_3_e_105_qs;
+ reg_rdata_next[10] = ie0_3_e_106_qs;
+ reg_rdata_next[11] = ie0_3_e_107_qs;
+ reg_rdata_next[12] = ie0_3_e_108_qs;
+ reg_rdata_next[13] = ie0_3_e_109_qs;
+ reg_rdata_next[14] = ie0_3_e_110_qs;
+ reg_rdata_next[15] = ie0_3_e_111_qs;
+ reg_rdata_next[16] = ie0_3_e_112_qs;
+ reg_rdata_next[17] = ie0_3_e_113_qs;
+ reg_rdata_next[18] = ie0_3_e_114_qs;
+ reg_rdata_next[19] = ie0_3_e_115_qs;
+ reg_rdata_next[20] = ie0_3_e_116_qs;
+ reg_rdata_next[21] = ie0_3_e_117_qs;
+ reg_rdata_next[22] = ie0_3_e_118_qs;
+ reg_rdata_next[23] = ie0_3_e_119_qs;
+ reg_rdata_next[24] = ie0_3_e_120_qs;
+ reg_rdata_next[25] = ie0_3_e_121_qs;
+ reg_rdata_next[26] = ie0_3_e_122_qs;
end
- addr_hit[111]: begin
+ addr_hit[135]: begin
reg_rdata_next[1:0] = threshold0_qs;
end
- addr_hit[112]: begin
+ addr_hit[136]: begin
reg_rdata_next[6:0] = cc0_qs;
end
- addr_hit[113]: begin
+ addr_hit[137]: begin
reg_rdata_next[0] = msip0_qs;
end
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 8084f89..af5679a 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -198,16 +198,12 @@
addr_range:
[
{
- base_addr: 0x18000000
- size_byte: 0x1000
- }
- {
base_addr: 0x40000000
size_byte: 0x421000
}
{
base_addr: 0x40500000
- size_byte: 0x20000
+ size_byte: 0x21000
}
]
}
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
index 11fe91a..22ed882 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
@@ -27,10 +27,10 @@
-node tb.dut tl_ram_main_o.a_address[31:29]
-node tb.dut tl_eflash_o.a_address[28:20]
-node tb.dut tl_eflash_o.a_address[31:30]
+-node tb.dut tl_peri_o.a_address[16:12]
-node tb.dut tl_peri_o.a_address[19:18]
-node tb.dut tl_peri_o.a_address[21:21]
--node tb.dut tl_peri_o.a_address[26:23]
--node tb.dut tl_peri_o.a_address[31:29]
+-node tb.dut tl_peri_o.a_address[31:23]
-node tb.dut tl_flash_ctrl_o.a_address[23:12]
-node tb.dut tl_flash_ctrl_o.a_address[29:25]
-node tb.dut tl_flash_ctrl_o.a_address[31:31]
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index 0d9823e..26d043b 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -20,9 +20,8 @@
'{32'h20000000, 32'h200fffff}
}},
'{"peri", '{
- '{32'h18000000, 32'h18000fff},
'{32'h40000000, 32'h40420fff},
- '{32'h40500000, 32'h4051ffff}
+ '{32'h40500000, 32'h40520fff}
}},
'{"flash_ctrl", '{
'{32'h41000000, 32'h41000fff}
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index 3348ad0..ff61dad 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,10 +10,9 @@
localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000;
localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000;
localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000;
- localparam logic [2:0][31:0] ADDR_SPACE_PERI = {
+ localparam logic [1:0][31:0] ADDR_SPACE_PERI = {
32'h 40500000,
- 32'h 40000000,
- 32'h 18000000
+ 32'h 40000000
};
localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 41000000;
localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 41110000;
@@ -34,10 +33,9 @@
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0001ffff;
localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 000fffff;
- localparam logic [2:0][31:0] ADDR_MASK_PERI = {
- 32'h 0001ffff,
- 32'h 00420fff,
- 32'h 00000fff
+ localparam logic [1:0][31:0] ADDR_MASK_PERI = {
+ 32'h 00020fff,
+ 32'h 00420fff
};
localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00000fff;
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index 5b5ec0b..d5a027d 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -541,11 +541,10 @@
dev_sel_s1n_27 = 5'd3;
end else if (
- ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_27_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
+ (tl_s1n_27_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
((tl_s1n_27_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_27_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
- ((tl_s1n_27_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
- (tl_s1n_27_us_h2d.a_address >= ADDR_SPACE_PERI[2]))
+ (tl_s1n_27_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
) begin
dev_sel_s1n_27 = 5'd4;
@@ -606,11 +605,10 @@
dev_sel_s1n_43 = 5'd2;
end else if (
- ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_43_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
+ (tl_s1n_43_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
((tl_s1n_43_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_43_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
- ((tl_s1n_43_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
- (tl_s1n_43_us_h2d.a_address >= ADDR_SPACE_PERI[2]))
+ (tl_s1n_43_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
) begin
dev_sel_s1n_43 = 5'd3;
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 185b61a..e8dceae 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -28,7 +28,10 @@
{
main:
[
- uart
+ uart0
+ uart1
+ uart2
+ uart3
gpio
spi_device
rv_timer
@@ -60,7 +63,7 @@
pipeline_byp: "true"
}
{
- name: uart
+ name: uart0
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -78,6 +81,60 @@
pipeline_byp: "true"
}
{
+ name: uart1
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40010000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: uart2
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40020000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: uart3
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40030000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
name: gpio
type: device
clock: clk_peri_i
@@ -213,7 +270,7 @@
addr_range:
[
{
- base_addr: 0x18000000
+ base_addr: 0x40520000
size_byte: 0x1000
}
]
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
index 6277bbb..1ada605 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -21,7 +21,25 @@
// device
{ struct: "tl"
type: "req_rsp"
- name: "tl_uart"
+ name: "tl_uart0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart1"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart2"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart3"
act: "req"
package: "tlul_pkg"
}
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index 674d511..ee1c37b 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -17,7 +17,10 @@
`CONNECT_TL_HOST_IF(main, dut, clk_peri_i, rst_n)
// Device TileLink interface connections
-`CONNECT_TL_DEVICE_IF(uart, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart0, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart1, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart2, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart3, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
index d026cf5..52057b9 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -16,8 +16,17 @@
-node tb.dut tl_*.d_opcode[2:1]
// [UNR] these device address bits are always 0
--node tb.dut tl_uart_o.a_address[29:12]
--node tb.dut tl_uart_o.a_address[31:31]
+-node tb.dut tl_uart0_o.a_address[29:12]
+-node tb.dut tl_uart0_o.a_address[31:31]
+-node tb.dut tl_uart1_o.a_address[15:12]
+-node tb.dut tl_uart1_o.a_address[29:17]
+-node tb.dut tl_uart1_o.a_address[31:31]
+-node tb.dut tl_uart2_o.a_address[16:12]
+-node tb.dut tl_uart2_o.a_address[29:18]
+-node tb.dut tl_uart2_o.a_address[31:31]
+-node tb.dut tl_uart3_o.a_address[15:12]
+-node tb.dut tl_uart3_o.a_address[29:18]
+-node tb.dut tl_uart3_o.a_address[31:31]
-node tb.dut tl_gpio_o.a_address[17:12]
-node tb.dut tl_gpio_o.a_address[29:19]
-node tb.dut tl_gpio_o.a_address[31:31]
@@ -43,8 +52,11 @@
-node tb.dut tl_clkmgr_o.a_address[21:18]
-node tb.dut tl_clkmgr_o.a_address[29:23]
-node tb.dut tl_clkmgr_o.a_address[31:31]
--node tb.dut tl_ram_ret_o.a_address[26:12]
--node tb.dut tl_ram_ret_o.a_address[31:29]
+-node tb.dut tl_ram_ret_o.a_address[16:12]
+-node tb.dut tl_ram_ret_o.a_address[19:18]
+-node tb.dut tl_ram_ret_o.a_address[21:21]
+-node tb.dut tl_ram_ret_o.a_address[29:23]
+-node tb.dut tl_ram_ret_o.a_address[31:31]
-node tb.dut tl_otp_ctrl_o.a_address[15:14]
-node tb.dut tl_otp_ctrl_o.a_address[19:18]
-node tb.dut tl_otp_ctrl_o.a_address[29:21]
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index e7d4141..f32a436 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -7,9 +7,18 @@
// List of Xbar device memory map
tl_device_t xbar_devices[$] = '{
- '{"uart", '{
+ '{"uart0", '{
'{32'h40000000, 32'h40000fff}
}},
+ '{"uart1", '{
+ '{32'h40010000, 32'h40010fff}
+ }},
+ '{"uart2", '{
+ '{32'h40020000, 32'h40020fff}
+ }},
+ '{"uart3", '{
+ '{32'h40030000, 32'h40030fff}
+ }},
'{"gpio", '{
'{32'h40040000, 32'h40040fff}
}},
@@ -32,7 +41,7 @@
'{32'h40420000, 32'h40420fff}
}},
'{"ram_ret", '{
- '{32'h18000000, 32'h18000fff}
+ '{32'h40520000, 32'h40520fff}
}},
'{"otp_ctrl", '{
'{32'h40130000, 32'h40133fff}
@@ -59,7 +68,10 @@
// List of Xbar hosts
tl_host_t xbar_hosts[$] = '{
'{"main", 0, '{
- "uart",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
"gpio",
"spi_device",
"rv_timer",
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index 64de93d..75fa8d9 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -14,11 +14,29 @@
);
// Device interfaces
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart0 (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_uart_o),
- .d2h (tl_uart_i)
+ .h2d (tl_uart0_o),
+ .d2h (tl_uart0_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart1 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart1_o),
+ .d2h (tl_uart1_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart2 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart2_o),
+ .d2h (tl_uart2_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart3 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart3_o),
+ .d2h (tl_uart3_i)
);
bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio (
.clk_i (clk_peri_i),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index 13462ee..c7610f0 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -6,7 +6,10 @@
package tl_peri_pkg;
- localparam logic [31:0] ADDR_SPACE_UART = 32'h 40000000;
+ localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 40000000;
+ localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 40010000;
+ localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 40020000;
+ localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 40030000;
localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000;
localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000;
localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000;
@@ -14,7 +17,7 @@
localparam logic [31:0] ADDR_SPACE_PWRMGR = 32'h 40400000;
localparam logic [31:0] ADDR_SPACE_RSTMGR = 32'h 40410000;
localparam logic [31:0] ADDR_SPACE_CLKMGR = 32'h 40420000;
- localparam logic [31:0] ADDR_SPACE_RAM_RET = 32'h 18000000;
+ localparam logic [31:0] ADDR_SPACE_RAM_RET = 32'h 40520000;
localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 40130000;
localparam logic [31:0] ADDR_SPACE_LC_CTRL = 32'h 40140000;
localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 40110000;
@@ -23,7 +26,10 @@
localparam logic [31:0] ADDR_SPACE_NMI_GEN = 32'h 40160000;
localparam logic [31:0] ADDR_SPACE_AST_WRAPPER = 32'h 40180000;
- localparam logic [31:0] ADDR_MASK_UART = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART0 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART2 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART3 = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff;
@@ -41,25 +47,28 @@
localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff;
localparam int N_HOST = 1;
- localparam int N_DEVICE = 16;
+ localparam int N_DEVICE = 19;
typedef enum int {
- TlUart = 0,
- TlGpio = 1,
- TlSpiDevice = 2,
- TlRvTimer = 3,
- TlUsbdev = 4,
- TlPwrmgr = 5,
- TlRstmgr = 6,
- TlClkmgr = 7,
- TlRamRet = 8,
- TlOtpCtrl = 9,
- TlLcCtrl = 10,
- TlSensorCtrl = 11,
- TlAlertHandler = 12,
- TlSramCtrlRet = 13,
- TlNmiGen = 14,
- TlAstWrapper = 15
+ TlUart0 = 0,
+ TlUart1 = 1,
+ TlUart2 = 2,
+ TlUart3 = 3,
+ TlGpio = 4,
+ TlSpiDevice = 5,
+ TlRvTimer = 6,
+ TlUsbdev = 7,
+ TlPwrmgr = 8,
+ TlRstmgr = 9,
+ TlClkmgr = 10,
+ TlRamRet = 11,
+ TlOtpCtrl = 12,
+ TlLcCtrl = 13,
+ TlSensorCtrl = 14,
+ TlAlertHandler = 15,
+ TlSramCtrlRet = 16,
+ TlNmiGen = 17,
+ TlAstWrapper = 18
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index 64fff82..379fc84 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,8 +7,11 @@
//
// Interconnect
// main
-// -> s1n_17
-// -> uart
+// -> s1n_20
+// -> uart0
+// -> uart1
+// -> uart2
+// -> uart3
// -> gpio
// -> spi_device
// -> rv_timer
@@ -34,8 +37,14 @@
output tlul_pkg::tl_d2h_t tl_main_o,
// Device interfaces
- output tlul_pkg::tl_h2d_t tl_uart_o,
- input tlul_pkg::tl_d2h_t tl_uart_i,
+ output tlul_pkg::tl_h2d_t tl_uart0_o,
+ input tlul_pkg::tl_d2h_t tl_uart0_i,
+ output tlul_pkg::tl_h2d_t tl_uart1_o,
+ input tlul_pkg::tl_d2h_t tl_uart1_i,
+ output tlul_pkg::tl_h2d_t tl_uart2_o,
+ input tlul_pkg::tl_d2h_t tl_uart2_i,
+ output tlul_pkg::tl_h2d_t tl_uart3_o,
+ input tlul_pkg::tl_d2h_t tl_uart3_i,
output tlul_pkg::tl_h2d_t tl_gpio_o,
input tlul_pkg::tl_d2h_t tl_gpio_i,
output tlul_pkg::tl_h2d_t tl_spi_device_o,
@@ -78,119 +87,137 @@
logic unused_scanmode;
assign unused_scanmode = scanmode_i;
- tl_h2d_t tl_s1n_17_us_h2d ;
- tl_d2h_t tl_s1n_17_us_d2h ;
+ tl_h2d_t tl_s1n_20_us_h2d ;
+ tl_d2h_t tl_s1n_20_us_d2h ;
- tl_h2d_t tl_s1n_17_ds_h2d [16];
- tl_d2h_t tl_s1n_17_ds_d2h [16];
+ tl_h2d_t tl_s1n_20_ds_h2d [19];
+ tl_d2h_t tl_s1n_20_ds_d2h [19];
// Create steering signal
- logic [4:0] dev_sel_s1n_17;
+ logic [4:0] dev_sel_s1n_20;
- assign tl_uart_o = tl_s1n_17_ds_h2d[0];
- assign tl_s1n_17_ds_d2h[0] = tl_uart_i;
+ assign tl_uart0_o = tl_s1n_20_ds_h2d[0];
+ assign tl_s1n_20_ds_d2h[0] = tl_uart0_i;
- assign tl_gpio_o = tl_s1n_17_ds_h2d[1];
- assign tl_s1n_17_ds_d2h[1] = tl_gpio_i;
+ assign tl_uart1_o = tl_s1n_20_ds_h2d[1];
+ assign tl_s1n_20_ds_d2h[1] = tl_uart1_i;
- assign tl_spi_device_o = tl_s1n_17_ds_h2d[2];
- assign tl_s1n_17_ds_d2h[2] = tl_spi_device_i;
+ assign tl_uart2_o = tl_s1n_20_ds_h2d[2];
+ assign tl_s1n_20_ds_d2h[2] = tl_uart2_i;
- assign tl_rv_timer_o = tl_s1n_17_ds_h2d[3];
- assign tl_s1n_17_ds_d2h[3] = tl_rv_timer_i;
+ assign tl_uart3_o = tl_s1n_20_ds_h2d[3];
+ assign tl_s1n_20_ds_d2h[3] = tl_uart3_i;
- assign tl_usbdev_o = tl_s1n_17_ds_h2d[4];
- assign tl_s1n_17_ds_d2h[4] = tl_usbdev_i;
+ assign tl_gpio_o = tl_s1n_20_ds_h2d[4];
+ assign tl_s1n_20_ds_d2h[4] = tl_gpio_i;
- assign tl_pwrmgr_o = tl_s1n_17_ds_h2d[5];
- assign tl_s1n_17_ds_d2h[5] = tl_pwrmgr_i;
+ assign tl_spi_device_o = tl_s1n_20_ds_h2d[5];
+ assign tl_s1n_20_ds_d2h[5] = tl_spi_device_i;
- assign tl_rstmgr_o = tl_s1n_17_ds_h2d[6];
- assign tl_s1n_17_ds_d2h[6] = tl_rstmgr_i;
+ assign tl_rv_timer_o = tl_s1n_20_ds_h2d[6];
+ assign tl_s1n_20_ds_d2h[6] = tl_rv_timer_i;
- assign tl_clkmgr_o = tl_s1n_17_ds_h2d[7];
- assign tl_s1n_17_ds_d2h[7] = tl_clkmgr_i;
+ assign tl_usbdev_o = tl_s1n_20_ds_h2d[7];
+ assign tl_s1n_20_ds_d2h[7] = tl_usbdev_i;
- assign tl_ram_ret_o = tl_s1n_17_ds_h2d[8];
- assign tl_s1n_17_ds_d2h[8] = tl_ram_ret_i;
+ assign tl_pwrmgr_o = tl_s1n_20_ds_h2d[8];
+ assign tl_s1n_20_ds_d2h[8] = tl_pwrmgr_i;
- assign tl_otp_ctrl_o = tl_s1n_17_ds_h2d[9];
- assign tl_s1n_17_ds_d2h[9] = tl_otp_ctrl_i;
+ assign tl_rstmgr_o = tl_s1n_20_ds_h2d[9];
+ assign tl_s1n_20_ds_d2h[9] = tl_rstmgr_i;
- assign tl_lc_ctrl_o = tl_s1n_17_ds_h2d[10];
- assign tl_s1n_17_ds_d2h[10] = tl_lc_ctrl_i;
+ assign tl_clkmgr_o = tl_s1n_20_ds_h2d[10];
+ assign tl_s1n_20_ds_d2h[10] = tl_clkmgr_i;
- assign tl_sensor_ctrl_o = tl_s1n_17_ds_h2d[11];
- assign tl_s1n_17_ds_d2h[11] = tl_sensor_ctrl_i;
+ assign tl_ram_ret_o = tl_s1n_20_ds_h2d[11];
+ assign tl_s1n_20_ds_d2h[11] = tl_ram_ret_i;
- assign tl_alert_handler_o = tl_s1n_17_ds_h2d[12];
- assign tl_s1n_17_ds_d2h[12] = tl_alert_handler_i;
+ assign tl_otp_ctrl_o = tl_s1n_20_ds_h2d[12];
+ assign tl_s1n_20_ds_d2h[12] = tl_otp_ctrl_i;
- assign tl_nmi_gen_o = tl_s1n_17_ds_h2d[13];
- assign tl_s1n_17_ds_d2h[13] = tl_nmi_gen_i;
+ assign tl_lc_ctrl_o = tl_s1n_20_ds_h2d[13];
+ assign tl_s1n_20_ds_d2h[13] = tl_lc_ctrl_i;
- assign tl_ast_wrapper_o = tl_s1n_17_ds_h2d[14];
- assign tl_s1n_17_ds_d2h[14] = tl_ast_wrapper_i;
+ assign tl_sensor_ctrl_o = tl_s1n_20_ds_h2d[14];
+ assign tl_s1n_20_ds_d2h[14] = tl_sensor_ctrl_i;
- assign tl_sram_ctrl_ret_o = tl_s1n_17_ds_h2d[15];
- assign tl_s1n_17_ds_d2h[15] = tl_sram_ctrl_ret_i;
+ assign tl_alert_handler_o = tl_s1n_20_ds_h2d[15];
+ assign tl_s1n_20_ds_d2h[15] = tl_alert_handler_i;
- assign tl_s1n_17_us_h2d = tl_main_i;
- assign tl_main_o = tl_s1n_17_us_d2h;
+ assign tl_nmi_gen_o = tl_s1n_20_ds_h2d[16];
+ assign tl_s1n_20_ds_d2h[16] = tl_nmi_gen_i;
+
+ assign tl_ast_wrapper_o = tl_s1n_20_ds_h2d[17];
+ assign tl_s1n_20_ds_d2h[17] = tl_ast_wrapper_i;
+
+ assign tl_sram_ctrl_ret_o = tl_s1n_20_ds_h2d[18];
+ assign tl_s1n_20_ds_d2h[18] = tl_sram_ctrl_ret_i;
+
+ assign tl_s1n_20_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_20_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_17 = 5'd16;
- if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
- dev_sel_s1n_17 = 5'd0;
+ dev_sel_s1n_20 = 5'd19;
+ if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
+ dev_sel_s1n_20 = 5'd0;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_17 = 5'd1;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
+ dev_sel_s1n_20 = 5'd1;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_17 = 5'd2;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
+ dev_sel_s1n_20 = 5'd2;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_17 = 5'd3;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
+ dev_sel_s1n_20 = 5'd3;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
- dev_sel_s1n_17 = 5'd4;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_20 = 5'd4;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin
- dev_sel_s1n_17 = 5'd5;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_20 = 5'd5;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin
- dev_sel_s1n_17 = 5'd6;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_20 = 5'd6;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin
- dev_sel_s1n_17 = 5'd7;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+ dev_sel_s1n_20 = 5'd7;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin
- dev_sel_s1n_17 = 5'd8;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin
+ dev_sel_s1n_20 = 5'd8;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
- dev_sel_s1n_17 = 5'd9;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin
+ dev_sel_s1n_20 = 5'd9;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
- dev_sel_s1n_17 = 5'd10;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin
+ dev_sel_s1n_20 = 5'd10;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
- dev_sel_s1n_17 = 5'd11;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin
+ dev_sel_s1n_20 = 5'd11;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
- dev_sel_s1n_17 = 5'd12;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
+ dev_sel_s1n_20 = 5'd12;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
- dev_sel_s1n_17 = 5'd13;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
+ dev_sel_s1n_20 = 5'd13;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
- dev_sel_s1n_17 = 5'd14;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
+ dev_sel_s1n_20 = 5'd14;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET)) == ADDR_SPACE_SRAM_CTRL_RET) begin
- dev_sel_s1n_17 = 5'd15;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+ dev_sel_s1n_20 = 5'd15;
+
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+ dev_sel_s1n_20 = 5'd16;
+
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
+ dev_sel_s1n_20 = 5'd17;
+
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET)) == ADDR_SPACE_SRAM_CTRL_RET) begin
+ dev_sel_s1n_20 = 5'd18;
end
end
@@ -199,17 +226,17 @@
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth (64'h0),
- .DRspDepth (64'h0),
- .N (16)
- ) u_s1n_17 (
+ .DReqDepth (76'h0),
+ .DRspDepth (76'h0),
+ .N (19)
+ ) u_s1n_20 (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .tl_h_i (tl_s1n_17_us_h2d),
- .tl_h_o (tl_s1n_17_us_d2h),
- .tl_d_o (tl_s1n_17_ds_h2d),
- .tl_d_i (tl_s1n_17_ds_d2h),
- .dev_select_i (dev_sel_s1n_17)
+ .tl_h_i (tl_s1n_20_us_h2d),
+ .tl_h_o (tl_s1n_20_us_d2h),
+ .tl_d_o (tl_s1n_20_ds_h2d),
+ .tl_d_i (tl_s1n_20_ds_d2h),
+ .dev_select_i (dev_sel_s1n_20)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index f16c423..f50f51a 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -100,16 +100,28 @@
import top_earlgrey_rnd_cnst_pkg::*;
// Signals
- logic [31:0] mio_p2d;
- logic [31:0] mio_d2p;
- logic [31:0] mio_d2p_en;
+ logic [34:0] mio_p2d;
+ logic [34:0] mio_d2p;
+ logic [34:0] mio_d2p_en;
logic [14:0] dio_p2d;
logic [14:0] dio_d2p;
logic [14:0] dio_d2p_en;
- // uart
- logic cio_uart_rx_p2d;
- logic cio_uart_tx_d2p;
- logic cio_uart_tx_en_d2p;
+ // uart0
+ logic cio_uart0_rx_p2d;
+ logic cio_uart0_tx_d2p;
+ logic cio_uart0_tx_en_d2p;
+ // uart1
+ logic cio_uart1_rx_p2d;
+ logic cio_uart1_tx_d2p;
+ logic cio_uart1_tx_en_d2p;
+ // uart2
+ logic cio_uart2_rx_p2d;
+ logic cio_uart2_tx_d2p;
+ logic cio_uart2_tx_en_d2p;
+ // uart3
+ logic cio_uart3_rx_p2d;
+ logic cio_uart3_tx_d2p;
+ logic cio_uart3_tx_en_d2p;
// gpio
logic [31:0] cio_gpio_gpio_p2d;
logic [31:0] cio_gpio_gpio_d2p;
@@ -167,16 +179,40 @@
// otbn
- logic [98:0] intr_vector;
+ logic [122:0] intr_vector;
// Interrupt source list
- logic intr_uart_tx_watermark;
- logic intr_uart_rx_watermark;
- logic intr_uart_tx_empty;
- logic intr_uart_rx_overflow;
- logic intr_uart_rx_frame_err;
- logic intr_uart_rx_break_err;
- logic intr_uart_rx_timeout;
- logic intr_uart_rx_parity_err;
+ logic intr_uart0_tx_watermark;
+ logic intr_uart0_rx_watermark;
+ logic intr_uart0_tx_empty;
+ logic intr_uart0_rx_overflow;
+ logic intr_uart0_rx_frame_err;
+ logic intr_uart0_rx_break_err;
+ logic intr_uart0_rx_timeout;
+ logic intr_uart0_rx_parity_err;
+ logic intr_uart1_tx_watermark;
+ logic intr_uart1_rx_watermark;
+ logic intr_uart1_tx_empty;
+ logic intr_uart1_rx_overflow;
+ logic intr_uart1_rx_frame_err;
+ logic intr_uart1_rx_break_err;
+ logic intr_uart1_rx_timeout;
+ logic intr_uart1_rx_parity_err;
+ logic intr_uart2_tx_watermark;
+ logic intr_uart2_rx_watermark;
+ logic intr_uart2_tx_empty;
+ logic intr_uart2_rx_overflow;
+ logic intr_uart2_rx_frame_err;
+ logic intr_uart2_rx_break_err;
+ logic intr_uart2_rx_timeout;
+ logic intr_uart2_rx_parity_err;
+ logic intr_uart3_tx_watermark;
+ logic intr_uart3_rx_watermark;
+ logic intr_uart3_tx_empty;
+ logic intr_uart3_rx_overflow;
+ logic intr_uart3_rx_frame_err;
+ logic intr_uart3_rx_break_err;
+ logic intr_uart3_rx_timeout;
+ logic intr_uart3_rx_parity_err;
logic [31:0] intr_gpio_gpio;
logic intr_spi_device_rxf;
logic intr_spi_device_rxlvl;
@@ -349,8 +385,14 @@
tlul_pkg::tl_d2h_t keymgr_tl_rsp;
tlul_pkg::tl_h2d_t sram_ctrl_main_tl_req;
tlul_pkg::tl_d2h_t sram_ctrl_main_tl_rsp;
- tlul_pkg::tl_h2d_t uart_tl_req;
- tlul_pkg::tl_d2h_t uart_tl_rsp;
+ tlul_pkg::tl_h2d_t uart0_tl_req;
+ tlul_pkg::tl_d2h_t uart0_tl_rsp;
+ tlul_pkg::tl_h2d_t uart1_tl_req;
+ tlul_pkg::tl_d2h_t uart1_tl_rsp;
+ tlul_pkg::tl_h2d_t uart2_tl_req;
+ tlul_pkg::tl_d2h_t uart2_tl_rsp;
+ tlul_pkg::tl_h2d_t uart3_tl_req;
+ tlul_pkg::tl_d2h_t uart3_tl_rsp;
tlul_pkg::tl_h2d_t gpio_tl_req;
tlul_pkg::tl_d2h_t gpio_tl_rsp;
tlul_pkg::tl_h2d_t spi_device_tl_req;
@@ -738,28 +780,106 @@
- uart u_uart (
+ uart u_uart0 (
// Input
- .cio_rx_i (cio_uart_rx_p2d),
+ .cio_rx_i (cio_uart0_rx_p2d),
// Output
- .cio_tx_o (cio_uart_tx_d2p),
- .cio_tx_en_o (cio_uart_tx_en_d2p),
+ .cio_tx_o (cio_uart0_tx_d2p),
+ .cio_tx_en_o (cio_uart0_tx_en_d2p),
// Interrupt
- .intr_tx_watermark_o (intr_uart_tx_watermark),
- .intr_rx_watermark_o (intr_uart_rx_watermark),
- .intr_tx_empty_o (intr_uart_tx_empty),
- .intr_rx_overflow_o (intr_uart_rx_overflow),
- .intr_rx_frame_err_o (intr_uart_rx_frame_err),
- .intr_rx_break_err_o (intr_uart_rx_break_err),
- .intr_rx_timeout_o (intr_uart_rx_timeout),
- .intr_rx_parity_err_o (intr_uart_rx_parity_err),
+ .intr_tx_watermark_o (intr_uart0_tx_watermark),
+ .intr_rx_watermark_o (intr_uart0_rx_watermark),
+ .intr_tx_empty_o (intr_uart0_tx_empty),
+ .intr_rx_overflow_o (intr_uart0_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart0_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart0_rx_break_err),
+ .intr_rx_timeout_o (intr_uart0_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart0_rx_parity_err),
// Inter-module signals
- .tl_i(uart_tl_req),
- .tl_o(uart_tl_rsp),
+ .tl_i(uart0_tl_req),
+ .tl_o(uart0_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ uart u_uart1 (
+
+ // Input
+ .cio_rx_i (cio_uart1_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart1_tx_d2p),
+ .cio_tx_en_o (cio_uart1_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart1_tx_watermark),
+ .intr_rx_watermark_o (intr_uart1_rx_watermark),
+ .intr_tx_empty_o (intr_uart1_tx_empty),
+ .intr_rx_overflow_o (intr_uart1_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart1_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart1_rx_break_err),
+ .intr_rx_timeout_o (intr_uart1_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart1_rx_parity_err),
+
+ // Inter-module signals
+ .tl_i(uart1_tl_req),
+ .tl_o(uart1_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ uart u_uart2 (
+
+ // Input
+ .cio_rx_i (cio_uart2_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart2_tx_d2p),
+ .cio_tx_en_o (cio_uart2_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart2_tx_watermark),
+ .intr_rx_watermark_o (intr_uart2_rx_watermark),
+ .intr_tx_empty_o (intr_uart2_tx_empty),
+ .intr_rx_overflow_o (intr_uart2_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart2_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart2_rx_break_err),
+ .intr_rx_timeout_o (intr_uart2_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart2_rx_parity_err),
+
+ // Inter-module signals
+ .tl_i(uart2_tl_req),
+ .tl_o(uart2_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ uart u_uart3 (
+
+ // Input
+ .cio_rx_i (cio_uart3_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart3_tx_d2p),
+ .cio_tx_en_o (cio_uart3_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart3_tx_watermark),
+ .intr_rx_watermark_o (intr_uart3_rx_watermark),
+ .intr_tx_empty_o (intr_uart3_tx_empty),
+ .intr_rx_overflow_o (intr_uart3_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart3_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart3_rx_break_err),
+ .intr_rx_timeout_o (intr_uart3_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart3_rx_parity_err),
+
+ // Inter-module signals
+ .tl_i(uart3_tl_req),
+ .tl_o(uart3_tl_rsp),
.clk_i (clkmgr_clocks.clk_io_div4_secure),
.rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
@@ -1539,15 +1659,39 @@
intr_spi_device_txlvl,
intr_spi_device_rxlvl,
intr_spi_device_rxf,
- intr_uart_rx_parity_err,
- intr_uart_rx_timeout,
- intr_uart_rx_break_err,
- intr_uart_rx_frame_err,
- intr_uart_rx_overflow,
- intr_uart_tx_empty,
- intr_uart_rx_watermark,
- intr_uart_tx_watermark,
intr_gpio_gpio,
+ intr_uart3_rx_parity_err,
+ intr_uart3_rx_timeout,
+ intr_uart3_rx_break_err,
+ intr_uart3_rx_frame_err,
+ intr_uart3_rx_overflow,
+ intr_uart3_tx_empty,
+ intr_uart3_rx_watermark,
+ intr_uart3_tx_watermark,
+ intr_uart2_rx_parity_err,
+ intr_uart2_rx_timeout,
+ intr_uart2_rx_break_err,
+ intr_uart2_rx_frame_err,
+ intr_uart2_rx_overflow,
+ intr_uart2_tx_empty,
+ intr_uart2_rx_watermark,
+ intr_uart2_tx_watermark,
+ intr_uart1_rx_parity_err,
+ intr_uart1_rx_timeout,
+ intr_uart1_rx_break_err,
+ intr_uart1_rx_frame_err,
+ intr_uart1_rx_overflow,
+ intr_uart1_tx_empty,
+ intr_uart1_rx_watermark,
+ intr_uart1_tx_watermark,
+ intr_uart0_rx_parity_err,
+ intr_uart0_rx_timeout,
+ intr_uart0_rx_break_err,
+ intr_uart0_rx_frame_err,
+ intr_uart0_rx_overflow,
+ intr_uart0_tx_empty,
+ intr_uart0_rx_watermark,
+ intr_uart0_tx_watermark,
1'b 0 // For ID 0.
};
@@ -1657,9 +1801,21 @@
.tl_main_i(main_tl_peri_req),
.tl_main_o(main_tl_peri_rsp),
- // port: tl_uart
- .tl_uart_o(uart_tl_req),
- .tl_uart_i(uart_tl_rsp),
+ // port: tl_uart0
+ .tl_uart0_o(uart0_tl_req),
+ .tl_uart0_i(uart0_tl_rsp),
+
+ // port: tl_uart1
+ .tl_uart1_o(uart1_tl_req),
+ .tl_uart1_i(uart1_tl_rsp),
+
+ // port: tl_uart2
+ .tl_uart2_o(uart2_tl_req),
+ .tl_uart2_i(uart2_tl_rsp),
+
+ // port: tl_uart3
+ .tl_uart3_o(uart3_tl_req),
+ .tl_uart3_i(uart3_tl_rsp),
// port: tl_gpio
.tl_gpio_o(gpio_tl_req),
@@ -1727,12 +1883,21 @@
// Pinmux connections
assign mio_d2p = {
+ cio_uart3_tx_d2p,
+ cio_uart2_tx_d2p,
+ cio_uart1_tx_d2p,
cio_gpio_gpio_d2p
};
assign mio_d2p_en = {
+ cio_uart3_tx_en_d2p,
+ cio_uart2_tx_en_d2p,
+ cio_uart1_tx_en_d2p,
cio_gpio_gpio_en_d2p
};
assign {
+ cio_uart3_rx_p2d,
+ cio_uart2_rx_p2d,
+ cio_uart1_rx_p2d,
cio_gpio_gpio_p2d
} = mio_p2d;
@@ -1743,8 +1908,8 @@
1'b0, // DIO13: cio_spi_device_csb
1'b0, // DIO12: cio_spi_device_sdi
cio_spi_device_sdo_d2p, // DIO11
- 1'b0, // DIO10: cio_uart_rx
- cio_uart_tx_d2p, // DIO9
+ 1'b0, // DIO10: cio_uart0_rx
+ cio_uart0_tx_d2p, // DIO9
1'b0, // DIO8: cio_usbdev_sense
cio_usbdev_se0_d2p, // DIO7
cio_usbdev_dp_pullup_d2p, // DIO6
@@ -1761,8 +1926,8 @@
1'b0, // DIO13: cio_spi_device_csb
1'b0, // DIO12: cio_spi_device_sdi
cio_spi_device_sdo_en_d2p, // DIO11
- 1'b0, // DIO10: cio_uart_rx
- cio_uart_tx_en_d2p, // DIO9
+ 1'b0, // DIO10: cio_uart0_rx
+ cio_uart0_tx_en_d2p, // DIO9
1'b0, // DIO8: cio_usbdev_sense
cio_usbdev_se0_en_d2p, // DIO7
cio_usbdev_dp_pullup_en_d2p, // DIO6
@@ -1779,8 +1944,8 @@
assign cio_spi_device_csb_p2d = dio_p2d[13]; // DIO13
assign cio_spi_device_sdi_p2d = dio_p2d[12]; // DIO12
// DIO11: cio_spi_device_sdo
- assign cio_uart_rx_p2d = dio_p2d[10]; // DIO10
- // DIO9: cio_uart_tx
+ assign cio_uart0_rx_p2d = dio_p2d[10]; // DIO10
+ // DIO9: cio_uart0_tx
assign cio_usbdev_sense_p2d = dio_p2d[8]; // DIO8
// DIO7: cio_usbdev_se0
// DIO6: cio_usbdev_dp_pullup
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 020902a..b7e8956 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -12,14 +12,44 @@
package top_earlgrey_pkg;
/**
- * Peripheral base address for uart in top earlgrey.
+ * Peripheral base address for uart0 in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_UART_BASE_ADDR = 32'h40000000;
+ parameter int unsigned TOP_EARLGREY_UART0_BASE_ADDR = 32'h40000000;
/**
- * Peripheral size in bytes for uart in top earlgrey.
+ * Peripheral size in bytes for uart0 in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_UART_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_UART0_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for uart1 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_UART1_BASE_ADDR = 32'h40010000;
+
+ /**
+ * Peripheral size in bytes for uart1 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_UART1_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for uart2 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_UART2_BASE_ADDR = 32'h40020000;
+
+ /**
+ * Peripheral size in bytes for uart2 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_UART2_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for uart3 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_UART3_BASE_ADDR = 32'h40030000;
+
+ /**
+ * Peripheral size in bytes for uart3 in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_UART3_SIZE_BYTES = 32'h1000;
/**
* Peripheral base address for gpio in top earlgrey.
@@ -314,7 +344,7 @@
/**
* Memory base address for ram_ret in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_RAM_RET_BASE_ADDR = 32'h18000000;
+ parameter int unsigned TOP_EARLGREY_RAM_RET_BASE_ADDR = 32'h40520000;
/**
* Memory size for ram_ret in top earlgrey.
@@ -342,8 +372,8 @@
TopEarlgreyDioPinUsbdevDpPullup = 6,
TopEarlgreyDioPinUsbdevSe0 = 7,
TopEarlgreyDioPinUsbdevSense = 8,
- TopEarlgreyDioPinUartTx = 9,
- TopEarlgreyDioPinUartRx = 10,
+ TopEarlgreyDioPinUart0Tx = 9,
+ TopEarlgreyDioPinUart0Rx = 10,
TopEarlgreyDioPinSpiDeviceSdo = 11,
TopEarlgreyDioPinSpiDeviceSdi = 12,
TopEarlgreyDioPinSpiDeviceCsb = 13,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 2434364..6593e50 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -11,8 +11,40 @@
* `top_earlgrey_plic_peripheral_t`.
*/
const top_earlgrey_plic_peripheral_t
- top_earlgrey_plic_interrupt_for_peripheral[99] = {
+ top_earlgrey_plic_interrupt_for_peripheral[123] = {
[kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown,
+ [kTopEarlgreyPlicIrqIdUart0TxWatermark] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0RxWatermark] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0TxEmpty] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0RxOverflow] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0RxFrameErr] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0RxBreakErr] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0RxTimeout] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart0RxParityErr] = kTopEarlgreyPlicPeripheralUart0,
+ [kTopEarlgreyPlicIrqIdUart1TxWatermark] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1RxWatermark] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1TxEmpty] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1RxOverflow] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1RxFrameErr] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1RxBreakErr] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1RxTimeout] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart1RxParityErr] = kTopEarlgreyPlicPeripheralUart1,
+ [kTopEarlgreyPlicIrqIdUart2TxWatermark] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2RxWatermark] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2TxEmpty] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2RxOverflow] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2RxFrameErr] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2RxBreakErr] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2RxTimeout] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart2RxParityErr] = kTopEarlgreyPlicPeripheralUart2,
+ [kTopEarlgreyPlicIrqIdUart3TxWatermark] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3RxWatermark] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3TxEmpty] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3RxOverflow] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3RxFrameErr] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3RxBreakErr] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3RxTimeout] = kTopEarlgreyPlicPeripheralUart3,
+ [kTopEarlgreyPlicIrqIdUart3RxParityErr] = kTopEarlgreyPlicPeripheralUart3,
[kTopEarlgreyPlicIrqIdGpioGpio0] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio1] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio2] = kTopEarlgreyPlicPeripheralGpio,
@@ -45,14 +77,6 @@
[kTopEarlgreyPlicIrqIdGpioGpio29] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio30] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio31] = kTopEarlgreyPlicPeripheralGpio,
- [kTopEarlgreyPlicIrqIdUartTxWatermark] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartRxWatermark] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartTxEmpty] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartRxOverflow] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartRxFrameErr] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartRxBreakErr] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartRxTimeout] = kTopEarlgreyPlicPeripheralUart,
- [kTopEarlgreyPlicIrqIdUartRxParityErr] = kTopEarlgreyPlicPeripheralUart,
[kTopEarlgreyPlicIrqIdSpiDeviceRxf] = kTopEarlgreyPlicPeripheralSpiDevice,
[kTopEarlgreyPlicIrqIdSpiDeviceRxlvl] = kTopEarlgreyPlicPeripheralSpiDevice,
[kTopEarlgreyPlicIrqIdSpiDeviceTxlvl] = kTopEarlgreyPlicPeripheralSpiDevice,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index f2dd406..a8a05b2 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -26,22 +26,76 @@
#endif
/**
- * Peripheral base address for uart in top earlgrey.
+ * Peripheral base address for uart0 in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_UART_BASE_ADDR 0x40000000u
+#define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000u
/**
- * Peripheral size for uart in top earlgrey.
+ * Peripheral size for uart0 in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_UART_BASE_ADDR and
- * `TOP_EARLGREY_UART_BASE_ADDR + TOP_EARLGREY_UART_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_UART0_BASE_ADDR and
+ * `TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_UART_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_UART0_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for uart1 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000u
+
+/**
+ * Peripheral size for uart1 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_UART1_BASE_ADDR and
+ * `TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_UART1_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for uart2 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000u
+
+/**
+ * Peripheral size for uart2 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_UART2_BASE_ADDR and
+ * `TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_UART2_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for uart3 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000u
+
+/**
+ * Peripheral size for uart3 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_UART3_BASE_ADDR and
+ * `TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_UART3_SIZE_BYTES 0x1000u
/**
* Peripheral base address for gpio in top earlgrey.
@@ -553,7 +607,7 @@
/**
* Memory base address for ram_ret in top earlgrey.
*/
-#define TOP_EARLGREY_RAM_RET_BASE_ADDR 0x18000000u
+#define TOP_EARLGREY_RAM_RET_BASE_ADDR 0x40520000u
/**
* Memory size for ram_ret in top earlgrey.
@@ -579,24 +633,27 @@
*/
typedef enum top_earlgrey_plic_peripheral {
kTopEarlgreyPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
- kTopEarlgreyPlicPeripheralGpio = 1, /**< gpio */
- kTopEarlgreyPlicPeripheralUart = 2, /**< uart */
- kTopEarlgreyPlicPeripheralSpiDevice = 3, /**< spi_device */
- kTopEarlgreyPlicPeripheralFlashCtrl = 4, /**< flash_ctrl */
- kTopEarlgreyPlicPeripheralHmac = 5, /**< hmac */
- kTopEarlgreyPlicPeripheralAlertHandler = 6, /**< alert_handler */
- kTopEarlgreyPlicPeripheralNmiGen = 7, /**< nmi_gen */
- kTopEarlgreyPlicPeripheralUsbdev = 8, /**< usbdev */
- kTopEarlgreyPlicPeripheralPwrmgr = 9, /**< pwrmgr */
- kTopEarlgreyPlicPeripheralOtbn = 10, /**< otbn */
- kTopEarlgreyPlicPeripheralKeymgr = 11, /**< keymgr */
- kTopEarlgreyPlicPeripheralKmac = 12, /**< kmac */
- kTopEarlgreyPlicPeripheralOtpCtrl = 13, /**< otp_ctrl */
- kTopEarlgreyPlicPeripheralCsrng = 14, /**< csrng */
- kTopEarlgreyPlicPeripheralEdn0 = 15, /**< edn0 */
- kTopEarlgreyPlicPeripheralEdn1 = 16, /**< edn1 */
- kTopEarlgreyPlicPeripheralEntropySrc = 17, /**< entropy_src */
- kTopEarlgreyPlicPeripheralLast = 17, /**< \internal Final PLIC peripheral */
+ kTopEarlgreyPlicPeripheralUart0 = 1, /**< uart0 */
+ kTopEarlgreyPlicPeripheralUart1 = 2, /**< uart1 */
+ kTopEarlgreyPlicPeripheralUart2 = 3, /**< uart2 */
+ kTopEarlgreyPlicPeripheralUart3 = 4, /**< uart3 */
+ kTopEarlgreyPlicPeripheralGpio = 5, /**< gpio */
+ kTopEarlgreyPlicPeripheralSpiDevice = 6, /**< spi_device */
+ kTopEarlgreyPlicPeripheralFlashCtrl = 7, /**< flash_ctrl */
+ kTopEarlgreyPlicPeripheralHmac = 8, /**< hmac */
+ kTopEarlgreyPlicPeripheralAlertHandler = 9, /**< alert_handler */
+ kTopEarlgreyPlicPeripheralNmiGen = 10, /**< nmi_gen */
+ kTopEarlgreyPlicPeripheralUsbdev = 11, /**< usbdev */
+ kTopEarlgreyPlicPeripheralPwrmgr = 12, /**< pwrmgr */
+ kTopEarlgreyPlicPeripheralOtbn = 13, /**< otbn */
+ kTopEarlgreyPlicPeripheralKeymgr = 14, /**< keymgr */
+ kTopEarlgreyPlicPeripheralKmac = 15, /**< kmac */
+ kTopEarlgreyPlicPeripheralOtpCtrl = 16, /**< otp_ctrl */
+ kTopEarlgreyPlicPeripheralCsrng = 17, /**< csrng */
+ kTopEarlgreyPlicPeripheralEdn0 = 18, /**< edn0 */
+ kTopEarlgreyPlicPeripheralEdn1 = 19, /**< edn1 */
+ kTopEarlgreyPlicPeripheralEntropySrc = 20, /**< entropy_src */
+ kTopEarlgreyPlicPeripheralLast = 20, /**< \internal Final PLIC peripheral */
} top_earlgrey_plic_peripheral_t;
/**
@@ -607,105 +664,129 @@
*/
typedef enum top_earlgrey_plic_irq_id {
kTopEarlgreyPlicIrqIdNone = 0, /**< No Interrupt */
- kTopEarlgreyPlicIrqIdGpioGpio0 = 1, /**< gpio_gpio 0 */
- kTopEarlgreyPlicIrqIdGpioGpio1 = 2, /**< gpio_gpio 1 */
- kTopEarlgreyPlicIrqIdGpioGpio2 = 3, /**< gpio_gpio 2 */
- kTopEarlgreyPlicIrqIdGpioGpio3 = 4, /**< gpio_gpio 3 */
- kTopEarlgreyPlicIrqIdGpioGpio4 = 5, /**< gpio_gpio 4 */
- kTopEarlgreyPlicIrqIdGpioGpio5 = 6, /**< gpio_gpio 5 */
- kTopEarlgreyPlicIrqIdGpioGpio6 = 7, /**< gpio_gpio 6 */
- kTopEarlgreyPlicIrqIdGpioGpio7 = 8, /**< gpio_gpio 7 */
- kTopEarlgreyPlicIrqIdGpioGpio8 = 9, /**< gpio_gpio 8 */
- kTopEarlgreyPlicIrqIdGpioGpio9 = 10, /**< gpio_gpio 9 */
- kTopEarlgreyPlicIrqIdGpioGpio10 = 11, /**< gpio_gpio 10 */
- kTopEarlgreyPlicIrqIdGpioGpio11 = 12, /**< gpio_gpio 11 */
- kTopEarlgreyPlicIrqIdGpioGpio12 = 13, /**< gpio_gpio 12 */
- kTopEarlgreyPlicIrqIdGpioGpio13 = 14, /**< gpio_gpio 13 */
- kTopEarlgreyPlicIrqIdGpioGpio14 = 15, /**< gpio_gpio 14 */
- kTopEarlgreyPlicIrqIdGpioGpio15 = 16, /**< gpio_gpio 15 */
- kTopEarlgreyPlicIrqIdGpioGpio16 = 17, /**< gpio_gpio 16 */
- kTopEarlgreyPlicIrqIdGpioGpio17 = 18, /**< gpio_gpio 17 */
- kTopEarlgreyPlicIrqIdGpioGpio18 = 19, /**< gpio_gpio 18 */
- kTopEarlgreyPlicIrqIdGpioGpio19 = 20, /**< gpio_gpio 19 */
- kTopEarlgreyPlicIrqIdGpioGpio20 = 21, /**< gpio_gpio 20 */
- kTopEarlgreyPlicIrqIdGpioGpio21 = 22, /**< gpio_gpio 21 */
- kTopEarlgreyPlicIrqIdGpioGpio22 = 23, /**< gpio_gpio 22 */
- kTopEarlgreyPlicIrqIdGpioGpio23 = 24, /**< gpio_gpio 23 */
- kTopEarlgreyPlicIrqIdGpioGpio24 = 25, /**< gpio_gpio 24 */
- kTopEarlgreyPlicIrqIdGpioGpio25 = 26, /**< gpio_gpio 25 */
- kTopEarlgreyPlicIrqIdGpioGpio26 = 27, /**< gpio_gpio 26 */
- kTopEarlgreyPlicIrqIdGpioGpio27 = 28, /**< gpio_gpio 27 */
- kTopEarlgreyPlicIrqIdGpioGpio28 = 29, /**< gpio_gpio 28 */
- kTopEarlgreyPlicIrqIdGpioGpio29 = 30, /**< gpio_gpio 29 */
- kTopEarlgreyPlicIrqIdGpioGpio30 = 31, /**< gpio_gpio 30 */
- kTopEarlgreyPlicIrqIdGpioGpio31 = 32, /**< gpio_gpio 31 */
- kTopEarlgreyPlicIrqIdUartTxWatermark = 33, /**< uart_tx_watermark */
- kTopEarlgreyPlicIrqIdUartRxWatermark = 34, /**< uart_rx_watermark */
- kTopEarlgreyPlicIrqIdUartTxEmpty = 35, /**< uart_tx_empty */
- kTopEarlgreyPlicIrqIdUartRxOverflow = 36, /**< uart_rx_overflow */
- kTopEarlgreyPlicIrqIdUartRxFrameErr = 37, /**< uart_rx_frame_err */
- kTopEarlgreyPlicIrqIdUartRxBreakErr = 38, /**< uart_rx_break_err */
- kTopEarlgreyPlicIrqIdUartRxTimeout = 39, /**< uart_rx_timeout */
- kTopEarlgreyPlicIrqIdUartRxParityErr = 40, /**< uart_rx_parity_err */
- kTopEarlgreyPlicIrqIdSpiDeviceRxf = 41, /**< spi_device_rxf */
- kTopEarlgreyPlicIrqIdSpiDeviceRxlvl = 42, /**< spi_device_rxlvl */
- kTopEarlgreyPlicIrqIdSpiDeviceTxlvl = 43, /**< spi_device_txlvl */
- kTopEarlgreyPlicIrqIdSpiDeviceRxerr = 44, /**< spi_device_rxerr */
- kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow = 45, /**< spi_device_rxoverflow */
- kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow = 46, /**< spi_device_txunderflow */
- kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 47, /**< flash_ctrl_prog_empty */
- kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 48, /**< flash_ctrl_prog_lvl */
- kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 49, /**< flash_ctrl_rd_full */
- kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 50, /**< flash_ctrl_rd_lvl */
- kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 51, /**< flash_ctrl_op_done */
- kTopEarlgreyPlicIrqIdFlashCtrlOpError = 52, /**< flash_ctrl_op_error */
- kTopEarlgreyPlicIrqIdHmacHmacDone = 53, /**< hmac_hmac_done */
- kTopEarlgreyPlicIrqIdHmacFifoEmpty = 54, /**< hmac_fifo_empty */
- kTopEarlgreyPlicIrqIdHmacHmacErr = 55, /**< hmac_hmac_err */
- kTopEarlgreyPlicIrqIdAlertHandlerClassa = 56, /**< alert_handler_classa */
- kTopEarlgreyPlicIrqIdAlertHandlerClassb = 57, /**< alert_handler_classb */
- kTopEarlgreyPlicIrqIdAlertHandlerClassc = 58, /**< alert_handler_classc */
- kTopEarlgreyPlicIrqIdAlertHandlerClassd = 59, /**< alert_handler_classd */
- kTopEarlgreyPlicIrqIdNmiGenEsc0 = 60, /**< nmi_gen_esc0 */
- kTopEarlgreyPlicIrqIdNmiGenEsc1 = 61, /**< nmi_gen_esc1 */
- kTopEarlgreyPlicIrqIdNmiGenEsc2 = 62, /**< nmi_gen_esc2 */
- kTopEarlgreyPlicIrqIdUsbdevPktReceived = 63, /**< usbdev_pkt_received */
- kTopEarlgreyPlicIrqIdUsbdevPktSent = 64, /**< usbdev_pkt_sent */
- kTopEarlgreyPlicIrqIdUsbdevDisconnected = 65, /**< usbdev_disconnected */
- kTopEarlgreyPlicIrqIdUsbdevHostLost = 66, /**< usbdev_host_lost */
- kTopEarlgreyPlicIrqIdUsbdevLinkReset = 67, /**< usbdev_link_reset */
- kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 68, /**< usbdev_link_suspend */
- kTopEarlgreyPlicIrqIdUsbdevLinkResume = 69, /**< usbdev_link_resume */
- kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 70, /**< usbdev_av_empty */
- kTopEarlgreyPlicIrqIdUsbdevRxFull = 71, /**< usbdev_rx_full */
- kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 72, /**< usbdev_av_overflow */
- kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 73, /**< usbdev_link_in_err */
- kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 74, /**< usbdev_rx_crc_err */
- kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 75, /**< usbdev_rx_pid_err */
- kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 76, /**< usbdev_rx_bitstuff_err */
- kTopEarlgreyPlicIrqIdUsbdevFrame = 77, /**< usbdev_frame */
- kTopEarlgreyPlicIrqIdUsbdevConnected = 78, /**< usbdev_connected */
- kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 79, /**< usbdev_link_out_err */
- kTopEarlgreyPlicIrqIdPwrmgrWakeup = 80, /**< pwrmgr_wakeup */
- kTopEarlgreyPlicIrqIdOtbnDone = 81, /**< otbn_done */
- kTopEarlgreyPlicIrqIdKeymgrOpDone = 82, /**< keymgr_op_done */
- kTopEarlgreyPlicIrqIdKmacKmacDone = 83, /**< kmac_kmac_done */
- kTopEarlgreyPlicIrqIdKmacFifoEmpty = 84, /**< kmac_fifo_empty */
- kTopEarlgreyPlicIrqIdKmacKmacErr = 85, /**< kmac_kmac_err */
- kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 86, /**< otp_ctrl_otp_operation_done */
- kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 87, /**< otp_ctrl_otp_error */
- kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 88, /**< csrng_cs_cmd_req_done */
- kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 89, /**< csrng_cs_entropy_req */
- kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 90, /**< csrng_cs_hw_inst_exc */
- kTopEarlgreyPlicIrqIdCsrngCsFifoErr = 91, /**< csrng_cs_fifo_err */
- kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 92, /**< edn0_edn_cmd_req_done */
- kTopEarlgreyPlicIrqIdEdn0EdnFifoErr = 93, /**< edn0_edn_fifo_err */
- kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 94, /**< edn1_edn_cmd_req_done */
- kTopEarlgreyPlicIrqIdEdn1EdnFifoErr = 95, /**< edn1_edn_fifo_err */
- kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 96, /**< entropy_src_es_entropy_valid */
- kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 97, /**< entropy_src_es_health_test_failed */
- kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr = 98, /**< entropy_src_es_fifo_err */
- kTopEarlgreyPlicIrqIdLast = 98, /**< \internal The Last Valid Interrupt ID. */
+ kTopEarlgreyPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
+ kTopEarlgreyPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
+ kTopEarlgreyPlicIrqIdUart0TxEmpty = 3, /**< uart0_tx_empty */
+ kTopEarlgreyPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
+ kTopEarlgreyPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
+ kTopEarlgreyPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
+ kTopEarlgreyPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
+ kTopEarlgreyPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
+ kTopEarlgreyPlicIrqIdUart1TxWatermark = 9, /**< uart1_tx_watermark */
+ kTopEarlgreyPlicIrqIdUart1RxWatermark = 10, /**< uart1_rx_watermark */
+ kTopEarlgreyPlicIrqIdUart1TxEmpty = 11, /**< uart1_tx_empty */
+ kTopEarlgreyPlicIrqIdUart1RxOverflow = 12, /**< uart1_rx_overflow */
+ kTopEarlgreyPlicIrqIdUart1RxFrameErr = 13, /**< uart1_rx_frame_err */
+ kTopEarlgreyPlicIrqIdUart1RxBreakErr = 14, /**< uart1_rx_break_err */
+ kTopEarlgreyPlicIrqIdUart1RxTimeout = 15, /**< uart1_rx_timeout */
+ kTopEarlgreyPlicIrqIdUart1RxParityErr = 16, /**< uart1_rx_parity_err */
+ kTopEarlgreyPlicIrqIdUart2TxWatermark = 17, /**< uart2_tx_watermark */
+ kTopEarlgreyPlicIrqIdUart2RxWatermark = 18, /**< uart2_rx_watermark */
+ kTopEarlgreyPlicIrqIdUart2TxEmpty = 19, /**< uart2_tx_empty */
+ kTopEarlgreyPlicIrqIdUart2RxOverflow = 20, /**< uart2_rx_overflow */
+ kTopEarlgreyPlicIrqIdUart2RxFrameErr = 21, /**< uart2_rx_frame_err */
+ kTopEarlgreyPlicIrqIdUart2RxBreakErr = 22, /**< uart2_rx_break_err */
+ kTopEarlgreyPlicIrqIdUart2RxTimeout = 23, /**< uart2_rx_timeout */
+ kTopEarlgreyPlicIrqIdUart2RxParityErr = 24, /**< uart2_rx_parity_err */
+ kTopEarlgreyPlicIrqIdUart3TxWatermark = 25, /**< uart3_tx_watermark */
+ kTopEarlgreyPlicIrqIdUart3RxWatermark = 26, /**< uart3_rx_watermark */
+ kTopEarlgreyPlicIrqIdUart3TxEmpty = 27, /**< uart3_tx_empty */
+ kTopEarlgreyPlicIrqIdUart3RxOverflow = 28, /**< uart3_rx_overflow */
+ kTopEarlgreyPlicIrqIdUart3RxFrameErr = 29, /**< uart3_rx_frame_err */
+ kTopEarlgreyPlicIrqIdUart3RxBreakErr = 30, /**< uart3_rx_break_err */
+ kTopEarlgreyPlicIrqIdUart3RxTimeout = 31, /**< uart3_rx_timeout */
+ kTopEarlgreyPlicIrqIdUart3RxParityErr = 32, /**< uart3_rx_parity_err */
+ kTopEarlgreyPlicIrqIdGpioGpio0 = 33, /**< gpio_gpio 0 */
+ kTopEarlgreyPlicIrqIdGpioGpio1 = 34, /**< gpio_gpio 1 */
+ kTopEarlgreyPlicIrqIdGpioGpio2 = 35, /**< gpio_gpio 2 */
+ kTopEarlgreyPlicIrqIdGpioGpio3 = 36, /**< gpio_gpio 3 */
+ kTopEarlgreyPlicIrqIdGpioGpio4 = 37, /**< gpio_gpio 4 */
+ kTopEarlgreyPlicIrqIdGpioGpio5 = 38, /**< gpio_gpio 5 */
+ kTopEarlgreyPlicIrqIdGpioGpio6 = 39, /**< gpio_gpio 6 */
+ kTopEarlgreyPlicIrqIdGpioGpio7 = 40, /**< gpio_gpio 7 */
+ kTopEarlgreyPlicIrqIdGpioGpio8 = 41, /**< gpio_gpio 8 */
+ kTopEarlgreyPlicIrqIdGpioGpio9 = 42, /**< gpio_gpio 9 */
+ kTopEarlgreyPlicIrqIdGpioGpio10 = 43, /**< gpio_gpio 10 */
+ kTopEarlgreyPlicIrqIdGpioGpio11 = 44, /**< gpio_gpio 11 */
+ kTopEarlgreyPlicIrqIdGpioGpio12 = 45, /**< gpio_gpio 12 */
+ kTopEarlgreyPlicIrqIdGpioGpio13 = 46, /**< gpio_gpio 13 */
+ kTopEarlgreyPlicIrqIdGpioGpio14 = 47, /**< gpio_gpio 14 */
+ kTopEarlgreyPlicIrqIdGpioGpio15 = 48, /**< gpio_gpio 15 */
+ kTopEarlgreyPlicIrqIdGpioGpio16 = 49, /**< gpio_gpio 16 */
+ kTopEarlgreyPlicIrqIdGpioGpio17 = 50, /**< gpio_gpio 17 */
+ kTopEarlgreyPlicIrqIdGpioGpio18 = 51, /**< gpio_gpio 18 */
+ kTopEarlgreyPlicIrqIdGpioGpio19 = 52, /**< gpio_gpio 19 */
+ kTopEarlgreyPlicIrqIdGpioGpio20 = 53, /**< gpio_gpio 20 */
+ kTopEarlgreyPlicIrqIdGpioGpio21 = 54, /**< gpio_gpio 21 */
+ kTopEarlgreyPlicIrqIdGpioGpio22 = 55, /**< gpio_gpio 22 */
+ kTopEarlgreyPlicIrqIdGpioGpio23 = 56, /**< gpio_gpio 23 */
+ kTopEarlgreyPlicIrqIdGpioGpio24 = 57, /**< gpio_gpio 24 */
+ kTopEarlgreyPlicIrqIdGpioGpio25 = 58, /**< gpio_gpio 25 */
+ kTopEarlgreyPlicIrqIdGpioGpio26 = 59, /**< gpio_gpio 26 */
+ kTopEarlgreyPlicIrqIdGpioGpio27 = 60, /**< gpio_gpio 27 */
+ kTopEarlgreyPlicIrqIdGpioGpio28 = 61, /**< gpio_gpio 28 */
+ kTopEarlgreyPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
+ kTopEarlgreyPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
+ kTopEarlgreyPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxf = 65, /**< spi_device_rxf */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxlvl = 66, /**< spi_device_rxlvl */
+ kTopEarlgreyPlicIrqIdSpiDeviceTxlvl = 67, /**< spi_device_txlvl */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxerr = 68, /**< spi_device_rxerr */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow = 69, /**< spi_device_rxoverflow */
+ kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow = 70, /**< spi_device_txunderflow */
+ kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 71, /**< flash_ctrl_prog_empty */
+ kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 72, /**< flash_ctrl_prog_lvl */
+ kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 73, /**< flash_ctrl_rd_full */
+ kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 74, /**< flash_ctrl_rd_lvl */
+ kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 75, /**< flash_ctrl_op_done */
+ kTopEarlgreyPlicIrqIdFlashCtrlOpError = 76, /**< flash_ctrl_op_error */
+ kTopEarlgreyPlicIrqIdHmacHmacDone = 77, /**< hmac_hmac_done */
+ kTopEarlgreyPlicIrqIdHmacFifoEmpty = 78, /**< hmac_fifo_empty */
+ kTopEarlgreyPlicIrqIdHmacHmacErr = 79, /**< hmac_hmac_err */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassa = 80, /**< alert_handler_classa */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassb = 81, /**< alert_handler_classb */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassc = 82, /**< alert_handler_classc */
+ kTopEarlgreyPlicIrqIdAlertHandlerClassd = 83, /**< alert_handler_classd */
+ kTopEarlgreyPlicIrqIdNmiGenEsc0 = 84, /**< nmi_gen_esc0 */
+ kTopEarlgreyPlicIrqIdNmiGenEsc1 = 85, /**< nmi_gen_esc1 */
+ kTopEarlgreyPlicIrqIdNmiGenEsc2 = 86, /**< nmi_gen_esc2 */
+ kTopEarlgreyPlicIrqIdUsbdevPktReceived = 87, /**< usbdev_pkt_received */
+ kTopEarlgreyPlicIrqIdUsbdevPktSent = 88, /**< usbdev_pkt_sent */
+ kTopEarlgreyPlicIrqIdUsbdevDisconnected = 89, /**< usbdev_disconnected */
+ kTopEarlgreyPlicIrqIdUsbdevHostLost = 90, /**< usbdev_host_lost */
+ kTopEarlgreyPlicIrqIdUsbdevLinkReset = 91, /**< usbdev_link_reset */
+ kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 92, /**< usbdev_link_suspend */
+ kTopEarlgreyPlicIrqIdUsbdevLinkResume = 93, /**< usbdev_link_resume */
+ kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 94, /**< usbdev_av_empty */
+ kTopEarlgreyPlicIrqIdUsbdevRxFull = 95, /**< usbdev_rx_full */
+ kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 96, /**< usbdev_av_overflow */
+ kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 97, /**< usbdev_link_in_err */
+ kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 98, /**< usbdev_rx_crc_err */
+ kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 99, /**< usbdev_rx_pid_err */
+ kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 100, /**< usbdev_rx_bitstuff_err */
+ kTopEarlgreyPlicIrqIdUsbdevFrame = 101, /**< usbdev_frame */
+ kTopEarlgreyPlicIrqIdUsbdevConnected = 102, /**< usbdev_connected */
+ kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 103, /**< usbdev_link_out_err */
+ kTopEarlgreyPlicIrqIdPwrmgrWakeup = 104, /**< pwrmgr_wakeup */
+ kTopEarlgreyPlicIrqIdOtbnDone = 105, /**< otbn_done */
+ kTopEarlgreyPlicIrqIdKeymgrOpDone = 106, /**< keymgr_op_done */
+ kTopEarlgreyPlicIrqIdKmacKmacDone = 107, /**< kmac_kmac_done */
+ kTopEarlgreyPlicIrqIdKmacFifoEmpty = 108, /**< kmac_fifo_empty */
+ kTopEarlgreyPlicIrqIdKmacKmacErr = 109, /**< kmac_kmac_err */
+ kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 110, /**< otp_ctrl_otp_operation_done */
+ kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 111, /**< otp_ctrl_otp_error */
+ kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 112, /**< csrng_cs_cmd_req_done */
+ kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 113, /**< csrng_cs_entropy_req */
+ kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 114, /**< csrng_cs_hw_inst_exc */
+ kTopEarlgreyPlicIrqIdCsrngCsFifoErr = 115, /**< csrng_cs_fifo_err */
+ kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 116, /**< edn0_edn_cmd_req_done */
+ kTopEarlgreyPlicIrqIdEdn0EdnFifoErr = 117, /**< edn0_edn_fifo_err */
+ kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 118, /**< edn1_edn_cmd_req_done */
+ kTopEarlgreyPlicIrqIdEdn1EdnFifoErr = 119, /**< edn1_edn_fifo_err */
+ kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 120, /**< entropy_src_es_entropy_valid */
+ kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 121, /**< entropy_src_es_health_test_failed */
+ kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr = 122, /**< entropy_src_es_fifo_err */
+ kTopEarlgreyPlicIrqIdLast = 122, /**< \internal The Last Valid Interrupt ID. */
} top_earlgrey_plic_irq_id_t;
/**
@@ -715,7 +796,7 @@
* `top_earlgrey_plic_peripheral_t`.
*/
extern const top_earlgrey_plic_peripheral_t
- top_earlgrey_plic_interrupt_for_peripheral[99];
+ top_earlgrey_plic_interrupt_for_peripheral[123];
/**
* PLIC Interrupt Target.
@@ -831,7 +912,10 @@
kTopEarlgreyPinmuxPeripheralInGpioGpio29 = 29, /**< gpio_gpio 29 */
kTopEarlgreyPinmuxPeripheralInGpioGpio30 = 30, /**< gpio_gpio 30 */
kTopEarlgreyPinmuxPeripheralInGpioGpio31 = 31, /**< gpio_gpio 31 */
- kTopEarlgreyPinmuxPeripheralInLast = 31, /**< \internal Last valid peripheral input */
+ kTopEarlgreyPinmuxPeripheralInUart1Rx = 32, /**< uart1_rx */
+ kTopEarlgreyPinmuxPeripheralInUart2Rx = 33, /**< uart2_rx */
+ kTopEarlgreyPinmuxPeripheralInUart3Rx = 34, /**< uart3_rx */
+ kTopEarlgreyPinmuxPeripheralInLast = 34, /**< \internal Last valid peripheral input */
} top_earlgrey_pinmux_peripheral_in_t;
/**
@@ -953,7 +1037,10 @@
kTopEarlgreyPinmuxOutselGpioGpio29 = 32, /**< gpio_gpio 29 */
kTopEarlgreyPinmuxOutselGpioGpio30 = 33, /**< gpio_gpio 30 */
kTopEarlgreyPinmuxOutselGpioGpio31 = 34, /**< gpio_gpio 31 */
- kTopEarlgreyPinmuxOutselLast = 34, /**< \internal Last valid outsel value */
+ kTopEarlgreyPinmuxOutselUart1Tx = 35, /**< uart1_tx */
+ kTopEarlgreyPinmuxOutselUart2Tx = 36, /**< uart2_tx */
+ kTopEarlgreyPinmuxOutselUart3Tx = 37, /**< uart3_tx */
+ kTopEarlgreyPinmuxOutselLast = 37, /**< \internal Last valid outsel value */
} top_earlgrey_pinmux_outsel_t;
/**
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
index 6442f53..cc37e7e 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
@@ -43,7 +43,7 @@
/**
* Memory base address for ram_ret in top earlgrey.
*/
-#define TOP_EARLGREY_RAM_RET_BASE_ADDR 0x18000000
+#define TOP_EARLGREY_RAM_RET_BASE_ADDR 0x40520000
/**
* Memory size for ram_ret in top earlgrey.
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
index 96770c7..f19a4ac 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
@@ -8,6 +8,6 @@
MEMORY {
rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x4000
ram_main(rw) : ORIGIN = 0x10000000, LENGTH = 0x20000
- ram_ret(rw) : ORIGIN = 0x18000000, LENGTH = 0x1000
+ ram_ret(rw) : ORIGIN = 0x40520000, LENGTH = 0x1000
eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000
}
