lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
| 4 | |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 5 | #include <iostream> |
Rupert Swarbrick | 6bd0867 | 2021-03-16 17:38:21 +0000 | [diff] [blame] | 6 | #include <string> |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 7 | |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 8 | #include "verilated_toplevel.h" |
Rupert Swarbrick | a695196 | 2020-10-27 11:26:28 +0000 | [diff] [blame] | 9 | #include "verilator_memutil.h" |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 10 | #include "verilator_sim_ctrl.h" |
| 11 | |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 12 | int main(int argc, char **argv) { |
Michael Schaffner | 93fe50c | 2021-03-31 16:25:42 -0700 | [diff] [blame] | 13 | chip_earlgrey_verilator top; |
Rupert Swarbrick | a695196 | 2020-10-27 11:26:28 +0000 | [diff] [blame] | 14 | VerilatorMemUtil memutil; |
Philipp Wagner | d4d65a1 | 2019-11-28 16:59:19 +0000 | [diff] [blame] | 15 | VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance(); |
| 16 | simctrl.SetTop(&top, &top.clk_i, &top.rst_ni, |
| 17 | VerilatorSimCtrlFlags::ResetPolarityNegative); |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 18 | |
Michael Schaffner | 93fe50c | 2021-03-31 16:25:42 -0700 | [diff] [blame] | 19 | std::string top_scope("TOP.chip_earlgrey_verilator.top_earlgrey"); |
Rupert Swarbrick | 6bd0867 | 2021-03-16 17:38:21 +0000 | [diff] [blame] | 20 | std::string ram1p_adv_scope( |
| 21 | "u_prim_ram_1p_adv.u_mem." |
Michael Schaffner | 0beb8a4 | 2020-06-05 23:17:40 -0700 | [diff] [blame] | 22 | "gen_generic.u_impl_generic"); |
Rupert Swarbrick | 6bd0867 | 2021-03-16 17:38:21 +0000 | [diff] [blame] | 23 | |
Rupert Swarbrick | 830aac5 | 2021-03-19 17:00:18 +0000 | [diff] [blame] | 24 | MemArea rom(top_scope + (".u_rom_ctrl.u_rom.u_rom." |
| 25 | "u_prim_rom.gen_generic.u_impl_generic"), |
| 26 | 0x4000 / 4, 4); |
Rupert Swarbrick | 532e2e7 | 2021-03-18 12:04:08 +0000 | [diff] [blame] | 27 | MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4, |
| 28 | 4); |
| 29 | MemArea flash(top_scope + |
| 30 | ".u_flash_eflash.u_flash.gen_generic.u_impl_generic." |
| 31 | "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem." |
| 32 | "gen_generic.u_impl_generic", |
| 33 | 0x100000 / 8, 8); |
| 34 | MemArea otp(top_scope + ".u_otp_ctrl.u_otp.gen_generic.u_impl_generic." + |
| 35 | ram1p_adv_scope, |
| 36 | 0x4000 / 4, 4); |
Rupert Swarbrick | 6bd0867 | 2021-03-16 17:38:21 +0000 | [diff] [blame] | 37 | |
Rupert Swarbrick | 532e2e7 | 2021-03-18 12:04:08 +0000 | [diff] [blame] | 38 | memutil.RegisterMemoryArea("rom", 0x8000, &rom); |
| 39 | memutil.RegisterMemoryArea("ram", 0x10000000u, &ram); |
| 40 | memutil.RegisterMemoryArea("flash", 0x20000000u, &flash); |
| 41 | memutil.RegisterMemoryArea("otp", 0x40000000u /* (bogus LMA) */, &otp); |
Philipp Wagner | 74a39e3 | 2020-01-03 08:44:40 +0000 | [diff] [blame] | 42 | simctrl.RegisterExtension(&memutil); |
Rupert Swarbrick | 6bd0867 | 2021-03-16 17:38:21 +0000 | [diff] [blame] | 43 | |
Timothy Chen | c9a00fe | 2021-02-17 17:37:56 -0800 | [diff] [blame] | 44 | // The initial reset delay must be long enough such that pwr/rst/clkmgr will |
| 45 | // release clocks to the entire design. This allows for synchronous resets |
| 46 | // to appropriately propagate. |
| 47 | // The reset duration must be appropriately sized to the divider for clk_aon |
Michael Schaffner | 93fe50c | 2021-03-31 16:25:42 -0700 | [diff] [blame] | 48 | // in chip_earlgrey_verilator.sv. It must be at least 2 cycles of clk_aon. |
Timothy Chen | c9a00fe | 2021-02-17 17:37:56 -0800 | [diff] [blame] | 49 | simctrl.SetInitialResetDelay(500); |
| 50 | simctrl.SetResetDuration(10); |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 51 | |
Philipp Wagner | d4d65a1 | 2019-11-28 16:59:19 +0000 | [diff] [blame] | 52 | std::cout << "Simulation of OpenTitan Earl Grey" << std::endl |
| 53 | << "=================================" << std::endl |
| 54 | << std::endl; |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 55 | |
Rupert Swarbrick | 1d329c4 | 2020-12-09 14:02:34 +0000 | [diff] [blame] | 56 | return simctrl.Exec(argc, argv).first; |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 57 | } |