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lowRISC Contributors802543a2019-08-31 12:12:56 +01001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
lowRISC Contributors802543a2019-08-31 12:12:56 +01005#include <iostream>
Rupert Swarbrick6bd08672021-03-16 17:38:21 +00006#include <string>
lowRISC Contributors802543a2019-08-31 12:12:56 +01007
lowRISC Contributors802543a2019-08-31 12:12:56 +01008#include "verilated_toplevel.h"
Rupert Swarbricka6951962020-10-27 11:26:28 +00009#include "verilator_memutil.h"
lowRISC Contributors802543a2019-08-31 12:12:56 +010010#include "verilator_sim_ctrl.h"
11
lowRISC Contributors802543a2019-08-31 12:12:56 +010012int main(int argc, char **argv) {
Michael Schaffner93fe50c2021-03-31 16:25:42 -070013 chip_earlgrey_verilator top;
Rupert Swarbricka6951962020-10-27 11:26:28 +000014 VerilatorMemUtil memutil;
Philipp Wagnerd4d65a12019-11-28 16:59:19 +000015 VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
16 simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
17 VerilatorSimCtrlFlags::ResetPolarityNegative);
lowRISC Contributors802543a2019-08-31 12:12:56 +010018
Michael Schaffner93fe50c2021-03-31 16:25:42 -070019 std::string top_scope("TOP.chip_earlgrey_verilator.top_earlgrey");
Rupert Swarbrick6bd08672021-03-16 17:38:21 +000020 std::string ram1p_adv_scope(
21 "u_prim_ram_1p_adv.u_mem."
Michael Schaffner0beb8a42020-06-05 23:17:40 -070022 "gen_generic.u_impl_generic");
Rupert Swarbrick6bd08672021-03-16 17:38:21 +000023
Rupert Swarbrick830aac52021-03-19 17:00:18 +000024 MemArea rom(top_scope + (".u_rom_ctrl.u_rom.u_rom."
25 "u_prim_rom.gen_generic.u_impl_generic"),
26 0x4000 / 4, 4);
Rupert Swarbrick532e2e72021-03-18 12:04:08 +000027 MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4,
28 4);
29 MemArea flash(top_scope +
30 ".u_flash_eflash.u_flash.gen_generic.u_impl_generic."
31 "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem."
32 "gen_generic.u_impl_generic",
33 0x100000 / 8, 8);
34 MemArea otp(top_scope + ".u_otp_ctrl.u_otp.gen_generic.u_impl_generic." +
35 ram1p_adv_scope,
36 0x4000 / 4, 4);
Rupert Swarbrick6bd08672021-03-16 17:38:21 +000037
Rupert Swarbrick532e2e72021-03-18 12:04:08 +000038 memutil.RegisterMemoryArea("rom", 0x8000, &rom);
39 memutil.RegisterMemoryArea("ram", 0x10000000u, &ram);
40 memutil.RegisterMemoryArea("flash", 0x20000000u, &flash);
41 memutil.RegisterMemoryArea("otp", 0x40000000u /* (bogus LMA) */, &otp);
Philipp Wagner74a39e32020-01-03 08:44:40 +000042 simctrl.RegisterExtension(&memutil);
Rupert Swarbrick6bd08672021-03-16 17:38:21 +000043
Timothy Chenc9a00fe2021-02-17 17:37:56 -080044 // The initial reset delay must be long enough such that pwr/rst/clkmgr will
45 // release clocks to the entire design. This allows for synchronous resets
46 // to appropriately propagate.
47 // The reset duration must be appropriately sized to the divider for clk_aon
Michael Schaffner93fe50c2021-03-31 16:25:42 -070048 // in chip_earlgrey_verilator.sv. It must be at least 2 cycles of clk_aon.
Timothy Chenc9a00fe2021-02-17 17:37:56 -080049 simctrl.SetInitialResetDelay(500);
50 simctrl.SetResetDuration(10);
lowRISC Contributors802543a2019-08-31 12:12:56 +010051
Philipp Wagnerd4d65a12019-11-28 16:59:19 +000052 std::cout << "Simulation of OpenTitan Earl Grey" << std::endl
53 << "=================================" << std::endl
54 << std::endl;
lowRISC Contributors802543a2019-08-31 12:12:56 +010055
Rupert Swarbrick1d329c42020-12-09 14:02:34 +000056 return simctrl.Exec(argc, argv).first;
lowRISC Contributors802543a2019-08-31 12:12:56 +010057}