commit 74a39e3e147145596fbcc25b0720662c2f417e54
author Philipp Wagner <phw@lowrisc.org> Fri Jan 03 08:44:40 2020 +0000
committer Philipp Wagner <mail@philipp-wagner.com> Fri Jan 03 17:40:26 2020 +0100
tree 4f1fa0c78a81b69e320c6a6c32032af87271ed43
parent fa12ce0845c7ff61cb22052be72b495d73ee7535

Update lowrisc_ibex to lowRISC/ibex@7e22830

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
7e2283056b18cf3b1733d12cfd877a46102ab201

The import required the following updates to our in-tree code:
- Update top_earlgrey to align its Verilator simulation with the changes
  made to simutil_verilator.
- Update the test harness to always use `--meminit=flash,...`, instead of
  `--meminit flash,...`. The variant with space doesn't work any more
  (and isn't documented to work).

* [rtl] Trigger C decoder assertions only if instr valid (Pirmin
  Vogel)
* [DV] Continue argument parsing (Tobias Wölfel)
* [ci] Add clang-format checking to CI (Tom Roberts)
* [verilator] Fix ELF processing (Bryan Cantrill)
* SimCtrlExtension: Add a default destructor (Philipp Wagner)
* [verilator] Modify verilator examples for memutils (Tom Roberts)
* [verilator] Separate out memory loading utilities (Tom Roberts)
* [make] Fix target reference (Tobias Wölfel)
* [rtl] By default, forward incoming instruction in C decoder (Pirmin
  Vogel)
* [rtl] Use macros for all SystemVerilog assertions (Pirmin Vogel)
* [rtl] Remove X assignments, add SVAs for selector signals (Pirmin
  Vogel)
* [rtl] Consistently use `data_offset` signal in LSU (Pirmin Vogel)
* [DV] Fix TB read responses (lowRISC/ibex#531) (udinator)
* Update google_riscv-dv to google/riscv-dv@9ecee87 (lowRISC/ibex#530)
  (udinator)
* Update google_riscv-dv to google/riscv-dv@74b8cb6 (lowRISC/ibex#529)
  (udinator)
* [DV] fix incorrect irq_seq handle name (lowRISC/ibex#525) (udinator)
* [DV] update MISA csr yaml description (lowRISC/ibex#513) (udinator)
* [DV] Enable sending multiple interrupts at once (lowRISC/ibex#519)
  (udinator)
* [DV] update override to riscv_asm_program gen in Makefile
  (lowRISC/ibex#520) (udinator)
* [RTL] Only restore from mstack in nmi mode (Greg Chadwick)
* Update google_riscv-dv to google/riscv-dv@5b1dd4e (lowRISC/ibex#523)
  (udinator)
* [DV] add support_unaligned_load_store setting (lowRISC/ibex#521)
  (udinator)
* [DV] Fix xRET wait checks (lowRISC/ibex#515) (udinator)
* [doc] Add a comment on mhpmcounter optimization (Tom Roberts)
* [dbg] Add minimal hardware breakpoint support (Tom Roberts)
* [verilator] Clarify ELF BSS handling (Tobias Wölfel)
* [examples] Fix spelling for description type (Tobias Wölfel)
* [csr] Add U Mode support to misa (Tom Roberts)
* RTL simulation scripts for Cadence tool was added (Taras Dulibianyk)
* Add Synopsys VCS Support for Ibex Simple System (Mehrdad Biglari)
* Pluseargs parsing was corrected (Taras Dulibianyk)
* [ci] Add CS registers TB to CI (Tom Roberts)

Signed-off-by: Philipp Wagner <phw@lowrisc.org>