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Timothy Chenff4a7702020-10-27 15:08:53 -07001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Flash Controller Module
6//
7//
8
9`include "prim_assert.sv"
10
Timothy Chenf52a4612020-12-04 20:37:49 -080011module flash_ctrl import flash_ctrl_pkg::*; #(
Timothy Chen16741102021-01-15 17:32:13 -080012 parameter logic AlertAsyncOn = 1'b1,
Timothy Chenaeffadc2020-12-11 15:03:07 -080013 parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
14 parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
15 parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
16 parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
Timothy Chenf52a4612020-12-04 20:37:49 -080017) (
Timothy Chenff4a7702020-10-27 15:08:53 -070018 input clk_i,
19 input rst_ni,
20
Timothy Chenf52a4612020-12-04 20:37:49 -080021 input clk_otp_i,
22 input rst_otp_ni,
23
Timothy Chen8ea1b412020-11-18 18:32:08 -080024 // life cycle interface
Timothy Chen99f3e3a2020-12-09 18:30:19 -080025 input lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en_i,
26 input lc_ctrl_pkg::lc_tx_t lc_owner_seed_sw_rw_en_i,
27 input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_rd_en_i,
28 input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i,
29 input lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i,
Timothy Chen8ea1b412020-11-18 18:32:08 -080030
Timothy Chenff4a7702020-10-27 15:08:53 -070031 // Bus Interface
32 input tlul_pkg::tl_h2d_t tl_i,
33 output tlul_pkg::tl_d2h_t tl_o,
34
35 // Flash Interface
36 input flash_rsp_t flash_i,
37 output flash_req_t flash_o,
38
39 // otp/lc/pwrmgr/keymgr Interface
Timothy Chenf52a4612020-12-04 20:37:49 -080040 output otp_ctrl_pkg::flash_otp_key_req_t otp_o,
41 input otp_ctrl_pkg::flash_otp_key_rsp_t otp_i,
Timothy Chend39402a2020-12-15 20:34:09 -080042 input lc_ctrl_pkg::lc_tx_t rma_req_i,
43 input lc_ctrl_pkg::lc_flash_rma_seed_t rma_seed_i,
44 output lc_ctrl_pkg::lc_tx_t rma_ack_o,
Timothy Chenff4a7702020-10-27 15:08:53 -070045 input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
46 output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
Timothy Chenff4a7702020-10-27 15:08:53 -070047 output keymgr_flash_t keymgr_o,
48
Timothy Chend8fded82021-02-22 11:32:55 -080049 // IOs
50 input cio_tck_i,
51 input cio_tms_i,
52 input cio_tdi_i,
53 output logic cio_tdo_en_o,
54 output logic cio_tdo_o,
55
Timothy Chenff4a7702020-10-27 15:08:53 -070056 // Interrupts
57 output logic intr_prog_empty_o, // Program fifo is empty
58 output logic intr_prog_lvl_o, // Program fifo is empty
59 output logic intr_rd_full_o, // Read fifo is full
60 output logic intr_rd_lvl_o, // Read fifo is full
61 output logic intr_op_done_o, // Requested flash operation (wr/erase) done
Timothy Chen16741102021-01-15 17:32:13 -080062
63 // Alerts
64 input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i,
65 output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o
66
67
Timothy Chenff4a7702020-10-27 15:08:53 -070068);
69
70 import flash_ctrl_reg_pkg::*;
71
72 flash_ctrl_reg2hw_t reg2hw;
73 flash_ctrl_hw2reg_t hw2reg;
74
Timothy Chen6e495182020-12-28 16:16:35 -080075 tlul_pkg::tl_h2d_t tl_win_h2d [3];
76 tlul_pkg::tl_d2h_t tl_win_d2h [3];
Timothy Chenff4a7702020-10-27 15:08:53 -070077
Timothy Chen6e495182020-12-28 16:16:35 -080078 assign tl_win_d2h[2] = flash_i.tl_flash_p2c;
Timothy Chenff4a7702020-10-27 15:08:53 -070079 // Register module
80 flash_ctrl_reg_top u_reg (
81 .clk_i,
82 .rst_ni,
83
84 .tl_i,
85 .tl_o,
86
Timothy Chen6e495182020-12-28 16:16:35 -080087 .tl_win_o (tl_win_h2d),
88 .tl_win_i (tl_win_d2h),
Timothy Chenff4a7702020-10-27 15:08:53 -070089
90 .reg2hw,
91 .hw2reg,
92
Timothy Chen8ec347f2021-03-02 11:52:17 -080093 .intg_err_o (),
Timothy Chenff4a7702020-10-27 15:08:53 -070094 .devmode_i (1'b1)
95 );
96
97 // FIFO Connections
98 logic prog_fifo_wvalid;
99 logic prog_fifo_wready;
100 logic prog_fifo_rvalid;
101 logic prog_fifo_ren;
102 logic [BusWidth-1:0] prog_fifo_wdata;
103 logic [BusWidth-1:0] prog_fifo_rdata;
104 logic [FifoDepthW-1:0] prog_fifo_depth;
105 logic rd_fifo_wready;
106 logic rd_fifo_rvalid;
107 logic rd_fifo_rready;
108 logic rd_fifo_wen;
109 logic rd_fifo_ren;
110 logic [BusWidth-1:0] rd_fifo_wdata;
111 logic [BusWidth-1:0] rd_fifo_rdata;
112 logic [FifoDepthW-1:0] rd_fifo_depth;
Timothy Chen71d98f82020-12-17 17:17:25 -0800113 logic rd_fifo_full;
Timothy Chenff4a7702020-10-27 15:08:53 -0700114
115 // Program Control Connections
116 logic prog_flash_req;
117 logic prog_flash_ovfl;
118 logic [BusAddrW-1:0] prog_flash_addr;
119 logic prog_op_valid;
120
121 // Read Control Connections
122 logic rd_flash_req;
123 logic rd_flash_ovfl;
124 logic [BusAddrW-1:0] rd_flash_addr;
125
126 // Erase Control Connections
127 logic erase_flash_req;
128 logic [BusAddrW-1:0] erase_flash_addr;
129 flash_erase_e erase_flash_type;
130
131 // Done / Error signaling from ctrl modules
132 logic prog_done, rd_done, erase_done;
133 logic prog_err, rd_err, erase_err;
134
Timothy Chend5323562020-12-02 16:10:44 -0800135 // Flash Memory Properties Connections
Timothy Chenff4a7702020-10-27 15:08:53 -0700136 logic [BusAddrW-1:0] flash_addr;
137 logic flash_req;
138 logic flash_rd_done, flash_prog_done, flash_erase_done;
139 logic flash_mp_error;
140 logic [BusWidth-1:0] flash_prog_data;
141 logic flash_prog_last;
142 flash_prog_e flash_prog_type;
143 logic [BusWidth-1:0] flash_rd_data;
144 logic flash_rd_err;
145 logic flash_phy_busy;
146 logic rd_op;
147 logic prog_op;
148 logic erase_op;
149 logic [AllPagesW-1:0] err_addr;
150 flash_lcmgr_phase_e phase;
151
152 // Flash control arbitration connections to hardware interface
Timothy Chenf52a4612020-12-04 20:37:49 -0800153 flash_key_t addr_key;
154 flash_key_t data_key;
Timothy Chenff4a7702020-10-27 15:08:53 -0700155 flash_ctrl_reg2hw_control_reg_t hw_ctrl;
156 logic hw_req;
157 logic [top_pkg::TL_AW-1:0] hw_addr;
158 logic hw_done;
159 logic hw_err;
160 logic hw_rvalid;
161 logic hw_rready;
Timothy Chend39402a2020-12-15 20:34:09 -0800162 logic hw_wvalid;
163 logic [BusWidth-1:0] hw_wdata;
164 logic hw_wready;
Timothy Chenff4a7702020-10-27 15:08:53 -0700165 flash_sel_e if_sel;
166 logic sw_sel;
167 flash_lcmgr_phase_e hw_phase;
168 logic creator_seed_priv;
169 logic owner_seed_priv;
170
171 // Flash control arbitration connections to software interface
172 logic sw_ctrl_done;
173 logic sw_ctrl_err;
174
175 // Flash control muxed connections
176 flash_ctrl_reg2hw_control_reg_t muxed_ctrl;
177 logic [top_pkg::TL_AW-1:0] muxed_addr;
178 logic op_start;
179 logic [11:0] op_num_words;
180 logic [BusAddrW-1:0] op_addr;
181 flash_op_e op_type;
182 flash_part_e op_part;
183 logic [InfoTypesWidth-1:0] op_info_sel;
184 flash_erase_e op_erase_type;
185 flash_prog_e op_prog_type;
186
187 logic ctrl_init_busy;
188 logic fifo_clr;
189
190 // software tlul to flash control aribration
191 logic sw_rvalid;
192 logic adapter_rvalid;
193 logic sw_wvalid;
Timothy Chend39402a2020-12-15 20:34:09 -0800194 logic [BusWidth-1:0] sw_wdata;
Timothy Chenff4a7702020-10-27 15:08:53 -0700195 logic sw_wen;
196 logic sw_wready;
197
198 // lfsr for local entropy usage
199 logic [31:0] rand_val;
200 logic lfsr_en;
Timothy Chend39402a2020-12-15 20:34:09 -0800201 logic lfsr_seed_en;
Timothy Chenff4a7702020-10-27 15:08:53 -0700202
Timothy Chen8ea1b412020-11-18 18:32:08 -0800203 // life cycle connections
Cindy Chen39b14342021-01-29 16:25:24 -0800204 lc_ctrl_pkg::lc_tx_t [0:0] lc_creator_seed_sw_rw_en;
205 lc_ctrl_pkg::lc_tx_t [0:0] lc_owner_seed_sw_rw_en;
206 lc_ctrl_pkg::lc_tx_t [0:0] lc_iso_part_sw_rd_en;
207 lc_ctrl_pkg::lc_tx_t [0:0] lc_iso_part_sw_wr_en;
208 lc_ctrl_pkg::lc_tx_t [0:0] lc_seed_hw_rd_en;
Timothy Chen8ea1b412020-11-18 18:32:08 -0800209
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800210 // synchronize enables into local domain
Timothy Chen8d923152020-12-02 18:01:28 -0800211 prim_lc_sync #(
212 .NumCopies(1)
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800213 ) u_lc_creator_seed_sw_rw_en_sync (
Timothy Chen8d923152020-12-02 18:01:28 -0800214 .clk_i,
215 .rst_ni,
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800216 .lc_en_i(lc_creator_seed_sw_rw_en_i),
217 .lc_en_o(lc_creator_seed_sw_rw_en)
Timothy Chen8d923152020-12-02 18:01:28 -0800218 );
219
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800220 prim_lc_sync #(
221 .NumCopies(1)
222 ) u_lc_owner_seed_sw_rw_en_sync (
223 .clk_i,
224 .rst_ni,
225 .lc_en_i(lc_owner_seed_sw_rw_en_i),
226 .lc_en_o(lc_owner_seed_sw_rw_en)
227 );
228
229 prim_lc_sync #(
230 .NumCopies(1)
231 ) u_lc_iso_part_sw_rd_en_sync (
232 .clk_i,
233 .rst_ni,
234 .lc_en_i(lc_iso_part_sw_rd_en_i),
235 .lc_en_o(lc_iso_part_sw_rd_en)
236 );
237
238 prim_lc_sync #(
239 .NumCopies(1)
240 ) u_lc_iso_part_sw_wr_en_sync (
241 .clk_i,
242 .rst_ni,
243 .lc_en_i(lc_iso_part_sw_wr_en_i),
244 .lc_en_o(lc_iso_part_sw_wr_en)
245 );
246
247 prim_lc_sync #(
248 .NumCopies(1)
249 ) u_lc_seed_hw_rd_en_sync (
250 .clk_i,
251 .rst_ni,
252 .lc_en_i(lc_seed_hw_rd_en_i),
253 .lc_en_o(lc_seed_hw_rd_en)
254 );
Timothy Chen8d923152020-12-02 18:01:28 -0800255
Timothy Chenff4a7702020-10-27 15:08:53 -0700256 prim_lfsr #(
Timothy Chenaeffadc2020-12-11 15:03:07 -0800257 .EntropyDw(EdnWidth),
Timothy Chenf52a4612020-12-04 20:37:49 -0800258 .LfsrDw(LfsrWidth),
Timothy Chenaeffadc2020-12-11 15:03:07 -0800259 .StateOutDw(LfsrWidth),
260 .DefaultSeed(RndCnstLfsrSeed),
261 .StatePermEn(1),
262 .StatePerm(RndCnstLfsrPerm)
Timothy Chenff4a7702020-10-27 15:08:53 -0700263 ) u_lfsr (
264 .clk_i,
265 .rst_ni,
Timothy Chend39402a2020-12-15 20:34:09 -0800266 .seed_en_i(lfsr_seed_en),
267 .seed_i(rma_seed_i),
Timothy Chenff4a7702020-10-27 15:08:53 -0700268 .lfsr_en_i(lfsr_en),
Timothy Chenaeffadc2020-12-11 15:03:07 -0800269 .entropy_i('0),
Timothy Chenff4a7702020-10-27 15:08:53 -0700270 .state_o(rand_val)
271 );
272
273 // flash control arbitration between softawre / harware interfaces
274 flash_ctrl_arb u_ctrl_arb (
275 .clk_i,
276 .rst_ni,
277
278 // software interface to rd_ctrl / erase_ctrl
279 .sw_ctrl_i(reg2hw.control),
280 .sw_addr_i(reg2hw.addr.q),
281 .sw_ack_o(sw_ctrl_done),
282 .sw_err_o(sw_ctrl_err),
283
284 // software interface to rd_fifo
285 .sw_rvalid_o(sw_rvalid),
286 .sw_rready_i(adapter_rvalid),
287
288 // software interface to prog_fifo
289 .sw_wvalid_i(sw_wvalid & sw_wen),
Timothy Chend39402a2020-12-15 20:34:09 -0800290 .sw_wdata_i(sw_wdata),
Timothy Chenff4a7702020-10-27 15:08:53 -0700291 .sw_wready_o(sw_wready),
292
293 // hardware interface to rd_ctrl / erase_ctrl
294 .hw_req_i(hw_req),
295 .hw_ctrl_i(hw_ctrl),
296
297 // hardware interface indicating operation phase
298 .hw_phase_i(hw_phase),
299
300 // hardware works on word address, however software expects byte address
301 .hw_addr_i(hw_addr),
302 .hw_ack_o(hw_done),
303 .hw_err_o(hw_err),
304
305 // hardware interface to rd_fifo
306 .hw_rvalid_o(hw_rvalid),
307 .hw_rready_i(hw_rready),
Timothy Chend39402a2020-12-15 20:34:09 -0800308 .hw_wvalid_i(hw_wvalid),
309 .hw_wdata_i(hw_wdata),
310 .hw_wready_o(hw_wready),
Timothy Chenff4a7702020-10-27 15:08:53 -0700311
312 // hardware interface does not talk to prog_fifo
313
314 // muxed interface to rd_ctrl / erase_ctrl
315 .muxed_ctrl_o(muxed_ctrl),
316 .muxed_addr_o(muxed_addr),
317 .prog_ack_i(prog_done),
318 .prog_err_i(prog_err),
319 .rd_ack_i(rd_done),
320 .rd_err_i(rd_err),
321 .erase_ack_i(erase_done),
322 .erase_err_i(erase_err),
323
324 // muxed interface to rd_fifo
325 .rd_fifo_rvalid_i(rd_fifo_rvalid),
326 .rd_fifo_rready_o(rd_fifo_rready),
327
328 // muxed interface to prog_fifo
329 .prog_fifo_wvalid_o(prog_fifo_wvalid),
Timothy Chend39402a2020-12-15 20:34:09 -0800330 .prog_fifo_wdata_o(prog_fifo_wdata),
Timothy Chenff4a7702020-10-27 15:08:53 -0700331 .prog_fifo_wready_i(prog_fifo_wready),
332
333 // flash phy initilization ongoing
334 .flash_phy_busy_i(flash_phy_busy),
335
336 // clear fifos
337 .fifo_clr_o(fifo_clr),
338
339 // phase indication
340 .phase_o(phase),
341
342 // indication that sw has been selected
Timothy Chenaeffadc2020-12-11 15:03:07 -0800343 .sel_o(if_sel)
Timothy Chenff4a7702020-10-27 15:08:53 -0700344 );
345
346 assign op_start = muxed_ctrl.start.q;
347 assign op_num_words = muxed_ctrl.num.q;
348 assign op_erase_type = flash_erase_e'(muxed_ctrl.erase_sel.q);
349 assign op_prog_type = flash_prog_e'(muxed_ctrl.prog_sel.q);
350 assign op_addr = muxed_addr[BusByteWidth +: BusAddrW];
351 assign op_type = flash_op_e'(muxed_ctrl.op.q);
352 assign op_part = flash_part_e'(muxed_ctrl.partition_sel.q);
353 assign op_info_sel = muxed_ctrl.info_sel.q;
354 assign rd_op = op_type == FlashOpRead;
355 assign prog_op = op_type == FlashOpProgram;
356 assign erase_op = op_type == FlashOpErase;
357 assign sw_sel = if_sel == SwSel;
358
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800359 // software privilege to creator seed
Cindy Chen39b14342021-01-29 16:25:24 -0800360 assign creator_seed_priv = lc_creator_seed_sw_rw_en[0] == lc_ctrl_pkg::On;
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800361
362 // software privilege to owner seed
Cindy Chen39b14342021-01-29 16:25:24 -0800363 assign owner_seed_priv = lc_owner_seed_sw_rw_en[0] == lc_ctrl_pkg::On;
Timothy Chen99f3e3a2020-12-09 18:30:19 -0800364
Timothy Chenff4a7702020-10-27 15:08:53 -0700365 // hardware interface
Timothy Chenf52a4612020-12-04 20:37:49 -0800366 flash_ctrl_lcmgr #(
367 .RndCnstAddrKey(RndCnstAddrKey),
368 .RndCnstDataKey(RndCnstDataKey)
369 ) u_flash_hw_if (
Timothy Chenff4a7702020-10-27 15:08:53 -0700370 .clk_i,
371 .rst_ni,
Timothy Chenf52a4612020-12-04 20:37:49 -0800372 .clk_otp_i,
373 .rst_otp_ni,
Timothy Chenff4a7702020-10-27 15:08:53 -0700374
375 .init_i(pwrmgr_i.flash_init),
376 .init_done_o(pwrmgr_o.flash_done),
Cindy Chen39b14342021-01-29 16:25:24 -0800377 .provision_en_i(lc_seed_hw_rd_en[0] == lc_ctrl_pkg::On),
Timothy Chenff4a7702020-10-27 15:08:53 -0700378
379 // interface to ctrl arb control ports
380 .ctrl_o(hw_ctrl),
381 .req_o(hw_req),
382 .addr_o(hw_addr),
383 .done_i(hw_done),
384 .err_i(hw_err),
385
386 // interface to ctrl_arb data ports
387 .rready_o(hw_rready),
388 .rvalid_i(hw_rvalid),
Timothy Chend39402a2020-12-15 20:34:09 -0800389 .wready_i(hw_wready),
390 .wvalid_o(hw_wvalid),
391 .wdata_o(hw_wdata),
Timothy Chenff4a7702020-10-27 15:08:53 -0700392
393 // direct form rd_fifo
394 .rdata_i(rd_fifo_rdata),
395
396 // external rma request
Timothy Chend39402a2020-12-15 20:34:09 -0800397 .rma_req_i,
398 .rma_ack_o,
Timothy Chenff4a7702020-10-27 15:08:53 -0700399
Timothy Chenff4a7702020-10-27 15:08:53 -0700400 // outgoing seeds
401 .seeds_o(keymgr_o.seeds),
402 .seed_err_o(), // TBD hook-up to Err code register
403
404 // phase indication
405 .phase_o(hw_phase),
406
Timothy Chen6b241b32020-11-13 15:15:45 -0800407 // phy read buffer enable
408 .rd_buf_en_o(flash_o.rd_buf_en),
409
Timothy Chenf52a4612020-12-04 20:37:49 -0800410 // connection to otp
411 .otp_key_req_o(otp_o),
412 .otp_key_rsp_i(otp_i),
413 .addr_key_o(addr_key),
414 .data_key_o(data_key),
415
Timothy Chenaeffadc2020-12-11 15:03:07 -0800416 // entropy interface
Timothy Chend39402a2020-12-15 20:34:09 -0800417 .edn_req_o(lfsr_seed_en),
418 .edn_ack_i(1'b1),
Timothy Chenaeffadc2020-12-11 15:03:07 -0800419 .lfsr_en_o(lfsr_en),
420 .rand_i(rand_val),
421
Timothy Chenff4a7702020-10-27 15:08:53 -0700422 // init ongoing
423 .init_busy_o(ctrl_init_busy)
424 );
425
426 // Program FIFO
427 // Since the program and read FIFOs are never used at the same time, it should really be one
428 // FIFO with muxed inputs and outputs. This should be addressed once the flash integration
429 // strategy has been identified
430 assign prog_op_valid = op_start & prog_op;
431
432 tlul_adapter_sram #(
433 .SramAw(1), //address unused
434 .SramDw(BusWidth),
435 .ByteAccess(0), //flash may not support byte access
436 .ErrOnRead(1) //reads not supported
437 ) u_to_prog_fifo (
438 .clk_i,
439 .rst_ni,
Timothy Chen1a9a60f2021-02-10 18:04:39 -0800440 .tl_i (tl_win_h2d[0]),
441 .tl_o (tl_win_d2h[0]),
442 .en_ifetch_i (tlul_pkg::InstrDis),
443 .req_o (sw_wvalid),
444 .gnt_i (sw_wready),
445 .we_o (sw_wen),
446 .addr_o (),
447 .wmask_o (),
448 .wdata_o (sw_wdata),
449 .rdata_i (BusWidth'(0)),
450 .rvalid_i (1'b0),
451 .rerror_i (2'b0)
Timothy Chenff4a7702020-10-27 15:08:53 -0700452 );
453
454 prim_fifo_sync #(
455 .Width(BusWidth),
456 .Depth(FifoDepth)
457 ) u_prog_fifo (
458 .clk_i,
459 .rst_ni,
460 .clr_i (reg2hw.fifo_rst.q | fifo_clr),
461 .wvalid_i(prog_fifo_wvalid & prog_op_valid),
462 .wready_o(prog_fifo_wready),
463 .wdata_i (prog_fifo_wdata),
464 .depth_o (prog_fifo_depth),
Philipp Wagner7858f3d2021-02-01 16:38:13 +0000465 .full_o (),
Timothy Chenff4a7702020-10-27 15:08:53 -0700466 .rvalid_o(prog_fifo_rvalid),
467 .rready_i(prog_fifo_ren),
468 .rdata_o (prog_fifo_rdata)
469 );
470
471 // Program handler is consumer of prog_fifo
Timothy Chenf52a4612020-12-04 20:37:49 -0800472 logic [1:0] prog_type_en;
473 assign prog_type_en[FlashProgNormal] = flash_i.prog_type_avail[FlashProgNormal] &
474 reg2hw.prog_type_en.normal.q;
475 assign prog_type_en[FlashProgRepair] = flash_i.prog_type_avail[FlashProgRepair] &
476 reg2hw.prog_type_en.repair.q;
Timothy Chenff4a7702020-10-27 15:08:53 -0700477 flash_ctrl_prog u_flash_ctrl_prog (
478 .clk_i,
479 .rst_ni,
480
481 // Control interface
482 .op_start_i (prog_op_valid),
483 .op_num_words_i (op_num_words),
484 .op_done_o (prog_done),
485 .op_err_o (prog_err),
486 .op_addr_i (op_addr),
487 .op_type_i (op_prog_type),
Timothy Chenf52a4612020-12-04 20:37:49 -0800488 .type_avail_i (prog_type_en),
Timothy Chenff4a7702020-10-27 15:08:53 -0700489
490 // FIFO Interface
491 .data_i (prog_fifo_rdata),
492 .data_rdy_i (prog_fifo_rvalid),
493 .data_rd_o (prog_fifo_ren),
494
495 // Flash Macro Interface
496 .flash_req_o (prog_flash_req),
497 .flash_addr_o (prog_flash_addr),
498 .flash_ovfl_o (prog_flash_ovfl),
499 .flash_data_o (flash_prog_data),
500 .flash_last_o (flash_prog_last),
501 .flash_type_o (flash_prog_type),
502 .flash_done_i (flash_prog_done),
503 .flash_error_i (flash_mp_error)
504 );
505
506 always_ff @(posedge clk_i or negedge rst_ni) begin
507 if (!rst_ni) begin
508 adapter_rvalid <= 1'b0;
509 end else begin
510 adapter_rvalid <= rd_fifo_ren && sw_rvalid;
511 end
512 end
513
514 // tlul adapter represents software's access interface to flash
515 tlul_adapter_sram #(
516 .SramAw(1), //address unused
517 .SramDw(BusWidth),
518 .ByteAccess(0), //flash may not support byte access
519 .ErrOnWrite(1) //writes not supported
520 ) u_to_rd_fifo (
521 .clk_i,
522 .rst_ni,
Timothy Chen1a9a60f2021-02-10 18:04:39 -0800523 .tl_i (tl_win_h2d[1]),
524 .tl_o (tl_win_d2h[1]),
525 .en_ifetch_i (tlul_pkg::InstrDis),
526 .req_o (rd_fifo_ren),
527 .gnt_i (rd_fifo_rvalid),
528 .we_o (),
529 .addr_o (),
530 .wmask_o (),
531 .wdata_o (),
532 .rdata_i (rd_fifo_rdata),
533 .rvalid_i (adapter_rvalid),
534 .rerror_i (2'b0)
Timothy Chenff4a7702020-10-27 15:08:53 -0700535 );
536
537 prim_fifo_sync #(
538 .Width(BusWidth),
539 .Depth(FifoDepth)
540 ) u_rd_fifo (
541 .clk_i,
542 .rst_ni,
543 .clr_i (reg2hw.fifo_rst.q | fifo_clr),
544 .wvalid_i(rd_fifo_wen),
545 .wready_o(rd_fifo_wready),
546 .wdata_i (rd_fifo_wdata),
Timothy Chen71d98f82020-12-17 17:17:25 -0800547 .full_o (rd_fifo_full),
Timothy Chenff4a7702020-10-27 15:08:53 -0700548 .depth_o (rd_fifo_depth),
549 .rvalid_o(rd_fifo_rvalid),
550 .rready_i(rd_fifo_rready),
551 .rdata_o (rd_fifo_rdata)
552 );
553
554 // Read handler is consumer of rd_fifo
555 flash_ctrl_rd u_flash_ctrl_rd (
556 .clk_i,
557 .rst_ni,
558
559 // To arbiter Interface
560 .op_start_i (op_start & rd_op),
561 .op_num_words_i (op_num_words),
562 .op_done_o (rd_done),
563 .op_err_o (rd_err),
564 .op_addr_i (op_addr),
565
566 // FIFO Interface
567 .data_rdy_i (rd_fifo_wready),
568 .data_o (rd_fifo_wdata),
569 .data_wr_o (rd_fifo_wen),
570
571 // Flash Macro Interface
572 .flash_req_o (rd_flash_req),
573 .flash_addr_o (rd_flash_addr),
574 .flash_ovfl_o (rd_flash_ovfl),
575 .flash_data_i (flash_rd_data),
576 .flash_done_i (flash_rd_done),
577 .flash_error_i (flash_mp_error | flash_rd_err)
578 );
579
580 // Erase handler does not consume fifo
581 flash_ctrl_erase u_flash_ctrl_erase (
582 // Software Interface
583 .op_start_i (op_start & erase_op),
584 .op_type_i (op_erase_type),
585 .op_done_o (erase_done),
586 .op_err_o (erase_err),
587 .op_addr_i (op_addr),
588
589 // Flash Macro Interface
590 .flash_req_o (erase_flash_req),
591 .flash_addr_o (erase_flash_addr),
592 .flash_op_o (erase_flash_type),
593 .flash_done_i (flash_erase_done),
594 .flash_error_i (flash_mp_error)
595 );
596
597 // Final muxing to flash macro module
598 always_comb begin
599 unique case (op_type)
600 FlashOpRead: begin
601 flash_req = rd_flash_req;
602 flash_addr = rd_flash_addr;
603 end
604 FlashOpProgram: begin
605 flash_req = prog_flash_req;
606 flash_addr = prog_flash_addr;
607 end
608 FlashOpErase: begin
609 flash_req = erase_flash_req;
610 flash_addr = erase_flash_addr;
611 end
612 default: begin
613 flash_req = 1'b0;
614 flash_addr = '0;
615 end
616 endcase // unique case (op_type)
617 end
618
619 //////////////////////////////////////
Timothy Chend5323562020-12-02 16:10:44 -0800620 // Data partition properties configuration
Timothy Chenff4a7702020-10-27 15:08:53 -0700621 //////////////////////////////////////
622 // extra region is the default region
623 mp_region_cfg_t [MpRegions:0] region_cfgs;
624 assign region_cfgs[MpRegions-1:0] = reg2hw.mp_region_cfg[MpRegions-1:0];
625
626 //default region
627 assign region_cfgs[MpRegions].base.q = '0;
628 assign region_cfgs[MpRegions].size.q = NumBanks * PagesPerBank;
629 assign region_cfgs[MpRegions].en.q = 1'b1;
630 assign region_cfgs[MpRegions].rd_en.q = reg2hw.default_region.rd_en.q;
631 assign region_cfgs[MpRegions].prog_en.q = reg2hw.default_region.prog_en.q;
632 assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
633 assign region_cfgs[MpRegions].scramble_en.q = reg2hw.default_region.scramble_en.q;
Timothy Chena2db9332020-11-13 18:47:54 -0800634 assign region_cfgs[MpRegions].ecc_en.q = reg2hw.default_region.ecc_en.q;
Timothy Chend5323562020-12-02 16:10:44 -0800635 assign region_cfgs[MpRegions].he_en.q = reg2hw.default_region.he_en.q;
Timothy Chenff4a7702020-10-27 15:08:53 -0700636
637 //////////////////////////////////////
Timothy Chend5323562020-12-02 16:10:44 -0800638 // Info partition properties configuration
Timothy Chenff4a7702020-10-27 15:08:53 -0700639 //////////////////////////////////////
640 info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] reg2hw_info_page_cfgs;
641 info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
Timothy Chene97e0b82020-12-11 17:18:43 -0800642 localparam int InfoBits = $bits(info_page_cfg_t) * InfosPerBank;
Timothy Chenff4a7702020-10-27 15:08:53 -0700643
644 // transform from reg output to structure
Timothy Chene97e0b82020-12-11 17:18:43 -0800645 // Not all types have the maximum number of banks, so those are packed to 0
Timothy Chenff4a7702020-10-27 15:08:53 -0700646 % for bank in range(cfg['banks']):
647 % for idx in range(cfg['info_types']):
Timothy Chene97e0b82020-12-11 17:18:43 -0800648 assign reg2hw_info_page_cfgs[${bank}][${idx}] = InfoBits'(reg2hw.bank${bank}_info${idx}_page_cfg);
Timothy Chenff4a7702020-10-27 15:08:53 -0700649 % endfor
650 % endfor
651
652 // qualify reg2hw settings with creator / owner privileges
653 for(genvar i = 0; i < NumBanks; i++) begin : gen_info_priv_bank
654 for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_priv_type
655 flash_ctrl_info_cfg # (
656 .Bank(i),
657 .InfoSel(j)
658 ) u_info_cfg (
659 .cfgs_i(reg2hw_info_page_cfgs[i][j]),
660 .creator_seed_priv_i(creator_seed_priv),
661 .owner_seed_priv_i(owner_seed_priv),
Cindy Chen39b14342021-01-29 16:25:24 -0800662 .iso_flash_wr_en_i(lc_iso_part_sw_wr_en[0] == lc_ctrl_pkg::On),
663 .iso_flash_rd_en_i(lc_iso_part_sw_rd_en[0] == lc_ctrl_pkg::On),
Timothy Chenff4a7702020-10-27 15:08:53 -0700664 .cfgs_o(info_page_cfgs[i][j])
665 );
666 end
667 end
668
669 //////////////////////////////////////
Timothy Chend5323562020-12-02 16:10:44 -0800670 // flash memory properties
Timothy Chenff4a7702020-10-27 15:08:53 -0700671 //////////////////////////////////////
672 // direct assignment since prog/rd/erase_ctrl do not make use of op_part
673 flash_part_e flash_part_sel;
674 logic [InfoTypesWidth-1:0] flash_info_sel;
675 assign flash_part_sel = op_part;
676 assign flash_info_sel = op_info_sel;
677
Timothy Chen7d051eb2020-12-11 14:06:43 -0800678 // tie off hardware clear path
679 assign hw2reg.erase_suspend.d = 1'b0;
680
Timothy Chend5323562020-12-02 16:10:44 -0800681 // Flash memory Properties
682 // Memory property is page based and thus should use phy addressing
Timothy Chenff4a7702020-10-27 15:08:53 -0700683 // This should move to flash_phy long term
684 flash_mp u_flash_mp (
685 .clk_i,
686 .rst_ni,
687
688 // arbiter interface selection
689 .if_sel_i(if_sel),
690
691 // sw configuration for data partition
692 .region_cfgs_i(region_cfgs),
693 .bank_cfgs_i(reg2hw.mp_bank_cfg),
694
695 // sw configuration for info partition
696 .info_page_cfgs_i(info_page_cfgs),
697
698 // read / prog / erase controls
699 .req_i(flash_req),
700 .phase_i(phase),
701 .req_addr_i(flash_addr[BusAddrW-1 -: AllPagesW]),
702 .req_part_i(flash_part_sel),
703 .info_sel_i(flash_info_sel),
704 .addr_ovfl_i(rd_flash_ovfl | prog_flash_ovfl),
705 .rd_i(rd_op),
706 .prog_i(prog_op),
707 .pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
708 .bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
Timothy Chen7d051eb2020-12-11 14:06:43 -0800709 .erase_suspend_i(reg2hw.erase_suspend),
710 .erase_suspend_done_o(hw2reg.erase_suspend.de),
Timothy Chenff4a7702020-10-27 15:08:53 -0700711 .rd_done_o(flash_rd_done),
712 .prog_done_o(flash_prog_done),
713 .erase_done_o(flash_erase_done),
714 .error_o(flash_mp_error),
715 .err_addr_o(err_addr),
716
717 // flash phy interface
718 .req_o(flash_o.req),
719 .scramble_en_o(flash_o.scramble_en),
Timothy Chena2db9332020-11-13 18:47:54 -0800720 .ecc_en_o(flash_o.ecc_en),
Timothy Chend5323562020-12-02 16:10:44 -0800721 .he_en_o(flash_o.he_en),
Timothy Chenff4a7702020-10-27 15:08:53 -0700722 .rd_o(flash_o.rd),
723 .prog_o(flash_o.prog),
724 .pg_erase_o(flash_o.pg_erase),
725 .bk_erase_o(flash_o.bk_erase),
Timothy Chen7d051eb2020-12-11 14:06:43 -0800726 .erase_suspend_o(flash_o.erase_suspend),
Timothy Chenff4a7702020-10-27 15:08:53 -0700727 .rd_done_i(flash_i.rd_done),
728 .prog_done_i(flash_i.prog_done),
729 .erase_done_i(flash_i.erase_done)
730 );
731
732
733 // software interface feedback
734 // most values (other than flash_phy_busy) should only update when software operations
735 // are actually selected
736 assign hw2reg.op_status.done.d = 1'b1;
737 assign hw2reg.op_status.done.de = sw_ctrl_done;
738 assign hw2reg.op_status.err.d = 1'b1;
739 assign hw2reg.op_status.err.de = sw_ctrl_err;
Timothy Chen71d98f82020-12-17 17:17:25 -0800740 assign hw2reg.status.rd_full.d = rd_fifo_full;
Timothy Chenff4a7702020-10-27 15:08:53 -0700741 assign hw2reg.status.rd_full.de = sw_sel;
742 assign hw2reg.status.rd_empty.d = ~rd_fifo_rvalid;
743 assign hw2reg.status.rd_empty.de = sw_sel;
744 assign hw2reg.status.prog_full.d = ~prog_fifo_wready;
745 assign hw2reg.status.prog_full.de = sw_sel;
746 assign hw2reg.status.prog_empty.d = ~prog_fifo_rvalid;
747 assign hw2reg.status.prog_empty.de = sw_sel;
748 assign hw2reg.status.init_wip.d = flash_phy_busy | ctrl_init_busy;
749 assign hw2reg.status.init_wip.de = 1'b1;
Timothy Chenff4a7702020-10-27 15:08:53 -0700750 assign hw2reg.control.start.d = 1'b0;
751 assign hw2reg.control.start.de = sw_ctrl_done;
752 // if software operation selected, based on transaction start
753 // if software operation not selected, software is free to change contents
754 assign hw2reg.ctrl_regwen.d = sw_sel ? !op_start : 1'b1;
755
756 // phy status
757 assign hw2reg.phy_status.init_wip.d = flash_phy_busy;
758 assign hw2reg.phy_status.init_wip.de = 1'b1;
759 assign hw2reg.phy_status.prog_normal_avail.d = flash_i.prog_type_avail[FlashProgNormal];
760 assign hw2reg.phy_status.prog_normal_avail.de = 1'b1;
761 assign hw2reg.phy_status.prog_repair_avail.d = flash_i.prog_type_avail[FlashProgRepair];
762 assign hw2reg.phy_status.prog_repair_avail.de = 1'b1;
763
764 // Flash Interface
765 assign flash_o.addr = flash_addr;
766 assign flash_o.part = flash_part_sel;
Timothy Chena0a550a2020-12-03 13:11:03 -0800767 assign flash_o.info_sel = flash_info_sel;
Timothy Chenff4a7702020-10-27 15:08:53 -0700768 assign flash_o.prog_type = flash_prog_type;
769 assign flash_o.prog_data = flash_prog_data;
770 assign flash_o.prog_last = flash_prog_last;
771 assign flash_o.region_cfgs = region_cfgs;
Timothy Chenf52a4612020-12-04 20:37:49 -0800772 assign flash_o.addr_key = addr_key;
773 assign flash_o.data_key = data_key;
Timothy Chen6e495182020-12-28 16:16:35 -0800774 assign flash_o.tl_flash_c2p = tl_win_h2d[2];
Timothy Chen16741102021-01-15 17:32:13 -0800775 assign flash_o.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q;
776 assign flash_o.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q;
Timothy Chend8fded82021-02-22 11:32:55 -0800777 assign flash_o.jtag_req.tck = cio_tck_i;
778 assign flash_o.jtag_req.tms = cio_tms_i;
779 assign flash_o.jtag_req.tdi = cio_tdi_i;
780 assign flash_o.jtag_req.trst_n = '0;
781 assign cio_tdo_o = flash_i.jtag_rsp.tdo;
782 assign cio_tdo_en_o = flash_i.jtag_rsp.tdo_oe;
Timothy Chenff4a7702020-10-27 15:08:53 -0700783 assign flash_rd_err = flash_i.rd_err;
784 assign flash_rd_data = flash_i.rd_data;
785 assign flash_phy_busy = flash_i.init_busy;
786
Timothy Chend8fded82021-02-22 11:32:55 -0800787
Timothy Chenff4a7702020-10-27 15:08:53 -0700788 // Interface to pwrmgr
789 // flash is not idle as long as there is a stateful operation ongoing
790 logic flash_idle_d;
791 assign flash_idle_d = ~(flash_o.req &
792 (flash_o.prog | flash_o.pg_erase | flash_o.bk_erase));
793
794 prim_flop #(
795 .Width(1),
796 .ResetValue(1'b1)
797 ) u_reg_idle (
798 .clk_i,
799 .rst_ni,
800 .d_i(flash_idle_d),
801 .q_o(pwrmgr_o.flash_idle)
802 );
803
Timothy Chen16741102021-01-15 17:32:13 -0800804 //////////////////////////////////////
805 // Alert senders
806 //////////////////////////////////////
Timothy Chenff4a7702020-10-27 15:08:53 -0700807
Timothy Chen16741102021-01-15 17:32:13 -0800808 logic [NumAlerts-1:0] alert_srcs;
809 logic [NumAlerts-1:0] alert_tests;
810
Timothy Chen5302fff2021-01-22 14:36:54 -0800811 logic recov_err;
812 assign recov_err = flash_i.flash_alert_p | ~flash_i.flash_alert_n;
Timothy Chen16741102021-01-15 17:32:13 -0800813
814 logic recov_mp_err;
815 assign recov_mp_err = flash_mp_error;
816
817 logic recov_ecc_err;
818 assign recov_ecc_err = |flash_i.ecc_single_err | |flash_i.ecc_multi_err;
819
820 assign alert_srcs = { recov_ecc_err,
821 recov_mp_err,
Timothy Chen5302fff2021-01-22 14:36:54 -0800822 recov_err
Timothy Chen16741102021-01-15 17:32:13 -0800823 };
824
825 assign alert_tests = { reg2hw.alert_test.recov_ecc_err.q & reg2hw.alert_test.recov_ecc_err.qe,
826 reg2hw.alert_test.recov_mp_err.q & reg2hw.alert_test.recov_mp_err.qe,
Timothy Chen5302fff2021-01-22 14:36:54 -0800827 reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
Timothy Chen16741102021-01-15 17:32:13 -0800828 };
829
830 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
831 prim_alert_sender #(
832 .AsyncOn(AlertAsyncOn)
833 ) u_alert_sender (
834 .clk_i,
835 .rst_ni,
Timothy Chen06f78312021-01-20 18:43:27 -0800836 .alert_req_i(alert_srcs[i]),
837 .alert_test_i(alert_tests[i]),
Timothy Chen16741102021-01-15 17:32:13 -0800838 .alert_ack_o(),
Timothy Chen06f78312021-01-20 18:43:27 -0800839 .alert_state_o(),
Timothy Chen16741102021-01-15 17:32:13 -0800840 .alert_rx_i(alert_rx_i[i]),
841 .alert_tx_o(alert_tx_o[i])
842 );
843 end
844
845
846 //////////////////////////////////////
847 // Errors and Interrupts
848 //////////////////////////////////////
849
850 assign hw2reg.err_code.mp_err.d = 1'b1;
851 assign hw2reg.err_code.ecc_single_err.d = 1'b1;
852 assign hw2reg.err_code.ecc_multi_err.d = 1'b1;
853 assign hw2reg.err_code.flash_err.d = 1'b1;
854 assign hw2reg.err_code.flash_alert.d = 1'b1;
855 assign hw2reg.err_code.mp_err.de = flash_mp_error;
856 assign hw2reg.err_code.ecc_single_err.de = |flash_i.ecc_single_err;
857 assign hw2reg.err_code.ecc_multi_err.de = |flash_i.ecc_multi_err;
858 assign hw2reg.err_code.flash_err.de = flash_i.flash_err;
859 assign hw2reg.err_code.flash_alert.de = flash_i.flash_alert_p | ~flash_i.flash_alert_n;
860 assign hw2reg.err_addr.d = err_addr;
861 assign hw2reg.err_addr.de = flash_mp_error;
862
863 for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_err_cons
864 assign hw2reg.ecc_err_addr[bank].d = {flash_i.ecc_addr[bank], {BusByteWidth{1'b0}}};
865 assign hw2reg.ecc_err_addr[bank].de = flash_i.ecc_single_err[bank] |
866 flash_i.ecc_multi_err[bank];
867 end
868
Timothy Chenff4a7702020-10-27 15:08:53 -0700869 // Generate edge triggered signals for sources that are level
870 logic [3:0] intr_src;
871 logic [3:0] intr_src_q;
872 logic [3:0] intr_assert;
873
874 assign intr_src = { ~prog_fifo_rvalid,
875 reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
Timothy Chen71d98f82020-12-17 17:17:25 -0800876 rd_fifo_full,
Timothy Chenff4a7702020-10-27 15:08:53 -0700877 reg2hw.fifo_lvl.rd.q == rd_fifo_depth
878 };
879
880 always_ff @(posedge clk_i or negedge rst_ni) begin
881 if (!rst_ni) begin
882 intr_src_q <= 4'h8; //prog_fifo is empty by default
883 end else if (sw_sel) begin
884 intr_src_q <= intr_src;
885 end
886 end
887
888 assign intr_assert = ~intr_src_q & intr_src;
889
890
891 assign intr_prog_empty_o = reg2hw.intr_enable.prog_empty.q & reg2hw.intr_state.prog_empty.q;
892 assign intr_prog_lvl_o = reg2hw.intr_enable.prog_lvl.q & reg2hw.intr_state.prog_lvl.q;
893 assign intr_rd_full_o = reg2hw.intr_enable.rd_full.q & reg2hw.intr_state.rd_full.q;
894 assign intr_rd_lvl_o = reg2hw.intr_enable.rd_lvl.q & reg2hw.intr_state.rd_lvl.q;
895 assign intr_op_done_o = reg2hw.intr_enable.op_done.q & reg2hw.intr_state.op_done.q;
Timothy Chenff4a7702020-10-27 15:08:53 -0700896
897 assign hw2reg.intr_state.prog_empty.d = 1'b1;
898 assign hw2reg.intr_state.prog_empty.de = intr_assert[3] |
899 (reg2hw.intr_test.prog_empty.qe &
900 reg2hw.intr_test.prog_empty.q);
901
902 assign hw2reg.intr_state.prog_lvl.d = 1'b1;
903 assign hw2reg.intr_state.prog_lvl.de = intr_assert[2] |
904 (reg2hw.intr_test.prog_lvl.qe &
905 reg2hw.intr_test.prog_lvl.q);
906
907 assign hw2reg.intr_state.rd_full.d = 1'b1;
908 assign hw2reg.intr_state.rd_full.de = intr_assert[1] |
909 (reg2hw.intr_test.rd_full.qe &
910 reg2hw.intr_test.rd_full.q);
911
912 assign hw2reg.intr_state.rd_lvl.d = 1'b1;
913 assign hw2reg.intr_state.rd_lvl.de = intr_assert[0] |
914 (reg2hw.intr_test.rd_lvl.qe &
915 reg2hw.intr_test.rd_lvl.q);
916
917
918 assign hw2reg.intr_state.op_done.d = 1'b1;
919 assign hw2reg.intr_state.op_done.de = sw_ctrl_done |
920 (reg2hw.intr_test.op_done.qe &
921 reg2hw.intr_test.op_done.q);
922
Timothy Chenff4a7702020-10-27 15:08:53 -0700923
924 // Unused bits
925 logic [BusByteWidth-1:0] unused_byte_sel;
926 logic [top_pkg::TL_AW-1-BusAddrW:0] unused_higher_addr_bits;
927 logic [top_pkg::TL_AW-1:0] unused_scratch;
928
Timothy Chenff4a7702020-10-27 15:08:53 -0700929 // Unused signals
930 assign unused_byte_sel = muxed_addr[BusByteWidth-1:0];
931 assign unused_higher_addr_bits = muxed_addr[top_pkg::TL_AW-1:BusAddrW];
932 assign unused_scratch = reg2hw.scratch;
933
934
935 // Assertions
936 `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid )
937 `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready )
938 `ASSERT_KNOWN(FlashKnownO_A, {flash_o.req, flash_o.rd, flash_o.prog, flash_o.pg_erase,
939 flash_o.bk_erase})
940 `ASSERT_KNOWN_IF(FlashAddrKnown_A, flash_o.addr, flash_o.req)
941 `ASSERT_KNOWN_IF(FlashProgKnown_A, flash_o.prog_data, flash_o.prog & flash_o.req)
942 `ASSERT_KNOWN(IntrProgEmptyKnownO_A, intr_prog_empty_o)
943 `ASSERT_KNOWN(IntrProgLvlKnownO_A, intr_prog_lvl_o )
944 `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o )
945 `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o )
946 `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o )
Timothy Chenff4a7702020-10-27 15:08:53 -0700947
948endmodule