blob: e9de226afb2e7915360f0f1e27b0ba89b3b7705d [file] [log] [blame]
Timothy Chenff4a7702020-10-27 15:08:53 -07001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Flash Controller Module
6//
7//
8
9`include "prim_assert.sv"
10
11module flash_ctrl import flash_ctrl_pkg::*; (
12 input clk_i,
13 input rst_ni,
14
15 // Bus Interface
16 input tlul_pkg::tl_h2d_t tl_i,
17 output tlul_pkg::tl_d2h_t tl_o,
18
19 // Flash Interface
20 input flash_rsp_t flash_i,
21 output flash_req_t flash_o,
22
23 // otp/lc/pwrmgr/keymgr Interface
24 input otp_flash_t otp_i,
25 input lc_flash_req_t lc_i,
26 output lc_flash_rsp_t lc_o,
27 input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
28 output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
29 input edn_entropy_t edn_i,
30 output keymgr_flash_t keymgr_o,
31
32 // Interrupts
33 output logic intr_prog_empty_o, // Program fifo is empty
34 output logic intr_prog_lvl_o, // Program fifo is empty
35 output logic intr_rd_full_o, // Read fifo is full
36 output logic intr_rd_lvl_o, // Read fifo is full
37 output logic intr_op_done_o, // Requested flash operation (wr/erase) done
38 output logic intr_op_error_o // Requested flash operation (wr/erase) done
39);
40
41 import flash_ctrl_reg_pkg::*;
42
43 flash_ctrl_reg2hw_t reg2hw;
44 flash_ctrl_hw2reg_t hw2reg;
45
46 tlul_pkg::tl_h2d_t tl_fifo_h2d [2];
47 tlul_pkg::tl_d2h_t tl_fifo_d2h [2];
48
49 // Register module
50 flash_ctrl_reg_top u_reg (
51 .clk_i,
52 .rst_ni,
53
54 .tl_i,
55 .tl_o,
56
57 .tl_win_o (tl_fifo_h2d),
58 .tl_win_i (tl_fifo_d2h),
59
60 .reg2hw,
61 .hw2reg,
62
63 .devmode_i (1'b1)
64 );
65
66 // FIFO Connections
67 logic prog_fifo_wvalid;
68 logic prog_fifo_wready;
69 logic prog_fifo_rvalid;
70 logic prog_fifo_ren;
71 logic [BusWidth-1:0] prog_fifo_wdata;
72 logic [BusWidth-1:0] prog_fifo_rdata;
73 logic [FifoDepthW-1:0] prog_fifo_depth;
74 logic rd_fifo_wready;
75 logic rd_fifo_rvalid;
76 logic rd_fifo_rready;
77 logic rd_fifo_wen;
78 logic rd_fifo_ren;
79 logic [BusWidth-1:0] rd_fifo_wdata;
80 logic [BusWidth-1:0] rd_fifo_rdata;
81 logic [FifoDepthW-1:0] rd_fifo_depth;
82
83 // Program Control Connections
84 logic prog_flash_req;
85 logic prog_flash_ovfl;
86 logic [BusAddrW-1:0] prog_flash_addr;
87 logic prog_op_valid;
88
89 // Read Control Connections
90 logic rd_flash_req;
91 logic rd_flash_ovfl;
92 logic [BusAddrW-1:0] rd_flash_addr;
93
94 // Erase Control Connections
95 logic erase_flash_req;
96 logic [BusAddrW-1:0] erase_flash_addr;
97 flash_erase_e erase_flash_type;
98
99 // Done / Error signaling from ctrl modules
100 logic prog_done, rd_done, erase_done;
101 logic prog_err, rd_err, erase_err;
102
103 // Flash Memory Protection Connections
104 logic [BusAddrW-1:0] flash_addr;
105 logic flash_req;
106 logic flash_rd_done, flash_prog_done, flash_erase_done;
107 logic flash_mp_error;
108 logic [BusWidth-1:0] flash_prog_data;
109 logic flash_prog_last;
110 flash_prog_e flash_prog_type;
111 logic [BusWidth-1:0] flash_rd_data;
112 logic flash_rd_err;
113 logic flash_phy_busy;
114 logic rd_op;
115 logic prog_op;
116 logic erase_op;
117 logic [AllPagesW-1:0] err_addr;
118 flash_lcmgr_phase_e phase;
119
120 // Flash control arbitration connections to hardware interface
121 flash_ctrl_reg2hw_control_reg_t hw_ctrl;
122 logic hw_req;
123 logic [top_pkg::TL_AW-1:0] hw_addr;
124 logic hw_done;
125 logic hw_err;
126 logic hw_rvalid;
127 logic hw_rready;
128 flash_sel_e if_sel;
129 logic sw_sel;
130 flash_lcmgr_phase_e hw_phase;
131 logic creator_seed_priv;
132 logic owner_seed_priv;
133
134 // Flash control arbitration connections to software interface
135 logic sw_ctrl_done;
136 logic sw_ctrl_err;
137
138 // Flash control muxed connections
139 flash_ctrl_reg2hw_control_reg_t muxed_ctrl;
140 logic [top_pkg::TL_AW-1:0] muxed_addr;
141 logic op_start;
142 logic [11:0] op_num_words;
143 logic [BusAddrW-1:0] op_addr;
144 flash_op_e op_type;
145 flash_part_e op_part;
146 logic [InfoTypesWidth-1:0] op_info_sel;
147 flash_erase_e op_erase_type;
148 flash_prog_e op_prog_type;
149
150 logic ctrl_init_busy;
151 logic fifo_clr;
152
153 // software tlul to flash control aribration
154 logic sw_rvalid;
155 logic adapter_rvalid;
156 logic sw_wvalid;
157 logic sw_wen;
158 logic sw_wready;
159
160 // lfsr for local entropy usage
161 logic [31:0] rand_val;
162 logic lfsr_en;
163
164 prim_lfsr #(
165 .DefaultSeed(),
166 .EntropyDw(4),
167 .LfsrDw(32),
168 .StateOutDw(32)
169 ) u_lfsr (
170 .clk_i,
171 .rst_ni,
172 .seed_en_i('0),
173 .seed_i('0),
174 .lfsr_en_i(lfsr_en),
175 .entropy_i(edn_i.valid ? edn_i.entropy : '0),
176 .state_o(rand_val)
177 );
178
179 // flash control arbitration between softawre / harware interfaces
180 flash_ctrl_arb u_ctrl_arb (
181 .clk_i,
182 .rst_ni,
183
184 // software interface to rd_ctrl / erase_ctrl
185 .sw_ctrl_i(reg2hw.control),
186 .sw_addr_i(reg2hw.addr.q),
187 .sw_ack_o(sw_ctrl_done),
188 .sw_err_o(sw_ctrl_err),
189
190 // software interface to rd_fifo
191 .sw_rvalid_o(sw_rvalid),
192 .sw_rready_i(adapter_rvalid),
193
194 // software interface to prog_fifo
195 .sw_wvalid_i(sw_wvalid & sw_wen),
196 .sw_wready_o(sw_wready),
197
198 // hardware interface to rd_ctrl / erase_ctrl
199 .hw_req_i(hw_req),
200 .hw_ctrl_i(hw_ctrl),
201
202 // hardware interface indicating operation phase
203 .hw_phase_i(hw_phase),
204
205 // hardware works on word address, however software expects byte address
206 .hw_addr_i(hw_addr),
207 .hw_ack_o(hw_done),
208 .hw_err_o(hw_err),
209
210 // hardware interface to rd_fifo
211 .hw_rvalid_o(hw_rvalid),
212 .hw_rready_i(hw_rready),
213
214 // hardware interface does not talk to prog_fifo
215
216 // muxed interface to rd_ctrl / erase_ctrl
217 .muxed_ctrl_o(muxed_ctrl),
218 .muxed_addr_o(muxed_addr),
219 .prog_ack_i(prog_done),
220 .prog_err_i(prog_err),
221 .rd_ack_i(rd_done),
222 .rd_err_i(rd_err),
223 .erase_ack_i(erase_done),
224 .erase_err_i(erase_err),
225
226 // muxed interface to rd_fifo
227 .rd_fifo_rvalid_i(rd_fifo_rvalid),
228 .rd_fifo_rready_o(rd_fifo_rready),
229
230 // muxed interface to prog_fifo
231 .prog_fifo_wvalid_o(prog_fifo_wvalid),
232 .prog_fifo_wready_i(prog_fifo_wready),
233
234 // flash phy initilization ongoing
235 .flash_phy_busy_i(flash_phy_busy),
236
237 // clear fifos
238 .fifo_clr_o(fifo_clr),
239
240 // phase indication
241 .phase_o(phase),
242
243 // indication that sw has been selected
244 .sel_o(if_sel),
245
246 // enable lfsr
247 .lfsr_en_o(lfsr_en)
248 );
249
250 assign op_start = muxed_ctrl.start.q;
251 assign op_num_words = muxed_ctrl.num.q;
252 assign op_erase_type = flash_erase_e'(muxed_ctrl.erase_sel.q);
253 assign op_prog_type = flash_prog_e'(muxed_ctrl.prog_sel.q);
254 assign op_addr = muxed_addr[BusByteWidth +: BusAddrW];
255 assign op_type = flash_op_e'(muxed_ctrl.op.q);
256 assign op_part = flash_part_e'(muxed_ctrl.partition_sel.q);
257 assign op_info_sel = muxed_ctrl.info_sel.q;
258 assign rd_op = op_type == FlashOpRead;
259 assign prog_op = op_type == FlashOpProgram;
260 assign erase_op = op_type == FlashOpErase;
261 assign sw_sel = if_sel == SwSel;
262
263 // hardware interface
264
265 // software only has privilege to change creator seed when provision enable is set and
266 // before the the seed is set as valid in otp
267 assign creator_seed_priv = lc_i.provision_en & ~otp_i.seed_valid;
268
269 // owner seed is under software control and can be modided whenever provision enable is set
270 assign owner_seed_priv = lc_i.provision_en;
271
272 flash_ctrl_lcmgr u_flash_hw_if (
273 .clk_i,
274 .rst_ni,
275
276 .init_i(pwrmgr_i.flash_init),
277 .init_done_o(pwrmgr_o.flash_done),
278 .provision_en_i(lc_i.provision_en),
279
280 // interface to ctrl arb control ports
281 .ctrl_o(hw_ctrl),
282 .req_o(hw_req),
283 .addr_o(hw_addr),
284 .done_i(hw_done),
285 .err_i(hw_err),
286
287 // interface to ctrl_arb data ports
288 .rready_o(hw_rready),
289 .rvalid_i(hw_rvalid),
290
291 // direct form rd_fifo
292 .rdata_i(rd_fifo_rdata),
293
294 // external rma request
295 .rma_i(lc_i.rma_req),
296 .rma_token_i(lc_i.rma_req_token),
297 .rma_token_o(lc_o.rma_ack_token),
298 .rma_rsp_o(lc_o.rma_ack),
299
300 // random value
301 .rand_i(rand_val),
302
303 // outgoing seeds
304 .seeds_o(keymgr_o.seeds),
305 .seed_err_o(), // TBD hook-up to Err code register
306
307 // phase indication
308 .phase_o(hw_phase),
309
310 // init ongoing
311 .init_busy_o(ctrl_init_busy)
312 );
313
314 // Program FIFO
315 // Since the program and read FIFOs are never used at the same time, it should really be one
316 // FIFO with muxed inputs and outputs. This should be addressed once the flash integration
317 // strategy has been identified
318 assign prog_op_valid = op_start & prog_op;
319
320 tlul_adapter_sram #(
321 .SramAw(1), //address unused
322 .SramDw(BusWidth),
323 .ByteAccess(0), //flash may not support byte access
324 .ErrOnRead(1) //reads not supported
325 ) u_to_prog_fifo (
326 .clk_i,
327 .rst_ni,
328 .tl_i (tl_fifo_h2d[0]),
329 .tl_o (tl_fifo_d2h[0]),
330 .req_o (sw_wvalid),
331 .gnt_i (sw_wready),
332 .we_o (sw_wen),
333 .addr_o (),
334 .wmask_o (),
335 .wdata_o (prog_fifo_wdata),
336 .rdata_i (BusWidth'(0)),
337 .rvalid_i (1'b0),
338 .rerror_i (2'b0)
339 );
340
341 prim_fifo_sync #(
342 .Width(BusWidth),
343 .Depth(FifoDepth)
344 ) u_prog_fifo (
345 .clk_i,
346 .rst_ni,
347 .clr_i (reg2hw.fifo_rst.q | fifo_clr),
348 .wvalid_i(prog_fifo_wvalid & prog_op_valid),
349 .wready_o(prog_fifo_wready),
350 .wdata_i (prog_fifo_wdata),
351 .depth_o (prog_fifo_depth),
352 .rvalid_o(prog_fifo_rvalid),
353 .rready_i(prog_fifo_ren),
354 .rdata_o (prog_fifo_rdata)
355 );
356
357 // Program handler is consumer of prog_fifo
358
359 // OTP control bits can be used to explicitly disable repair
360 logic [ProgTypes-1:0] otp_en;
361 assign otp_en[FlashProgNormal] = 1'b1;
362 assign otp_en[FlashProgRepair] = otp_i.prog_repair_en;
363
364 flash_ctrl_prog u_flash_ctrl_prog (
365 .clk_i,
366 .rst_ni,
367
368 // Control interface
369 .op_start_i (prog_op_valid),
370 .op_num_words_i (op_num_words),
371 .op_done_o (prog_done),
372 .op_err_o (prog_err),
373 .op_addr_i (op_addr),
374 .op_type_i (op_prog_type),
375 .type_avail_i (flash_i.prog_type_avail & otp_en),
376
377 // FIFO Interface
378 .data_i (prog_fifo_rdata),
379 .data_rdy_i (prog_fifo_rvalid),
380 .data_rd_o (prog_fifo_ren),
381
382 // Flash Macro Interface
383 .flash_req_o (prog_flash_req),
384 .flash_addr_o (prog_flash_addr),
385 .flash_ovfl_o (prog_flash_ovfl),
386 .flash_data_o (flash_prog_data),
387 .flash_last_o (flash_prog_last),
388 .flash_type_o (flash_prog_type),
389 .flash_done_i (flash_prog_done),
390 .flash_error_i (flash_mp_error)
391 );
392
393 always_ff @(posedge clk_i or negedge rst_ni) begin
394 if (!rst_ni) begin
395 adapter_rvalid <= 1'b0;
396 end else begin
397 adapter_rvalid <= rd_fifo_ren && sw_rvalid;
398 end
399 end
400
401 // tlul adapter represents software's access interface to flash
402 tlul_adapter_sram #(
403 .SramAw(1), //address unused
404 .SramDw(BusWidth),
405 .ByteAccess(0), //flash may not support byte access
406 .ErrOnWrite(1) //writes not supported
407 ) u_to_rd_fifo (
408 .clk_i,
409 .rst_ni,
410 .tl_i (tl_fifo_h2d[1]),
411 .tl_o (tl_fifo_d2h[1]),
412 .req_o (rd_fifo_ren),
413 .gnt_i (rd_fifo_rvalid),
414 .we_o (),
415 .addr_o (),
416 .wmask_o (),
417 .wdata_o (),
418 .rdata_i (rd_fifo_rdata),
419 .rvalid_i (adapter_rvalid),
420 .rerror_i (2'b0)
421 );
422
423 prim_fifo_sync #(
424 .Width(BusWidth),
425 .Depth(FifoDepth)
426 ) u_rd_fifo (
427 .clk_i,
428 .rst_ni,
429 .clr_i (reg2hw.fifo_rst.q | fifo_clr),
430 .wvalid_i(rd_fifo_wen),
431 .wready_o(rd_fifo_wready),
432 .wdata_i (rd_fifo_wdata),
433 .depth_o (rd_fifo_depth),
434 .rvalid_o(rd_fifo_rvalid),
435 .rready_i(rd_fifo_rready),
436 .rdata_o (rd_fifo_rdata)
437 );
438
439 // Read handler is consumer of rd_fifo
440 flash_ctrl_rd u_flash_ctrl_rd (
441 .clk_i,
442 .rst_ni,
443
444 // To arbiter Interface
445 .op_start_i (op_start & rd_op),
446 .op_num_words_i (op_num_words),
447 .op_done_o (rd_done),
448 .op_err_o (rd_err),
449 .op_addr_i (op_addr),
450
451 // FIFO Interface
452 .data_rdy_i (rd_fifo_wready),
453 .data_o (rd_fifo_wdata),
454 .data_wr_o (rd_fifo_wen),
455
456 // Flash Macro Interface
457 .flash_req_o (rd_flash_req),
458 .flash_addr_o (rd_flash_addr),
459 .flash_ovfl_o (rd_flash_ovfl),
460 .flash_data_i (flash_rd_data),
461 .flash_done_i (flash_rd_done),
462 .flash_error_i (flash_mp_error | flash_rd_err)
463 );
464
465 // Erase handler does not consume fifo
466 flash_ctrl_erase u_flash_ctrl_erase (
467 // Software Interface
468 .op_start_i (op_start & erase_op),
469 .op_type_i (op_erase_type),
470 .op_done_o (erase_done),
471 .op_err_o (erase_err),
472 .op_addr_i (op_addr),
473
474 // Flash Macro Interface
475 .flash_req_o (erase_flash_req),
476 .flash_addr_o (erase_flash_addr),
477 .flash_op_o (erase_flash_type),
478 .flash_done_i (flash_erase_done),
479 .flash_error_i (flash_mp_error)
480 );
481
482 // Final muxing to flash macro module
483 always_comb begin
484 unique case (op_type)
485 FlashOpRead: begin
486 flash_req = rd_flash_req;
487 flash_addr = rd_flash_addr;
488 end
489 FlashOpProgram: begin
490 flash_req = prog_flash_req;
491 flash_addr = prog_flash_addr;
492 end
493 FlashOpErase: begin
494 flash_req = erase_flash_req;
495 flash_addr = erase_flash_addr;
496 end
497 default: begin
498 flash_req = 1'b0;
499 flash_addr = '0;
500 end
501 endcase // unique case (op_type)
502 end
503
504 //////////////////////////////////////
505 // Data partition protection configuration
506 //////////////////////////////////////
507 // extra region is the default region
508 mp_region_cfg_t [MpRegions:0] region_cfgs;
509 assign region_cfgs[MpRegions-1:0] = reg2hw.mp_region_cfg[MpRegions-1:0];
510
511 //default region
512 assign region_cfgs[MpRegions].base.q = '0;
513 assign region_cfgs[MpRegions].size.q = NumBanks * PagesPerBank;
514 assign region_cfgs[MpRegions].en.q = 1'b1;
515 assign region_cfgs[MpRegions].rd_en.q = reg2hw.default_region.rd_en.q;
516 assign region_cfgs[MpRegions].prog_en.q = reg2hw.default_region.prog_en.q;
517 assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
518 assign region_cfgs[MpRegions].scramble_en.q = reg2hw.default_region.scramble_en.q;
Timothy Chena2db9332020-11-13 18:47:54 -0800519 assign region_cfgs[MpRegions].ecc_en.q = reg2hw.default_region.ecc_en.q;
Timothy Chenff4a7702020-10-27 15:08:53 -0700520
521 //////////////////////////////////////
522 // Info partition protection configuration
523 //////////////////////////////////////
524 info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] reg2hw_info_page_cfgs;
525 info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
526
527 // transform from reg output to structure
528 % for bank in range(cfg['banks']):
529 % for idx in range(cfg['info_types']):
530 assign reg2hw_info_page_cfgs[${bank}][${idx}] = reg2hw.bank${bank}_info${idx}_page_cfg;
531 % endfor
532 % endfor
533
534 // qualify reg2hw settings with creator / owner privileges
535 for(genvar i = 0; i < NumBanks; i++) begin : gen_info_priv_bank
536 for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_priv_type
537 flash_ctrl_info_cfg # (
538 .Bank(i),
539 .InfoSel(j)
540 ) u_info_cfg (
541 .cfgs_i(reg2hw_info_page_cfgs[i][j]),
542 .creator_seed_priv_i(creator_seed_priv),
543 .owner_seed_priv_i(owner_seed_priv),
544 .cfgs_o(info_page_cfgs[i][j])
545 );
546 end
547 end
548
549 //////////////////////////////////////
550 // flash memory protection
551 //////////////////////////////////////
552 // direct assignment since prog/rd/erase_ctrl do not make use of op_part
553 flash_part_e flash_part_sel;
554 logic [InfoTypesWidth-1:0] flash_info_sel;
555 assign flash_part_sel = op_part;
556 assign flash_info_sel = op_info_sel;
557
558 // Flash memory protection
559 // Memory protection is page based and thus should use phy addressing
560 // This should move to flash_phy long term
561 flash_mp u_flash_mp (
562 .clk_i,
563 .rst_ni,
564
565 // arbiter interface selection
566 .if_sel_i(if_sel),
567
568 // sw configuration for data partition
569 .region_cfgs_i(region_cfgs),
570 .bank_cfgs_i(reg2hw.mp_bank_cfg),
571
572 // sw configuration for info partition
573 .info_page_cfgs_i(info_page_cfgs),
574
575 // read / prog / erase controls
576 .req_i(flash_req),
577 .phase_i(phase),
578 .req_addr_i(flash_addr[BusAddrW-1 -: AllPagesW]),
579 .req_part_i(flash_part_sel),
580 .info_sel_i(flash_info_sel),
581 .addr_ovfl_i(rd_flash_ovfl | prog_flash_ovfl),
582 .rd_i(rd_op),
583 .prog_i(prog_op),
584 .pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
585 .bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
586 .rd_done_o(flash_rd_done),
587 .prog_done_o(flash_prog_done),
588 .erase_done_o(flash_erase_done),
589 .error_o(flash_mp_error),
590 .err_addr_o(err_addr),
591
592 // flash phy interface
593 .req_o(flash_o.req),
594 .scramble_en_o(flash_o.scramble_en),
Timothy Chena2db9332020-11-13 18:47:54 -0800595 .ecc_en_o(flash_o.ecc_en),
Timothy Chenff4a7702020-10-27 15:08:53 -0700596 .rd_o(flash_o.rd),
597 .prog_o(flash_o.prog),
598 .pg_erase_o(flash_o.pg_erase),
599 .bk_erase_o(flash_o.bk_erase),
600 .rd_done_i(flash_i.rd_done),
601 .prog_done_i(flash_i.prog_done),
602 .erase_done_i(flash_i.erase_done)
603 );
604
605
606 // software interface feedback
607 // most values (other than flash_phy_busy) should only update when software operations
608 // are actually selected
609 assign hw2reg.op_status.done.d = 1'b1;
610 assign hw2reg.op_status.done.de = sw_ctrl_done;
611 assign hw2reg.op_status.err.d = 1'b1;
612 assign hw2reg.op_status.err.de = sw_ctrl_err;
613 assign hw2reg.status.rd_full.d = ~rd_fifo_wready;
614 assign hw2reg.status.rd_full.de = sw_sel;
615 assign hw2reg.status.rd_empty.d = ~rd_fifo_rvalid;
616 assign hw2reg.status.rd_empty.de = sw_sel;
617 assign hw2reg.status.prog_full.d = ~prog_fifo_wready;
618 assign hw2reg.status.prog_full.de = sw_sel;
619 assign hw2reg.status.prog_empty.d = ~prog_fifo_rvalid;
620 assign hw2reg.status.prog_empty.de = sw_sel;
621 assign hw2reg.status.init_wip.d = flash_phy_busy | ctrl_init_busy;
622 assign hw2reg.status.init_wip.de = 1'b1;
623 assign hw2reg.status.error_addr.d = err_addr;
624 assign hw2reg.status.error_addr.de = sw_sel;
625 assign hw2reg.control.start.d = 1'b0;
626 assign hw2reg.control.start.de = sw_ctrl_done;
627 // if software operation selected, based on transaction start
628 // if software operation not selected, software is free to change contents
629 assign hw2reg.ctrl_regwen.d = sw_sel ? !op_start : 1'b1;
630
631 // phy status
632 assign hw2reg.phy_status.init_wip.d = flash_phy_busy;
633 assign hw2reg.phy_status.init_wip.de = 1'b1;
634 assign hw2reg.phy_status.prog_normal_avail.d = flash_i.prog_type_avail[FlashProgNormal];
635 assign hw2reg.phy_status.prog_normal_avail.de = 1'b1;
636 assign hw2reg.phy_status.prog_repair_avail.d = flash_i.prog_type_avail[FlashProgRepair];
637 assign hw2reg.phy_status.prog_repair_avail.de = 1'b1;
638
639 // Flash Interface
640 assign flash_o.addr = flash_addr;
641 assign flash_o.part = flash_part_sel;
642 assign flash_o.prog_type = flash_prog_type;
643 assign flash_o.prog_data = flash_prog_data;
644 assign flash_o.prog_last = flash_prog_last;
645 assign flash_o.region_cfgs = region_cfgs;
646 assign flash_o.addr_key = otp_i.addr_key;
647 assign flash_o.data_key = otp_i.data_key;
648 assign flash_rd_err = flash_i.rd_err;
649 assign flash_rd_data = flash_i.rd_data;
650 assign flash_phy_busy = flash_i.init_busy;
651
652 // Interface to pwrmgr
653 // flash is not idle as long as there is a stateful operation ongoing
654 logic flash_idle_d;
655 assign flash_idle_d = ~(flash_o.req &
656 (flash_o.prog | flash_o.pg_erase | flash_o.bk_erase));
657
658 prim_flop #(
659 .Width(1),
660 .ResetValue(1'b1)
661 ) u_reg_idle (
662 .clk_i,
663 .rst_ni,
664 .d_i(flash_idle_d),
665 .q_o(pwrmgr_o.flash_idle)
666 );
667
668
669 // Interrupts
670 // Generate edge triggered signals for sources that are level
671 logic [3:0] intr_src;
672 logic [3:0] intr_src_q;
673 logic [3:0] intr_assert;
674
675 assign intr_src = { ~prog_fifo_rvalid,
676 reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
677 ~rd_fifo_wready,
678 reg2hw.fifo_lvl.rd.q == rd_fifo_depth
679 };
680
681 always_ff @(posedge clk_i or negedge rst_ni) begin
682 if (!rst_ni) begin
683 intr_src_q <= 4'h8; //prog_fifo is empty by default
684 end else if (sw_sel) begin
685 intr_src_q <= intr_src;
686 end
687 end
688
689 assign intr_assert = ~intr_src_q & intr_src;
690
691
692 assign intr_prog_empty_o = reg2hw.intr_enable.prog_empty.q & reg2hw.intr_state.prog_empty.q;
693 assign intr_prog_lvl_o = reg2hw.intr_enable.prog_lvl.q & reg2hw.intr_state.prog_lvl.q;
694 assign intr_rd_full_o = reg2hw.intr_enable.rd_full.q & reg2hw.intr_state.rd_full.q;
695 assign intr_rd_lvl_o = reg2hw.intr_enable.rd_lvl.q & reg2hw.intr_state.rd_lvl.q;
696 assign intr_op_done_o = reg2hw.intr_enable.op_done.q & reg2hw.intr_state.op_done.q;
697 assign intr_op_error_o = reg2hw.intr_enable.op_error.q & reg2hw.intr_state.op_error.q;
698
699 assign hw2reg.intr_state.prog_empty.d = 1'b1;
700 assign hw2reg.intr_state.prog_empty.de = intr_assert[3] |
701 (reg2hw.intr_test.prog_empty.qe &
702 reg2hw.intr_test.prog_empty.q);
703
704 assign hw2reg.intr_state.prog_lvl.d = 1'b1;
705 assign hw2reg.intr_state.prog_lvl.de = intr_assert[2] |
706 (reg2hw.intr_test.prog_lvl.qe &
707 reg2hw.intr_test.prog_lvl.q);
708
709 assign hw2reg.intr_state.rd_full.d = 1'b1;
710 assign hw2reg.intr_state.rd_full.de = intr_assert[1] |
711 (reg2hw.intr_test.rd_full.qe &
712 reg2hw.intr_test.rd_full.q);
713
714 assign hw2reg.intr_state.rd_lvl.d = 1'b1;
715 assign hw2reg.intr_state.rd_lvl.de = intr_assert[0] |
716 (reg2hw.intr_test.rd_lvl.qe &
717 reg2hw.intr_test.rd_lvl.q);
718
719
720 assign hw2reg.intr_state.op_done.d = 1'b1;
721 assign hw2reg.intr_state.op_done.de = sw_ctrl_done |
722 (reg2hw.intr_test.op_done.qe &
723 reg2hw.intr_test.op_done.q);
724
725 assign hw2reg.intr_state.op_error.d = 1'b1;
726 assign hw2reg.intr_state.op_error.de = sw_ctrl_err |
727 (reg2hw.intr_test.op_error.qe &
728 reg2hw.intr_test.op_error.q);
729
730
731
732 // Unused bits
733 logic [BusByteWidth-1:0] unused_byte_sel;
734 logic [top_pkg::TL_AW-1-BusAddrW:0] unused_higher_addr_bits;
735 logic [top_pkg::TL_AW-1:0] unused_scratch;
736
737
738 // Unused signals
739 assign unused_byte_sel = muxed_addr[BusByteWidth-1:0];
740 assign unused_higher_addr_bits = muxed_addr[top_pkg::TL_AW-1:BusAddrW];
741 assign unused_scratch = reg2hw.scratch;
742
743
744 // Assertions
745 `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid )
746 `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready )
747 `ASSERT_KNOWN(FlashKnownO_A, {flash_o.req, flash_o.rd, flash_o.prog, flash_o.pg_erase,
748 flash_o.bk_erase})
749 `ASSERT_KNOWN_IF(FlashAddrKnown_A, flash_o.addr, flash_o.req)
750 `ASSERT_KNOWN_IF(FlashProgKnown_A, flash_o.prog_data, flash_o.prog & flash_o.req)
751 `ASSERT_KNOWN(IntrProgEmptyKnownO_A, intr_prog_empty_o)
752 `ASSERT_KNOWN(IntrProgLvlKnownO_A, intr_prog_lvl_o )
753 `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o )
754 `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o )
755 `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o )
756 `ASSERT_KNOWN(IntrOpErrorKnownO_A, intr_op_error_o )
757
758endmodule