Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
| 4 | { |
| 5 | name: "spi_device" |
Weicai Yang | a0f1ab9 | 2020-10-01 17:57:44 -0700 | [diff] [blame] | 6 | import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", |
| 7 | "hw/dv/tools/dvsim/testplans/mem_testplan.hjson", |
Cindy Chen | da227f6 | 2021-06-16 10:42:42 -0700 | [diff] [blame] | 8 | "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", |
Weicai Yang | a0f1ab9 | 2020-10-01 17:57:44 -0700 | [diff] [blame] | 9 | "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", |
Srikrishna Iyer | a463e17 | 2022-02-02 12:09:39 -0800 | [diff] [blame] | 10 | "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", |
Weicai Yang | a28800f | 2022-10-17 16:50:54 -0700 | [diff] [blame] | 11 | "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", |
Srikrishna Iyer | a463e17 | 2022-02-02 12:09:39 -0800 | [diff] [blame] | 12 | "spi_device_sec_cm_testplan.hjson"] |
Srikrishna Iyer | 86169d0 | 2021-05-10 09:35:52 -0700 | [diff] [blame] | 13 | testpoints: [ |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 14 | { |
Cindy Chen | 6ff7954 | 2020-11-11 10:16:16 -0800 | [diff] [blame] | 15 | name: smoke |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 16 | desc: ''' |
| 17 | Use default SRAM fifo setting. Seq: |
| 18 | - Write a word data to TX memory and update wptr |
| 19 | - Send a word SPI transfer |
| 20 | - Read a word data from RX memory and update rptr |
| 21 | - Compare the data and check no pending data in SRAM FIFO |
| 22 | - Repeat above steps''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 23 | stage: V1 |
Cindy Chen | 6ff7954 | 2020-11-11 10:16:16 -0800 | [diff] [blame] | 24 | tests: ["spi_device_smoke"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 25 | } |
| 26 | { |
| 27 | name: base_random_seq |
| 28 | desc: ''' |
| 29 | Create 3 parallel threads |
| 30 | - Write random data to TX memory unless fifo is full |
| 31 | - Send SPI transfer unless TX is empty or RX is full |
| 32 | - Read RX memory unless RX is empty''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 33 | stage: V2 |
Weicai Yang | 8fbd532 | 2020-01-21 18:13:10 -0800 | [diff] [blame] | 34 | tests: ["spi_device_txrx"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 35 | } |
| 36 | { |
| 37 | name: fifo_full |
| 38 | desc: ''' |
| 39 | Increase the chance to have fifo full by following |
| 40 | - Reduce delay to write TX memory |
| 41 | - Increase delay to read RX memory''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 42 | stage: V2 |
Weicai Yang | 8fbd532 | 2020-01-21 18:13:10 -0800 | [diff] [blame] | 43 | tests: ["spi_device_fifo_full"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 44 | } |
| 45 | { |
| 46 | name: fifo_underflow_overflow |
| 47 | desc: ''' |
| 48 | Override spi_device_txrx_vseq to send SPI transfer without checking TX/RX fifo, note: |
| 49 | - When TX is underflow, SW shouldn't update wptr if spi isn't idle, otherwise, spi may |
| 50 | send mis-aligned data |
| 51 | - When RX is overflow, data will be lost and if SW update rptr, received data may be |
| 52 | mis-aligned |
| 53 | - Ensure underflow/overflow is triggered correctly''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 54 | stage: V2 |
Weicai Yang | 8fbd532 | 2020-01-21 18:13:10 -0800 | [diff] [blame] | 55 | tests: ["spi_device_fifo_underflow_overflow"] |
| 56 | } |
| 57 | { |
| 58 | name: dummy_sck_and_dummy_csb |
| 59 | desc: ''' |
| 60 | Drive dummy sck without csb or drive dummy csb without sck, and test no impact on the |
| 61 | design''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 62 | stage: V2 |
Weicai Yang | 8fbd532 | 2020-01-21 18:13:10 -0800 | [diff] [blame] | 63 | tests: ["spi_device_dummy_item_extra_dly"] |
| 64 | } |
| 65 | { |
| 66 | name: extra_delay_on_spi |
| 67 | desc: ''' |
| 68 | Add extra delay between spi clock edge or extra delay between 2 words data |
| 69 | This is to test host pause transfer for a while without turning off csb and then stream |
| 70 | in data again''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 71 | stage: V2 |
Weicai Yang | 8fbd532 | 2020-01-21 18:13:10 -0800 | [diff] [blame] | 72 | tests: ["spi_device_dummy_item_extra_dly"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 73 | } |
| 74 | { |
Weicai Yang | dba4833 | 2021-12-02 16:09:28 -0800 | [diff] [blame] | 75 | name: tx_async_fifo_reset |
| 76 | desc: ''' |
| 77 | Reset TX async fifo when SPI interface is idle |
| 78 | |
| 79 | - Fill TX SRAM FIFO with some data, which will be transfered to TX async FIFO |
| 80 | - Write 0 into read and write point of TX SRAM FIFO |
| 81 | - Program `rst_txfifo` to reset the async FIFO |
| 82 | - Check `async_fifo_level.txlvl` is 0 |
| 83 | - Fill TX SRAM FIFO with some other data and enable SPI transfer |
| 84 | - Check SPI device sends and receives the correct data |
| 85 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 86 | stage: V2 |
Kosta Kojdic | f3d772a | 2021-12-28 20:37:14 +0000 | [diff] [blame] | 87 | tests: ["spi_device_tx_async_fifo_reset"] |
Weicai Yang | dba4833 | 2021-12-02 16:09:28 -0800 | [diff] [blame] | 88 | } |
| 89 | { |
| 90 | name: rx_async_fifo_reset |
| 91 | desc: ''' |
| 92 | Reset RX async fifo when SPI interface is idle |
| 93 | |
| 94 | - Configure RX SRAM FIFO with a small size, so that it's easy to fill up |
| 95 | - Start SPI transfers to fill up the RX SRAM FIFO and at least part of the RX async |
| 96 | FIFO |
| 97 | - Program `rst_rxfifo` to reset the async FIFO |
| 98 | - Check `async_fifo_level.rxlvl` is 0 |
| 99 | - Write 0 into read and write point of RX SRAM FIFO |
| 100 | - Fill TX SRAM FIFO with some other data and start another SPI transfers |
| 101 | - Check SPI device sends and receives the correct data |
| 102 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 103 | stage: V2 |
Kosta Kojdic | f3d772a | 2021-12-28 20:37:14 +0000 | [diff] [blame] | 104 | tests: ["spi_device_rx_async_fifo_reset"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 105 | } |
| 106 | { |
| 107 | name: interrupts |
| 108 | desc: ''' |
| 109 | Test all supported interrupts: |
| 110 | - tx/rx lvl |
| 111 | - rx full |
| 112 | - rx error |
| 113 | - overflow/underflow''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 114 | stage: V2 |
Weicai Yang | b37566f | 2021-06-04 17:03:08 -0700 | [diff] [blame] | 115 | tests: ["spi_device_intr"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 116 | } |
| 117 | { |
| 118 | name: abort |
| 119 | desc: ''' |
Kosta Kojdic | f3d772a | 2021-12-28 20:37:14 +0000 | [diff] [blame] | 120 | - Fill TX FIFO without host traffic |
| 121 | - Issue Abort to control register |
| 122 | - Poll until abort_done in status register |
| 123 | - TBD additional checking |
| 124 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 125 | stage: V2 |
Kosta Kojdic | f3d772a | 2021-12-28 20:37:14 +0000 | [diff] [blame] | 126 | tests: ["spi_device_abort"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 127 | } |
| 128 | { |
| 129 | name: byte_transfer_on_spi |
| 130 | desc: '''send spi transfer on byte granularity, and make sure the timer never expires''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 131 | stage: V2 |
kosta-kojdic | de09c16 | 2021-12-02 13:29:12 +0000 | [diff] [blame] | 132 | tests: ["spi_device_byte_transfer"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 133 | } |
| 134 | { |
| 135 | name: rx_timeout |
| 136 | desc: ''' |
| 137 | - Send spi transfer on byte granularity, and timer may expires |
| 138 | - Only check data in sequence level when timer expires. Monitor and scoreboard don't |
| 139 | model the timer feature |
| 140 | - Note: Timeout only for RX''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 141 | stage: V2 |
kosta-kojdic | de09c16 | 2021-12-02 13:29:12 +0000 | [diff] [blame] | 142 | tests: ["spi_device_rx_timeout"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 143 | } |
| 144 | { |
| 145 | name: bit_transfer_on_spi |
| 146 | desc: ''' |
| 147 | Send spi transfer on bit granularity |
| 148 | - If TX drives < 7 bits, this byte will be sent in next CSB. |
| 149 | - If TX drives 7 bits and set CSB to high, this byte won't be sent in next CSB''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 150 | stage: V2 |
Kosta Kojdic | f3d772a | 2021-12-28 20:37:14 +0000 | [diff] [blame] | 151 | tests: ["spi_device_bit_transfer"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 152 | } |
| 153 | { |
| 154 | name: extreme_fifo_setting |
| 155 | desc: '''Set fifo size to 4 bytes(minimum), 2k-4bytes(maximum) and others''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 156 | stage: V2 |
Weicai Yang | 8fbd532 | 2020-01-21 18:13:10 -0800 | [diff] [blame] | 157 | tests: ["spi_device_extreme_fifo_size"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 158 | } |
| 159 | { |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 160 | name: perf |
| 161 | desc: '''Run spi_device_fifi_full_vseq with very small delays''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 162 | stage: V2 |
kosta-kojdic | de09c16 | 2021-12-02 13:29:12 +0000 | [diff] [blame] | 163 | tests: ["spi_device_perf"] |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 164 | } |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 165 | { |
Weicai Yang | 613668a | 2022-10-11 14:19:10 -0700 | [diff] [blame] | 166 | name: csb_read |
| 167 | desc: '''Read CSB value from CSR and check the correctness |
| 168 | |
| 169 | This feature is for debug only, so it's sufficient to verify with this direct sequence: |
| 170 | - Assign both CSB pins with random values and read the CSB CSRs to check the values''' |
| 171 | stage: V2 |
| 172 | tests: ["spi_device_csb_read"] |
| 173 | } |
| 174 | { |
Weicai Yang | 8b1c3bd | 2022-10-20 15:31:39 -0700 | [diff] [blame] | 175 | name: mem_parity |
| 176 | desc: '''Test memory parity error |
| 177 | |
| 178 | pick a random mem address to inject parity errors and read it back, |
| 179 | then check it returns d_error with all 1s data.''' |
| 180 | stage: V2 |
| 181 | tests: ["spi_device_mem_parity"] |
| 182 | } |
| 183 | { |
Weicai Yang | 7a7139c | 2022-10-24 15:38:17 -0700 | [diff] [blame] | 184 | name: mem_cfg |
| 185 | desc: '''Test cfg_i connectivity between spi_device and prim_ram_2p. |
| 186 | |
| 187 | Randomly set dut.ram_cfg_i and check this value is propagated to prim_mem_2p.''' |
| 188 | stage: V2 |
| 189 | tests: ["spi_device_ram_cfg"] |
| 190 | } |
| 191 | { |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 192 | name: tpm_read |
| 193 | desc: ''' |
Weicai Yang | 2512ca0 | 2022-10-03 17:00:07 -0700 | [diff] [blame] | 194 | - Set TPM_CFG.TPM_MODE to CRB mode and set TPM_CFG.EN. |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 195 | - Randomise other fields in TPM_CFG. |
| 196 | - Assert the tpm_csb. |
| 197 | - Send TPM read command over the SPI bus with a randomised address. |
| 198 | - Check TPM_CMD_ADDR. |
| 199 | - Confirm FIFO behaviour dictated by TPM_CFG.tpm_mode. |
| 200 | - Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty, they should be asserted if hw_reg_dis == 0. |
| 201 | - If hw_reg_dis == 0, the data is returned to the host via return-by-HW register, else the data is returned via read FIFO. |
| 202 | - Confirm that the TPM submodule sends WAIT until the read FIFO is available. |
| 203 | - Check the read FIFO. |
| 204 | - When available, confirm that the TPM submodule sends START followed by the register value. |
| 205 | - Compare this value with the expected value.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 206 | stage: V2 |
Weicai Yang | 652feab | 2022-09-22 21:22:44 -0700 | [diff] [blame] | 207 | tests: ["spi_device_tpm_rw"] |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 208 | } |
| 209 | { |
| 210 | name: tpm_write |
| 211 | desc: ''' |
Weicai Yang | 2512ca0 | 2022-10-03 17:00:07 -0700 | [diff] [blame] | 212 | - Set TPM_CFG.TPM_MODE to CRB mode and set TPM_CFG.EN. |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 213 | - Randomise other fields in TPM_CFG. |
| 214 | - Assert the tpm_csb. |
| 215 | - Send TPM write command with a randomised address. |
| 216 | - Check TPM_CMD_ADDR and write FIFO. |
| 217 | - Check TPM_STATUS.cmdaddr_notempty and INTR_STATE.tpm_header_notempty. |
| 218 | - Based on FIFO status, check SPI bus to confirm WAIT or START sent. |
| 219 | - Check that the TPM submodule accepts write data without the WAIT state if the write FIFO is empty. |
| 220 | - Otherwise, check WAIT until the write FIFO becomes available (empty).''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 221 | stage: V2 |
Weicai Yang | 2512ca0 | 2022-10-03 17:00:07 -0700 | [diff] [blame] | 222 | tests: ["spi_device_tpm_rw"] |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 223 | } |
| 224 | { |
Weicai Yang | 144e511 | 2022-10-05 23:00:18 -0700 | [diff] [blame] | 225 | name: tpm_hw_reg |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 226 | desc: ''' |
Weicai Yang | 144e511 | 2022-10-05 23:00:18 -0700 | [diff] [blame] | 227 | - Configure `TPM_CFG` as follows to have DUT directly respond for the access to the HW |
| 228 | registers. |
| 229 | - Set `tpm_mode` to fifo mode. |
| 230 | - Set `hw_reg_dis` to 0. |
| 231 | - Set `tpm_reg_chk_dis` to 0. |
| 232 | - Set `invalid_locality` to 1. |
| 233 | - Send SPI transactions of varying HW registers. In the meanwhile, SW updates the HW |
| 234 | registers. |
| 235 | - Ensure that the data returned is correct for the given address and active locality.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 236 | stage: V2 |
Weicai Yang | 2512ca0 | 2022-10-03 17:00:07 -0700 | [diff] [blame] | 237 | tests: ["spi_device_tpm_sts_read", "spi_device_tpm_read_hw_reg"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 238 | } |
| 239 | { |
Weicai Yang | 144e511 | 2022-10-05 23:00:18 -0700 | [diff] [blame] | 240 | name: tpm_fully_random_case |
| 241 | desc: ''' |
| 242 | - Configure `TPM_CFG.EN` to On and fully randomize other TPM configuration. |
| 243 | - Run these 3 threads to randomly access TPM HW registers and other addresses. |
| 244 | - Host issues random TPM reads/writes to spi_device. |
| 245 | - SW polls the TPM interrupt `tpm_header_not_empty`, then read command/address and |
| 246 | the corresponding FIFO. |
| 247 | - SW randomly updates TPM HW registers. |
| 248 | - Ensure all the data is correct in the scoreboard.''' |
| 249 | stage: V2 |
| 250 | tests: ["spi_device_tpm_all"] |
| 251 | } |
| 252 | { |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 253 | name: pass_cmd_filtering |
| 254 | desc: ''' |
| 255 | - Randomize command opcode. |
| 256 | - Configure unused CMD_INFO reg with new opcode and set it to valid. |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 257 | - Check opcode, address and payload are passing through. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 258 | - Configure filter bit corresponding to opcode to 1. |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 259 | - Check the entire command is filtered. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 260 | - Set filter bit back to 0. |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 261 | - Check opcode and address are passing through again. |
| 262 | - Invalid opcode is also filtered''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 263 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 264 | tests: ["spi_device_pass_cmd_filtering", "spi_device_flash_all"] |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 265 | } |
| 266 | { |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 267 | name: pass_addr_translation |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 268 | desc: ''' |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 269 | - Randomize command opcode. |
| 270 | - Configure unused CMD_INFO reg with new opcode and set it to valid. |
| 271 | - Enable address translation for given command. |
| 272 | - Configure address translation bits. |
| 273 | - Check proper address translation is applied. |
| 274 | - Disable address translation for given command. |
| 275 | - Check address is now passing unchanged.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 276 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 277 | tests: ["spi_device_pass_addr_payload_swap", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 278 | } |
| 279 | { |
| 280 | name: pass_payload_translation |
| 281 | desc: ''' |
| 282 | - Configure program or write_status command. |
| 283 | - Enable payload translation for given command. |
| 284 | - Configure payload translation bits. |
| 285 | - Check proper payload translation is applied. |
| 286 | - Disable payload translation for given command. |
| 287 | - Check payload is now passing unchanged.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 288 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 289 | tests: ["spi_device_pass_addr_payload_swap", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 290 | } |
| 291 | { |
| 292 | name: cmd_info_slots |
| 293 | desc: ''' |
| 294 | - Configure first 5 slots according to required configuration. |
| 295 | - Configure next 6 slots for read commands |
| 296 | - Randomize configuration of the remaining 13 cmd info slots. |
| 297 | - Issue commands with various opcodes enabled in info slots. |
| 298 | - Check proper command propagation. |
| 299 | - Disable some cmd info slots. |
| 300 | - Check no propagation of disabled commands.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 301 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 302 | tests: ["spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 303 | } |
| 304 | { |
| 305 | name: cmd_read_status |
| 306 | desc: ''' |
| 307 | - Configure proper read status command info slot. |
| 308 | - Issue read status command. |
| 309 | - Check propagation of read status command. |
| 310 | - Initiate response to the read status. |
| 311 | - Check proper reception of response.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 312 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 313 | tests: ["spi_device_intercept", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 314 | } |
| 315 | { |
| 316 | name: cmd_read_jedec |
| 317 | desc: ''' |
| 318 | - Configure proper read jedec command info slot. |
| 319 | - Issue read jedec command. |
| 320 | - Check propagation of read jedec command. |
| 321 | - Initiate response to the read jedec. |
| 322 | - Check proper reception of response.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 323 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 324 | tests: ["spi_device_intercept", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 325 | } |
| 326 | { |
| 327 | name: cmd_read_sfdp |
| 328 | desc: ''' |
| 329 | - Configure proper read sfdp command info slot. |
| 330 | - Issue read sfdp command. |
| 331 | - Check propagation of read sfdp command. |
| 332 | - Initiate response to the read sfdp. |
| 333 | - Check proper reception of response.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 334 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 335 | tests: ["spi_device_intercept", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 336 | } |
| 337 | { |
| 338 | name: cmd_fast_read |
| 339 | desc: ''' |
| 340 | - Configure proper fast read command info slot. |
| 341 | - Issue fast read command. |
| 342 | - Check propagation of fast read command. |
| 343 | - Initiate response to the fast read. |
| 344 | - Check proper reception of response.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 345 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 346 | tests: ["spi_device_intercept", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 347 | } |
| 348 | { |
| 349 | name: flash_cmd_upload |
| 350 | desc: ''' |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 351 | - Configure spi_device on flash or passthrough mode. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 352 | - Configure cmd info slots. |
| 353 | - Set upload to 1 for some of 13 non fixed cmd info slots. |
| 354 | - Host should poll busy field status to check if command is done. |
| 355 | - Issue next command upload and poll busy status again.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 356 | stage: V2 |
Weicai Yang | 3fd71c0 | 2022-08-08 11:49:52 -0700 | [diff] [blame] | 357 | tests: ["spi_device_upload"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 358 | } |
| 359 | { |
| 360 | name: mailbox_command |
| 361 | desc: ''' |
| 362 | - Configure cmd info slots. |
| 363 | - Issue one of predefined read command targeting mailbox space. |
| 364 | - Check response to read command. |
| 365 | - Check if command is processed internally.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 366 | stage: V2 |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 367 | tests: ["spi_device_mailbox"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 368 | } |
| 369 | { |
| 370 | name: mailbox_cross_outside_command |
| 371 | desc: ''' |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 372 | - Configure spi_device on passthrough mode. Mailbox boundary crossing is not expected to |
| 373 | be used on flash mode, so that testing this on flash mode isn't needed. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 374 | - Configure cmd info slots. |
| 375 | - Issue one of predefined read command targeting mailbox space. |
| 376 | - Command should start inside mailbox space and cross into read space. |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 377 | - When the address falls in the mailbox region, data returns from the mailbox. when the |
| 378 | address is outside the mailbox, data returns as follows |
| 379 | - returns high-z if the read command is filtered. |
| 380 | - returns from downstream port if read command is passed through.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 381 | stage: V2 |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 382 | tests: ["spi_device_mailbox"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 383 | } |
| 384 | { |
| 385 | name: mailbox_cross_inside_command |
| 386 | desc: ''' |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 387 | - Similar to `mailbox_cross_outside_command`, except that start address is inside the |
| 388 | mailbox.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 389 | stage: V2 |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 390 | tests: ["spi_device_mailbox"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 391 | } |
| 392 | { |
| 393 | name: cmd_read_buffer |
| 394 | desc: ''' |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 395 | - Configure device in flash mode. |
| 396 | - Issue read commands. |
| 397 | - Create another parallel thread that SW updates read buffer contents after a watermark |
| 398 | or buffer flip event occurs. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 399 | - Check proper read data. |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 400 | - Randomly issue read command that crosses read buffer boundary and switches back to |
| 401 | index 0. |
| 402 | - Check correctness of `last_read_addr`, `readbuf_watermark` and `readbuf_flip`.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 403 | stage: V2 |
Weicai Yang | fc2548b | 2022-08-22 22:46:04 -0700 | [diff] [blame] | 404 | tests: ["spi_device_flash_mode", "spi_device_read_buffer_direct"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 405 | } |
| 406 | { |
| 407 | name: cmd_dummy_cycle |
| 408 | desc: ''' |
| 409 | - Configure cmd info slots. |
| 410 | - Configure dummy cycle of read commands to non default value. |
Weicai Yang | 3fd71c0 | 2022-08-08 11:49:52 -0700 | [diff] [blame] | 411 | - For single mode allowed dummy cycle is 0 or more. |
| 412 | - For dual/quad mode allowed dummy cycle is 2 or more. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 413 | - Check return data timing for configured commands. |
| 414 | - Check proper read data. |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 415 | - Issue new read command that crosses read maibox boundary. |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 416 | - Check internal buffer index bit.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 417 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 418 | tests: ["spi_device_mailbox", "spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 419 | } |
| 420 | { |
| 421 | name: quad_spi |
| 422 | desc: ''' |
| 423 | - Configure passthrough or flash mode. |
| 424 | - Configure cmd info slots. |
| 425 | - Configure quad mode. |
| 426 | - Issue supported command. |
| 427 | - Check data on all four lines.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 428 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 429 | tests: ["spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 430 | } |
| 431 | { |
| 432 | name: dual_spi |
| 433 | desc: ''' |
| 434 | - Configure passthrough or flash mode. |
| 435 | - Configure cmd info slots. |
| 436 | - Configure dual mode. |
| 437 | - Issue supported command. |
| 438 | - Check data on both lines.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 439 | stage: V2 |
Weicai Yang | a1d24f3 | 2022-08-18 17:13:54 -0700 | [diff] [blame] | 440 | tests: ["spi_device_flash_all"] |
Kosta Kojdic | 057465f | 2022-01-21 11:10:56 +0000 | [diff] [blame] | 441 | } |
| 442 | { |
| 443 | name: 4b_3b_feature |
| 444 | desc: ''' |
| 445 | - Configure passthrough or flash mode. |
| 446 | - Configure command info slots. |
| 447 | - Configure different values for 4B/3B. |
| 448 | - Randomize configuration of EN4B and EX4B register fields. |
| 449 | - Issue supported command with required address. |
| 450 | - Check proper address propagation.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 451 | stage: V2 |
Weicai Yang | de87d8c | 2022-08-16 17:45:50 -0700 | [diff] [blame] | 452 | tests: ["spi_device_cfg_cmd"] |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 453 | } |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 454 | { |
| 455 | name: write_enable_disable |
| 456 | desc: ''' |
| 457 | - Configure passthrough or flash mode. |
| 458 | - Randomize WREN and WRDI command info slots. |
| 459 | - Issue WREN and WRDI commands along with read_status command and others. |
| 460 | - Read flash status via TL interface. |
| 461 | - Check WREN/WRDI sets/clears flash status correctly.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 462 | stage: V2 |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 463 | tests: ["spi_device_cfg_cmd"] |
| 464 | } |
Weicai Yang | 3c0501a | 2022-08-23 11:37:40 -0700 | [diff] [blame] | 465 | { |
| 466 | name: TPM_with_flash_or_passthrough_mode |
| 467 | desc: ''' |
| 468 | - Enable TPM mode. |
| 469 | - Configure passthrough or flash mode. |
| 470 | - Issue TPM read/write interleaving with flash transactions.''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 471 | stage: V2 |
Weicai Yang | 5ed2fcb | 2022-10-07 16:04:56 -0700 | [diff] [blame] | 472 | tests: ["spi_device_flash_and_tpm"] |
Weicai Yang | 3c0501a | 2022-08-23 11:37:40 -0700 | [diff] [blame] | 473 | } |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 474 | { |
| 475 | name: tpm_and_flash_trans_with_min_inactive_time |
| 476 | desc: ''' |
| 477 | Issue these transactions with 2 sys_clk inactive time in between. |
| 478 | - 2 tpm transactions. |
| 479 | - 2 flash transactions. |
| 480 | - a tpm transaction and a flash transaction.''' |
| 481 | stage: V2 |
Weicai Yang | e01285f | 2022-10-25 12:24:27 -0700 | [diff] [blame] | 482 | tests: ["spi_device_flash_and_tpm_min_idle"] |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 483 | } |
| 484 | { |
| 485 | name: stress_all |
| 486 | desc: ''' |
| 487 | - Combine above sequences in one test to run sequentially, except csr sequences. |
| 488 | - Test modes switch among FW, flash, passthrough and tpm. |
| 489 | - Randomly add reset between each sequence''' |
| 490 | stage: V2 |
Weicai Yang | a28800f | 2022-10-17 16:50:54 -0700 | [diff] [blame] | 491 | tests: ["spi_device_stress_all"] |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 492 | } |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 493 | ] |
| 494 | covergroups: [ |
| 495 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 496 | name: all_modes_cg |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 497 | desc: ''' |
| 498 | Cover every combination of all possible modes: |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 499 | - FW mode, passthrough mode and flash mode. |
| 500 | Cover passthrough mode and flash mode with TPM mode enabled.''' |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 501 | } |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 502 | // FW mode |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 503 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 504 | name: bit_order_clk_cfg_cg |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 505 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 506 | Cover all configurations of rx/tx order in SPI_DEVICE.CFG for FW mode. |
| 507 | Note: Flash or TPM mode always use the fixed bit order. |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 508 | |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 509 | Cover all combinations of SPI_DEVICE.CFG.CPOL and SPI_DEVICE.CFG.CPHA. |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 510 | Cross both bit order and clock configure.''' |
| 511 | } |
| 512 | { |
| 513 | name: fw_tx_fifo_size_cg |
| 514 | desc: ''' |
| 515 | Cover these values are used to configure TX fifo size for FW mode. |
| 516 | - min(1 word), typical(half of SRAM size), max(SRAM size - 1 word) |
| 517 | Sample this when fifo is full.''' |
| 518 | } |
| 519 | { |
| 520 | name: fw_rx_fifo_size_cg |
| 521 | desc: ''' |
| 522 | The same CG as `fw_tx_fifo_size_cg` for RX.''' |
| 523 | } |
| 524 | // TPM mode |
| 525 | { |
| 526 | name: tpm_cfg_cg |
| 527 | desc: ''' |
| 528 | Cover all combinations of these configurations in CSR `tpm_cfg`: |
| 529 | - tpm_mode, hw_reg_dis, tpm_reg_chk_dis, invalid_locality. |
| 530 | Cover these address mode: |
| 531 | - TPM address in both valid and invalid locality. |
| 532 | - TPM address in/outside TPM address region ('hd4_xxxx). |
| 533 | - TPM offset matching to any HW return register. |
| 534 | - Both word aligned and unaligned. |
| 535 | Cross above with TPM read and write transactions. |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 536 | |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 537 | This CG is sampled when receiving a TPM request.''' |
Jason Hoddinett | 2527f07 | 2021-11-22 10:25:15 +0000 | [diff] [blame] | 538 | } |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 539 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 540 | name: tpm_read_hw_reg_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 541 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 542 | Cover TPM read on all HW returned registered.''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 543 | } |
| 544 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 545 | name: tpm_transfer_size_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 546 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 547 | Cover both TPM read and write. |
| 548 | Cover request HW returned and SW handled. |
| 549 | Cross above with various payload size. |
| 550 | - min (1B), typical (4B), max (64B).''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 551 | } |
| 552 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 553 | name: tpm_sts_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 554 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 555 | Cover `tpm_sts` read and write on an active/inactive tpm access. |
| 556 | Cover `tpm_sts` read with HW returned and SW handled. |
| 557 | Cross above with all locality.''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 558 | } |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 559 | // flash/passthrough mode |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 560 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 561 | name: flash_cmd_info_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 562 | desc: ''' |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 563 | Cover flash/passthrough mode. |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 564 | Cover all opcode enabled in cmd info. |
| 565 | Cover all payload direction. |
| 566 | Cover all address modes. |
| 567 | Cover addr swap enable. |
| 568 | Cover payload swap enable. |
| 569 | Cover upload enable. |
| 570 | Cover busy enable. |
| 571 | Cover all dummy sizes. |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 572 | Cover number of payload lanes (single, dual and quad modes or no payload). |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 573 | |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 574 | cross mode, payload directions, address modes, addr/payload swap enable. |
Weicai Yang | d0f667d | 2022-10-24 13:04:54 -0700 | [diff] [blame] | 575 | cross mode, dummy sizes, number of lanes. |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 576 | ''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 577 | } |
| 578 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 579 | name: passthrough_addr_swap_cg |
| 580 | desc: ''' |
| 581 | Cover address swap on a transaction with both payload direction (read and program). |
| 582 | Cover all bits toggled on the swap address and mask. |
| 583 | Cross with filter enabled and disabled.''' |
| 584 | } |
| 585 | { |
| 586 | name: passthrough_payload_swap_cg |
| 587 | desc: ''' |
| 588 | Cover payload swap on a transaction with both payload direction (read and program). |
| 589 | Cover all bits toggled on the swap payload and mask. |
| 590 | Cross with filter enabled and disabled.''' |
| 591 | } |
| 592 | { |
| 593 | name: passthrough_cmd_filter_cg |
| 594 | desc: ''' |
| 595 | Cover all possible bits for command filter. |
| 596 | Every opcode should be enabled and filtering checked.''' |
| 597 | } |
| 598 | { |
| 599 | name: flash_status_cg |
| 600 | desc: ''' |
| 601 | Cover all status bits toggled. |
| 602 | Cross above with host reading status and SW reading status. |
| 603 | Cover SW updating flash_status while CSB is active.''' |
| 604 | } |
| 605 | { |
| 606 | name: flash_upload_payload_size_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 607 | desc: ''' |
| 608 | Cover supported payload sizes for IN transactions. |
| 609 | Cover supported payload sizes for OUT transactions. |
| 610 | Cover upload transaction payload size. |
| 611 | Cover payload size of upload transaction exceeds 256B limit (wrap around).''' |
| 612 | } |
| 613 | { |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 614 | name: flash_command_while_busy_set_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 615 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 616 | Cover host sends flash commands while busy bit is set. |
| 617 | Cover above with filter enabled/disabled on that command. |
| 618 | ''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 619 | } |
| 620 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 621 | name: flash_read_commands_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 622 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 623 | Cover read status/read JEDEC/read SFDP and all other read commands configurable in the |
| 624 | first 10 slots. |
| 625 | Cover dummy cycle. |
| 626 | Cover filter enabled/disabled. |
| 627 | Cover various payload size |
| 628 | Cover INTERCEPT_EN. |
| 629 | Cross all above items.''' |
| 630 | } |
| 631 | { |
| 632 | name: passthrough_mailbox_cg |
| 633 | desc: ''' |
| 634 | Cover read commands targeting inside mailbox space. |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 635 | Cover command starting outside mailbox and crossing into mailbox space. |
| 636 | Cover command starting in mailbox comming outside mailbox space. |
| 637 | Cover command starting outside mailbox and crossing the entire mailbox space and coming |
| 638 | outside mailbox. |
| 639 | Cross above with filter on and off.''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 640 | } |
| 641 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 642 | name: flash_mailbox_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 643 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 644 | Cover read commands targeting inside mailbox space in the flash mode.''' |
| 645 | } |
| 646 | { |
| 647 | name: spi_device_4B_enter_exit_command_cg |
| 648 | desc: ''' |
| 649 | Cover both EN4B and EX4B commands. |
| 650 | Cross this with the previous `cfg_addr_4b_en` value. |
| 651 | ''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 652 | } |
| 653 | { |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 654 | name: sw_update_addr4b_cg |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 655 | desc: ''' |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 656 | Cover SW updating addr4b to another value. |
| 657 | ''' |
Kosta Kojdic | 569feb9 | 2022-04-11 14:13:19 +0100 | [diff] [blame] | 658 | } |
Guillermo Maturana | de067f7 | 2022-08-15 13:45:30 -0700 | [diff] [blame] | 659 | { |
| 660 | name: spi_device_write_enable_disable_cg |
| 661 | desc: ''' |
| 662 | Cover write enable and write disable commands. |
| 663 | Cross this with the previous flash_status.wel value.''' |
| 664 | } |
Weicai Yang | 3c0501a | 2022-08-23 11:37:40 -0700 | [diff] [blame] | 665 | { |
Weicai Yang | d1721e2 | 2022-10-18 22:00:42 -0700 | [diff] [blame] | 666 | name: spi_device_buffer_boundary_cg |
| 667 | desc: ''' |
| 668 | Cover all the read commands. |
| 669 | Cover buffer boundary crossing (2 buffer flips).''' |
| 670 | } |
| 671 | { |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 672 | name: tpm_interleave_with_flash_item_cg |
Weicai Yang | 3c0501a | 2022-08-23 11:37:40 -0700 | [diff] [blame] | 673 | desc: ''' |
Weicai Yang | 045f122 | 2022-10-13 11:38:04 -0700 | [diff] [blame] | 674 | Cover TPM transactions interleaving with flash transactions.''' |
Weicai Yang | 3c0501a | 2022-08-23 11:37:40 -0700 | [diff] [blame] | 675 | } |
Weicai Yang | dda5948 | 2019-11-12 16:42:18 -0800 | [diff] [blame] | 676 | ] |
| 677 | } |