Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
| 4 | // |
| 5 | { |
Michael Schaffner | 2608b59 | 2023-01-13 14:12:48 -0800 | [diff] [blame] | 6 | name: "aon_timer", |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 7 | human_name: "Always-On Timer", |
Andreas Kurth | 218294b | 2023-02-07 19:03:35 +0100 | [diff] [blame] | 8 | one_line_desc: "Wakeup and watchdog timers running on a low-power, always-on clock", |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 9 | one_paragraph_desc: ''' |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 10 | Always-On (AON) Timer is the main timer hardware block of OpenTitan. |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 11 | It includes two 32-bit up-counting timers, one of which functions as a wakeup timer and the other as a watchdog timer. |
| 12 | The watchdog timer has two thresholds: a 'bark' threshold that generates an interrupt and a 'bite' threshold that resets the system. |
| 13 | The wakeup timer has a 12-bit pre-scaler to enable very long timeouts and also generates an interrupt to the core. |
| 14 | The timers run on a ~200 kHz AON clock and have a maximum timeout window of roughly ~6 hours for the watchdog timer and ~1000 days with the use of the pre-scaler for the wakeup timer. |
| 15 | ''' |
Michael Schaffner | 2608b59 | 2023-01-13 14:12:48 -0800 | [diff] [blame] | 16 | design_spec: "../doc", |
| 17 | dv_doc: "../doc/dv", |
| 18 | hw_checklist: "../doc/checklist", |
| 19 | sw_checklist: "/sw/device/lib/dif/dif_aon_timer", |
| 20 | version: "1.0", |
| 21 | life_stage: "L1", |
| 22 | design_stage: "D3", |
| 23 | verification_stage: "V2", |
| 24 | dif_stage: "S2", |
Rupert Swarbrick | d0cbfad | 2021-06-29 17:04:51 +0100 | [diff] [blame] | 25 | clocking: [ |
| 26 | {clock: "clk_i", reset: "rst_ni", primary: true}, |
| 27 | {clock: "clk_aon_i", reset: "rst_aon_ni"} |
| 28 | ] |
Rupert Swarbrick | 6c83129 | 2021-02-25 17:08:53 +0000 | [diff] [blame] | 29 | bus_interfaces: [ |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 30 | { protocol: "tlul", direction: "device"} |
Rupert Swarbrick | 6c83129 | 2021-02-25 17:08:53 +0000 | [diff] [blame] | 31 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 32 | interrupt_list: [ |
| 33 | { name: "wkup_timer_expired", |
| 34 | desc: "Raised if the wakeup timer has hit the specified threshold" |
| 35 | }, |
| 36 | { name: "wdog_timer_bark", |
| 37 | desc: "Raised if the watchdog timer has hit the bark threshold" |
| 38 | }, |
| 39 | ], |
Michael Schaffner | ae414ef | 2021-06-22 18:56:31 -0700 | [diff] [blame] | 40 | alert_list: [ |
| 41 | { name: "fatal_fault", |
| 42 | desc: ''' |
Michael Schaffner | 99e8937 | 2021-06-25 17:33:33 -0700 | [diff] [blame] | 43 | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
Michael Schaffner | ae414ef | 2021-06-22 18:56:31 -0700 | [diff] [blame] | 44 | ''' |
| 45 | } |
| 46 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 47 | wakeup_list: [ |
Timothy Chen | 910d01c | 2021-09-24 13:53:39 -0700 | [diff] [blame] | 48 | { name: "wkup_req", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 49 | desc: "Raised if the wakeup or watchdog timer has hit the specified threshold" |
| 50 | }, |
| 51 | ], |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 52 | reset_request_list: [ |
| 53 | { name: "aon_timer_rst_req", |
| 54 | desc: "watchdog reset requestt" |
| 55 | }, |
| 56 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 57 | inter_signal_list: [ |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 58 | // wakeup and reset request signals |
| 59 | { struct: "logic", |
| 60 | type: "uni", |
Timothy Chen | 576cc08 | 2021-07-21 17:42:48 -0700 | [diff] [blame] | 61 | name: "nmi_wdog_timer_bark", |
| 62 | act: "req", |
| 63 | package: "", |
| 64 | default: "1'b0" |
| 65 | }, |
| 66 | { struct: "logic", |
| 67 | type: "uni", |
Timothy Chen | 910d01c | 2021-09-24 13:53:39 -0700 | [diff] [blame] | 68 | name: "wkup_req", |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 69 | act: "req", |
| 70 | package: "", |
| 71 | default: "1'b0" |
| 72 | }, |
| 73 | { struct: "logic", |
| 74 | type: "uni", |
| 75 | name: "aon_timer_rst_req", |
| 76 | act: "req", |
| 77 | package: "", |
| 78 | default: "1'b0" |
| 79 | }, |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 80 | // Broadcast from LC |
| 81 | { struct: "lc_tx" |
| 82 | type: "uni" |
Michael Schaffner | 475c711 | 2021-05-12 14:25:43 -0700 | [diff] [blame] | 83 | name: "lc_escalate_en" |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 84 | act: "rcv" |
| 85 | default: "lc_ctrl_pkg::Off" |
| 86 | package: "lc_ctrl_pkg" |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 87 | }, |
| 88 | { name: "sleep_mode", |
| 89 | type: "uni", |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 90 | act: "rcv", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 91 | package: "", |
| 92 | struct: "logic", |
| 93 | width: "1" |
| 94 | } |
| 95 | ], |
Michael Schaffner | 1762693 | 2021-12-13 09:10:43 -0800 | [diff] [blame] | 96 | countermeasures: [ |
| 97 | { name: "BUS.INTEGRITY", |
| 98 | desc: "End-to-end bus integrity scheme." |
| 99 | } |
| 100 | ] |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 101 | no_auto_intr_regs: "true", |
| 102 | regwidth: "32", |
| 103 | registers: [ |
| 104 | { name: "WKUP_CTRL", |
| 105 | desc: "Wakeup Timer Control register", |
| 106 | swaccess: "rw", |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 107 | hwaccess: "hro", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 108 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 109 | fields: [ |
| 110 | { bits: "0", |
| 111 | name: "enable", |
| 112 | desc: "When set to 1, the wakeup timer will count", |
| 113 | } |
| 114 | { bits: "12:1", |
| 115 | name: "prescaler", |
| 116 | desc: "Pre-scaler value for wakeup timer count", |
| 117 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 118 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 119 | }, |
| 120 | { name: "WKUP_THOLD", |
| 121 | desc: "Wakeup Timer Threshold Register", |
| 122 | swaccess: "rw", |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 123 | hwaccess: "hro", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 124 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 125 | fields: [ |
| 126 | { bits: "31:0", |
| 127 | name: "threshold", |
| 128 | desc: "The count at which a wakeup interrupt should be generated", |
| 129 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 130 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 131 | }, |
| 132 | { name: "WKUP_COUNT", |
| 133 | desc: "Wakeup Timer Count Register", |
| 134 | swaccess: "rw", |
| 135 | hwaccess: "hrw", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 136 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 137 | fields: [ |
| 138 | { bits: "31:0", |
| 139 | name: "count", |
| 140 | desc: "The current wakeup counter value", |
| 141 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 142 | ], |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 143 | tags: [// this could be updated by HW |
| 144 | "excl:CsrNonInitTests:CsrExclWriteCheck"], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 145 | }, |
| 146 | { name: "WDOG_REGWEN", |
| 147 | desc: "Watchdog Timer Write Enable Register", |
Michael Schaffner | 3a06723 | 2021-02-10 18:13:45 -0800 | [diff] [blame] | 148 | swaccess: "rw0c", |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 149 | hwaccess: "none", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 150 | fields: [ |
| 151 | { bits: "0", |
| 152 | name: "regwen", |
| 153 | desc: "Once cleared, the watchdog configuration will be locked until the next reset", |
| 154 | resval: 1 |
| 155 | } |
| 156 | ] |
| 157 | }, |
| 158 | { name: "WDOG_CTRL", |
| 159 | desc: "Watchdog Timer Control register", |
| 160 | swaccess: "rw", |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 161 | hwaccess: "hro", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 162 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 163 | regwen: "WDOG_REGWEN", |
| 164 | fields: [ |
| 165 | { bits: "0", |
| 166 | name: "enable", |
| 167 | desc: "When set to 1, the watchdog timer will count", |
| 168 | }, |
| 169 | { bits: "1", |
| 170 | name: "pause_in_sleep", |
| 171 | desc: "When set to 1, the watchdog timer will not count during sleep", |
| 172 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 173 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 174 | }, |
| 175 | { name: "WDOG_BARK_THOLD", |
| 176 | desc: "Watchdog Timer Bark Threshold Register", |
| 177 | swaccess: "rw", |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 178 | hwaccess: "hro", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 179 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 180 | regwen: "WDOG_REGWEN", |
| 181 | fields: [ |
| 182 | { bits: "31:0", |
| 183 | name: "threshold", |
| 184 | desc: "The count at which a watchdog bark interrupt should be generated", |
| 185 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 186 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 187 | }, |
| 188 | { name: "WDOG_BITE_THOLD", |
| 189 | desc: "Watchdog Timer Bite Threshold Register", |
| 190 | swaccess: "rw", |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 191 | hwaccess: "hro", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 192 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 193 | regwen: "WDOG_REGWEN", |
| 194 | fields: [ |
| 195 | { bits: "31:0", |
| 196 | name: "threshold", |
| 197 | desc: "The count at which a watchdog bite reset should be generated", |
| 198 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 199 | ], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 200 | }, |
| 201 | { name: "WDOG_COUNT", |
| 202 | desc: "Watchdog Timer Count Register", |
| 203 | swaccess: "rw", |
| 204 | hwaccess: "hrw", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 205 | async: "clk_aon_i", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 206 | fields: [ |
| 207 | { bits: "31:0", |
| 208 | name: "count", |
| 209 | desc: "The current watchdog counter value", |
| 210 | } |
Timothy Chen | 2b8ef76 | 2021-02-16 14:44:55 -0800 | [diff] [blame] | 211 | ], |
Tom Roberts | 535dfe3 | 2021-06-10 15:50:37 +0100 | [diff] [blame] | 212 | tags: [// this could be updated by HW |
| 213 | "excl:CsrNonInitTests:CsrExclWriteCheck"], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 214 | }, |
| 215 | { name: "INTR_STATE", |
| 216 | desc: "Interrupt State Register", |
| 217 | swaccess: "rw1c", |
| 218 | hwaccess: "hrw", |
| 219 | fields: [ |
| 220 | { bits: "0", |
| 221 | name: "wkup_timer_expired", |
| 222 | desc: "Raised if the wakeup timer has hit the specified threshold", |
| 223 | } |
| 224 | { bits: "1", |
Timothy Trippel | e56b147 | 2021-10-06 19:01:01 +0000 | [diff] [blame] | 225 | name: "wdog_timer_bark", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 226 | desc: "Raised if the watchdog timer has hit the bark threshold", |
| 227 | } |
| 228 | ] |
Weicai Yang | ea96a35 | 2021-02-22 12:07:46 -0800 | [diff] [blame] | 229 | tags: [// interrupt could be updated by HW |
| 230 | "excl:CsrNonInitTests:CsrExclWriteCheck"], |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 231 | }, |
| 232 | { name: "INTR_TEST", |
| 233 | desc: "Interrupt Test Register", |
| 234 | swaccess: "wo", |
| 235 | hwaccess: "hro", |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 236 | hwext: "true", |
| 237 | hwqe: "true", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 238 | fields: [ |
| 239 | { bits: "0", |
| 240 | name: "wkup_timer_expired", |
| 241 | desc: "Write 1 to force wkup_timer_expired interrupt", |
| 242 | } |
| 243 | { bits: "1", |
Timothy Trippel | e56b147 | 2021-10-06 19:01:01 +0000 | [diff] [blame] | 244 | name: "wdog_timer_bark", |
| 245 | desc: "Write 1 to force wdog_timer_bark interrupt", |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 246 | } |
| 247 | ] |
| 248 | }, |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 249 | { name: "WKUP_CAUSE", |
| 250 | desc: "Wakeup request status", |
| 251 | swaccess: "rw0c", |
| 252 | hwaccess: "hrw", |
Timothy Chen | a49ceb6 | 2021-07-13 14:59:09 -0700 | [diff] [blame] | 253 | async: "clk_aon_i", |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 254 | fields: [ |
| 255 | { bits: "0", |
| 256 | name: "cause", |
| 257 | desc: "AON timer requested wakeup, write 0 to clear", |
| 258 | } |
| 259 | ] |
Weicai Yang | ea96a35 | 2021-02-22 12:07:46 -0800 | [diff] [blame] | 260 | tags: [// this could be updated by HW |
| 261 | "excl:CsrNonInitTests:CsrExclWriteCheck"], |
Tom Roberts | 1a0a024 | 2020-12-17 12:06:23 +0000 | [diff] [blame] | 262 | }, |
Tom Roberts | 7f173f2 | 2020-12-01 14:29:31 +0000 | [diff] [blame] | 263 | ], |
| 264 | } |