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Tom Roberts7f173f22020-12-01 14:29:31 +00001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5{
Michael Schaffner2608b592023-01-13 14:12:48 -08006 name: "aon_timer",
Andreas Kurth62113492023-02-13 14:50:22 +01007 human_name: "Always-On Timer",
Andreas Kurth218294b2023-02-07 19:03:35 +01008 one_line_desc: "Wakeup and watchdog timers running on a low-power, always-on clock",
Andreas Kurthf8500c02023-02-10 11:40:59 +01009 one_paragraph_desc: '''
Andreas Kurth62113492023-02-13 14:50:22 +010010 Always-On (AON) Timer is the main timer hardware block of OpenTitan.
Andreas Kurthf8500c02023-02-10 11:40:59 +010011 It includes two 32-bit up-counting timers, one of which functions as a wakeup timer and the other as a watchdog timer.
12 The watchdog timer has two thresholds: a 'bark' threshold that generates an interrupt and a 'bite' threshold that resets the system.
13 The wakeup timer has a 12-bit pre-scaler to enable very long timeouts and also generates an interrupt to the core.
14 The timers run on a ~200 kHz AON clock and have a maximum timeout window of roughly ~6 hours for the watchdog timer and ~1000 days with the use of the pre-scaler for the wakeup timer.
15 '''
Michael Schaffner2608b592023-01-13 14:12:48 -080016 design_spec: "../doc",
17 dv_doc: "../doc/dv",
18 hw_checklist: "../doc/checklist",
19 sw_checklist: "/sw/device/lib/dif/dif_aon_timer",
20 version: "1.0",
21 life_stage: "L1",
22 design_stage: "D3",
23 verification_stage: "V2",
24 dif_stage: "S2",
Rupert Swarbrickd0cbfad2021-06-29 17:04:51 +010025 clocking: [
26 {clock: "clk_i", reset: "rst_ni", primary: true},
27 {clock: "clk_aon_i", reset: "rst_aon_ni"}
28 ]
Rupert Swarbrick6c831292021-02-25 17:08:53 +000029 bus_interfaces: [
Timothy Chena49ceb62021-07-13 14:59:09 -070030 { protocol: "tlul", direction: "device"}
Rupert Swarbrick6c831292021-02-25 17:08:53 +000031 ],
Tom Roberts7f173f22020-12-01 14:29:31 +000032 interrupt_list: [
33 { name: "wkup_timer_expired",
34 desc: "Raised if the wakeup timer has hit the specified threshold"
35 },
36 { name: "wdog_timer_bark",
37 desc: "Raised if the watchdog timer has hit the bark threshold"
38 },
39 ],
Michael Schaffnerae414ef2021-06-22 18:56:31 -070040 alert_list: [
41 { name: "fatal_fault",
42 desc: '''
Michael Schaffner99e89372021-06-25 17:33:33 -070043 This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
Michael Schaffnerae414ef2021-06-22 18:56:31 -070044 '''
45 }
46 ],
Tom Roberts7f173f22020-12-01 14:29:31 +000047 wakeup_list: [
Timothy Chen910d01c2021-09-24 13:53:39 -070048 { name: "wkup_req",
Tom Roberts7f173f22020-12-01 14:29:31 +000049 desc: "Raised if the wakeup or watchdog timer has hit the specified threshold"
50 },
51 ],
Timothy Chen2b8ef762021-02-16 14:44:55 -080052 reset_request_list: [
53 { name: "aon_timer_rst_req",
54 desc: "watchdog reset requestt"
55 },
56 ],
Tom Roberts7f173f22020-12-01 14:29:31 +000057 inter_signal_list: [
Timothy Chen2b8ef762021-02-16 14:44:55 -080058 // wakeup and reset request signals
59 { struct: "logic",
60 type: "uni",
Timothy Chen576cc082021-07-21 17:42:48 -070061 name: "nmi_wdog_timer_bark",
62 act: "req",
63 package: "",
64 default: "1'b0"
65 },
66 { struct: "logic",
67 type: "uni",
Timothy Chen910d01c2021-09-24 13:53:39 -070068 name: "wkup_req",
Timothy Chen2b8ef762021-02-16 14:44:55 -080069 act: "req",
70 package: "",
71 default: "1'b0"
72 },
73 { struct: "logic",
74 type: "uni",
75 name: "aon_timer_rst_req",
76 act: "req",
77 package: "",
78 default: "1'b0"
79 },
Tom Roberts1a0a0242020-12-17 12:06:23 +000080 // Broadcast from LC
81 { struct: "lc_tx"
82 type: "uni"
Michael Schaffner475c7112021-05-12 14:25:43 -070083 name: "lc_escalate_en"
Tom Roberts1a0a0242020-12-17 12:06:23 +000084 act: "rcv"
85 default: "lc_ctrl_pkg::Off"
86 package: "lc_ctrl_pkg"
Tom Roberts7f173f22020-12-01 14:29:31 +000087 },
88 { name: "sleep_mode",
89 type: "uni",
Timothy Chen2b8ef762021-02-16 14:44:55 -080090 act: "rcv",
Tom Roberts7f173f22020-12-01 14:29:31 +000091 package: "",
92 struct: "logic",
93 width: "1"
94 }
95 ],
Michael Schaffner17626932021-12-13 09:10:43 -080096 countermeasures: [
97 { name: "BUS.INTEGRITY",
98 desc: "End-to-end bus integrity scheme."
99 }
100 ]
Tom Roberts7f173f22020-12-01 14:29:31 +0000101 no_auto_intr_regs: "true",
102 regwidth: "32",
103 registers: [
104 { name: "WKUP_CTRL",
105 desc: "Wakeup Timer Control register",
106 swaccess: "rw",
Tom Roberts535dfe32021-06-10 15:50:37 +0100107 hwaccess: "hro",
Timothy Chena49ceb62021-07-13 14:59:09 -0700108 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000109 fields: [
110 { bits: "0",
111 name: "enable",
112 desc: "When set to 1, the wakeup timer will count",
113 }
114 { bits: "12:1",
115 name: "prescaler",
116 desc: "Pre-scaler value for wakeup timer count",
117 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800118 ],
Tom Roberts7f173f22020-12-01 14:29:31 +0000119 },
120 { name: "WKUP_THOLD",
121 desc: "Wakeup Timer Threshold Register",
122 swaccess: "rw",
Tom Roberts535dfe32021-06-10 15:50:37 +0100123 hwaccess: "hro",
Timothy Chena49ceb62021-07-13 14:59:09 -0700124 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000125 fields: [
126 { bits: "31:0",
127 name: "threshold",
128 desc: "The count at which a wakeup interrupt should be generated",
129 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800130 ],
Tom Roberts7f173f22020-12-01 14:29:31 +0000131 },
132 { name: "WKUP_COUNT",
133 desc: "Wakeup Timer Count Register",
134 swaccess: "rw",
135 hwaccess: "hrw",
Timothy Chena49ceb62021-07-13 14:59:09 -0700136 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000137 fields: [
138 { bits: "31:0",
139 name: "count",
140 desc: "The current wakeup counter value",
141 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800142 ],
Tom Roberts535dfe32021-06-10 15:50:37 +0100143 tags: [// this could be updated by HW
144 "excl:CsrNonInitTests:CsrExclWriteCheck"],
Tom Roberts7f173f22020-12-01 14:29:31 +0000145 },
146 { name: "WDOG_REGWEN",
147 desc: "Watchdog Timer Write Enable Register",
Michael Schaffner3a067232021-02-10 18:13:45 -0800148 swaccess: "rw0c",
Tom Roberts1a0a0242020-12-17 12:06:23 +0000149 hwaccess: "none",
Tom Roberts7f173f22020-12-01 14:29:31 +0000150 fields: [
151 { bits: "0",
152 name: "regwen",
153 desc: "Once cleared, the watchdog configuration will be locked until the next reset",
154 resval: 1
155 }
156 ]
157 },
158 { name: "WDOG_CTRL",
159 desc: "Watchdog Timer Control register",
160 swaccess: "rw",
Tom Roberts535dfe32021-06-10 15:50:37 +0100161 hwaccess: "hro",
Timothy Chena49ceb62021-07-13 14:59:09 -0700162 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000163 regwen: "WDOG_REGWEN",
164 fields: [
165 { bits: "0",
166 name: "enable",
167 desc: "When set to 1, the watchdog timer will count",
168 },
169 { bits: "1",
170 name: "pause_in_sleep",
171 desc: "When set to 1, the watchdog timer will not count during sleep",
172 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800173 ],
Tom Roberts7f173f22020-12-01 14:29:31 +0000174 },
175 { name: "WDOG_BARK_THOLD",
176 desc: "Watchdog Timer Bark Threshold Register",
177 swaccess: "rw",
Tom Roberts535dfe32021-06-10 15:50:37 +0100178 hwaccess: "hro",
Timothy Chena49ceb62021-07-13 14:59:09 -0700179 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000180 regwen: "WDOG_REGWEN",
181 fields: [
182 { bits: "31:0",
183 name: "threshold",
184 desc: "The count at which a watchdog bark interrupt should be generated",
185 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800186 ],
Tom Roberts7f173f22020-12-01 14:29:31 +0000187 },
188 { name: "WDOG_BITE_THOLD",
189 desc: "Watchdog Timer Bite Threshold Register",
190 swaccess: "rw",
Tom Roberts535dfe32021-06-10 15:50:37 +0100191 hwaccess: "hro",
Timothy Chena49ceb62021-07-13 14:59:09 -0700192 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000193 regwen: "WDOG_REGWEN",
194 fields: [
195 { bits: "31:0",
196 name: "threshold",
197 desc: "The count at which a watchdog bite reset should be generated",
198 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800199 ],
Tom Roberts7f173f22020-12-01 14:29:31 +0000200 },
201 { name: "WDOG_COUNT",
202 desc: "Watchdog Timer Count Register",
203 swaccess: "rw",
204 hwaccess: "hrw",
Timothy Chena49ceb62021-07-13 14:59:09 -0700205 async: "clk_aon_i",
Tom Roberts7f173f22020-12-01 14:29:31 +0000206 fields: [
207 { bits: "31:0",
208 name: "count",
209 desc: "The current watchdog counter value",
210 }
Timothy Chen2b8ef762021-02-16 14:44:55 -0800211 ],
Tom Roberts535dfe32021-06-10 15:50:37 +0100212 tags: [// this could be updated by HW
213 "excl:CsrNonInitTests:CsrExclWriteCheck"],
Tom Roberts7f173f22020-12-01 14:29:31 +0000214 },
215 { name: "INTR_STATE",
216 desc: "Interrupt State Register",
217 swaccess: "rw1c",
218 hwaccess: "hrw",
219 fields: [
220 { bits: "0",
221 name: "wkup_timer_expired",
222 desc: "Raised if the wakeup timer has hit the specified threshold",
223 }
224 { bits: "1",
Timothy Trippele56b1472021-10-06 19:01:01 +0000225 name: "wdog_timer_bark",
Tom Roberts7f173f22020-12-01 14:29:31 +0000226 desc: "Raised if the watchdog timer has hit the bark threshold",
227 }
228 ]
Weicai Yangea96a352021-02-22 12:07:46 -0800229 tags: [// interrupt could be updated by HW
230 "excl:CsrNonInitTests:CsrExclWriteCheck"],
Tom Roberts7f173f22020-12-01 14:29:31 +0000231 },
232 { name: "INTR_TEST",
233 desc: "Interrupt Test Register",
234 swaccess: "wo",
235 hwaccess: "hro",
Tom Roberts1a0a0242020-12-17 12:06:23 +0000236 hwext: "true",
237 hwqe: "true",
Tom Roberts7f173f22020-12-01 14:29:31 +0000238 fields: [
239 { bits: "0",
240 name: "wkup_timer_expired",
241 desc: "Write 1 to force wkup_timer_expired interrupt",
242 }
243 { bits: "1",
Timothy Trippele56b1472021-10-06 19:01:01 +0000244 name: "wdog_timer_bark",
245 desc: "Write 1 to force wdog_timer_bark interrupt",
Tom Roberts7f173f22020-12-01 14:29:31 +0000246 }
247 ]
248 },
Tom Roberts1a0a0242020-12-17 12:06:23 +0000249 { name: "WKUP_CAUSE",
250 desc: "Wakeup request status",
251 swaccess: "rw0c",
252 hwaccess: "hrw",
Timothy Chena49ceb62021-07-13 14:59:09 -0700253 async: "clk_aon_i",
Tom Roberts1a0a0242020-12-17 12:06:23 +0000254 fields: [
255 { bits: "0",
256 name: "cause",
257 desc: "AON timer requested wakeup, write 0 to clear",
258 }
259 ]
Weicai Yangea96a352021-02-22 12:07:46 -0800260 tags: [// this could be updated by HW
261 "excl:CsrNonInitTests:CsrExclWriteCheck"],
Tom Roberts1a0a0242020-12-17 12:06:23 +0000262 },
Tom Roberts7f173f22020-12-01 14:29:31 +0000263 ],
264}