lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 1 | #!/bin/bash |
| 2 | |
| 3 | # Copyright lowRISC contributors. |
| 4 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 5 | # SPDX-License-Identifier: Apache-2.0 |
| 6 | |
| 7 | # This script converts all SystemVerilog RTL files to Verilog and then |
| 8 | # runs Yosys. |
| 9 | # |
| 10 | # The following tools are required: |
| 11 | # - sv2v: SystemVerilog-to-Verilog converter from github.com/zachjs/sv2v |
| 12 | # - yosys: synthesis tool from github.com/YosysHQ/yosys |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 13 | # - Cadence Conformal |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 14 | # |
| 15 | # Usage: |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 16 | # ./syn_yosys.sh 2>&1 | tee syn.std |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 17 | |
| 18 | #------------------------------------------------------------------------- |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 19 | # use fusesoc to generate files and file list |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 20 | #------------------------------------------------------------------------- |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 21 | \rm -Rf build syn_out |
| 22 | fusesoc --cores-root .. run --target=syn \ |
| 23 | --setup lowrisc:systems:top_earlgrey > /dev/null 2>&1 |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 24 | |
| 25 | # copy all files into directory "syn_out" |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 26 | mkdir syn_out |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 27 | cp \ |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 28 | build/*/src/*/*.sv* \ |
| 29 | build/*/src/*/*/*.sv* \ |
| 30 | build/*/src/*/*/*/*.sv* \ |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 31 | syn_out |
Miles Dai | 762b9ae | 2022-07-07 15:29:11 -0400 | [diff] [blame] | 32 | cd syn_out || exit |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 33 | |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 34 | # copy file list, remove incdir and pins_if, and flatten pathnames |
| 35 | grep -Ev 'incdir|pins_if' ../build/*/*/*.scr | sed 's!.*/!!' > flist_gold |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 36 | |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 37 | # generate revised flist by replacing '.sv' by '.v' and removing packages |
Zachary Snow | a07394d | 2020-07-25 17:22:44 -0400 | [diff] [blame] | 38 | sed -e 's/.sv/.v/g' flist_gold | grep -v "_pkg.v" > flist_rev |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 39 | |
| 40 | #------------------------------------------------------------------------- |
| 41 | # convert all RTL files to Verilog |
| 42 | #------------------------------------------------------------------------- |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 43 | |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 44 | printf "\nSV2V VERSION:\n" |
| 45 | sv2v --version |
| 46 | |
| 47 | printf "\nSV2V ERRORS:\n" |
| 48 | |
Zachary Snow | a07394d | 2020-07-25 17:22:44 -0400 | [diff] [blame] | 49 | # drive strengths are not supported by Yosys |
| 50 | sed -i.bak -e "s/VERILATOR/SYNTHESIS/" prim_generic_pad_wrapper.sv |
| 51 | |
Zachary Snow | a07394d | 2020-07-25 17:22:44 -0400 | [diff] [blame] | 52 | rm *.sv.bak |
| 53 | |
| 54 | sv2v -DSYNTHESIS *.sv +RTS -N4 > combined.v |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 55 | # split files up |
| 56 | modules=`cat combined.v | grep "^module" | sed -e "s/^module //" | sed -e "s/ (//"` |
| 57 | echo "$modules" > modules.txt # for debugging |
| 58 | for module in $modules; do |
| 59 | sed -n "/^module $module /,/^endmodule/p" < combined.v > $module.v |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 60 | done |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 61 | rm combined.v |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 62 | |
| 63 | #------------------------------------------------------------------------- |
Philipp Wagner | 14a3fee | 2019-11-21 10:07:02 +0000 | [diff] [blame] | 64 | # run LEC (generarted Verilog vs. original SystemVerilog) |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 65 | #------------------------------------------------------------------------- |
| 66 | printf "\n\nLEC RESULTS:\n" |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 67 | |
Zachary Snow | a07394d | 2020-07-25 17:22:44 -0400 | [diff] [blame] | 68 | # all of top_earlgrey's submodules |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 69 | declare -a modules=( |
| 70 | "rv_dm" |
| 71 | "spi_device" |
| 72 | "usbdev" |
| 73 | "flash_ctrl" |
| 74 | "tlul_adapter_sram" |
| 75 | "prim_rom_adv" |
| 76 | "prim_ram_1p_adv" |
| 77 | "uart" |
| 78 | "gpio" |
| 79 | "aes" |
| 80 | "hmac" |
| 81 | "pinmux" |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 82 | "alert_handler" |
| 83 | "pwrmgr" |
| 84 | "rstmgr" |
| 85 | "clkmgr" |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 86 | "rv_timer" |
| 87 | "rv_plic" |
| 88 | "rv_core_ibex" |
| 89 | "xbar_main" |
| 90 | "xbar_peri" |
| 91 | "flash_phy" |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 92 | ) |
| 93 | |
Zachary Snow | a07394d | 2020-07-25 17:22:44 -0400 | [diff] [blame] | 94 | # TODO: top_earlgrey appears to be too large for verification under the currrent |
| 95 | # setup. Consider adding verification using `hier_compare`. |
| 96 | |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 97 | for module in "${modules[@]}"; do |
| 98 | export LEC_TOP="$module" |
| 99 | |
| 100 | # run Conformal LEC |
| 101 | lec -xl -nogui -nobanner \ |
| 102 | -dofile ../../hw/formal/lec_sv2v.do \ |
| 103 | -logfile lec_${module}.log \ |
| 104 | <<< "exit -force" > /dev/null 2>&1 |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 105 | |
| 106 | # summarize results |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 107 | result=`grep "Compare Results" lec_${module}.log 2>&1` |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 108 | if [ $? -ne 0 ]; then |
| 109 | result="CRASH" |
| 110 | else |
| 111 | result=`echo $result | awk '{ print $4 }'` |
| 112 | fi |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 113 | printf "%-25s %s\n" $module $result |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 114 | done |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 115 | |
| 116 | #------------------------------------------------------------------------- |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 117 | # run yosys |
| 118 | #------------------------------------------------------------------------- |
Nils Graf | 03cf29f | 2019-09-18 16:06:17 -0700 | [diff] [blame] | 119 | printf "\n\nYosys:\n" |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 120 | yosys -QTqp " |
Nils Graf | 03a87c0 | 2020-06-26 18:01:17 -0700 | [diff] [blame] | 121 | read_verilog *.v; |
| 122 | hierarchy -check -top top_earlgrey; |
| 123 | synth_xilinx; |
| 124 | write_blif out.blif; |
| 125 | write_edif out.edif; |
| 126 | write_json out.json; |
Zachary Snow | 42ae6fc | 2020-06-10 21:15:29 -0400 | [diff] [blame] | 127 | " |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 128 | |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 129 | # TODOs: |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 130 | # - add full yosys synthesis for all modules |
| 131 | # - add final LEC check (RTL-versus-netlist) |