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lowRISC Contributors802543a2019-08-31 12:12:56 +01001#!/bin/bash
2
3# Copyright lowRISC contributors.
4# Licensed under the Apache License, Version 2.0, see LICENSE for details.
5# SPDX-License-Identifier: Apache-2.0
6
7# This script converts all SystemVerilog RTL files to Verilog and then
8# runs Yosys.
9#
10# The following tools are required:
11# - sv2v: SystemVerilog-to-Verilog converter from github.com/zachjs/sv2v
12# - yosys: synthesis tool from github.com/YosysHQ/yosys
Nils Graf03a87c02020-06-26 18:01:17 -070013# - Cadence Conformal
lowRISC Contributors802543a2019-08-31 12:12:56 +010014#
15# Usage:
Nils Graf03a87c02020-06-26 18:01:17 -070016# ./syn_yosys.sh 2>&1 | tee syn.std
lowRISC Contributors802543a2019-08-31 12:12:56 +010017
18#-------------------------------------------------------------------------
Nils Graf03cf29f2019-09-18 16:06:17 -070019# use fusesoc to generate files and file list
lowRISC Contributors802543a2019-08-31 12:12:56 +010020#-------------------------------------------------------------------------
Nils Graf03a87c02020-06-26 18:01:17 -070021\rm -Rf build syn_out
22fusesoc --cores-root .. run --target=syn \
23 --setup lowrisc:systems:top_earlgrey > /dev/null 2>&1
lowRISC Contributors802543a2019-08-31 12:12:56 +010024
25# copy all files into directory "syn_out"
lowRISC Contributors802543a2019-08-31 12:12:56 +010026mkdir syn_out
Zachary Snow42ae6fc2020-06-10 21:15:29 -040027cp \
Nils Graf03a87c02020-06-26 18:01:17 -070028 build/*/src/*/*.sv* \
29 build/*/src/*/*/*.sv* \
30 build/*/src/*/*/*/*.sv* \
Zachary Snow42ae6fc2020-06-10 21:15:29 -040031 syn_out
Miles Dai762b9ae2022-07-07 15:29:11 -040032cd syn_out || exit
Zachary Snow42ae6fc2020-06-10 21:15:29 -040033
Nils Graf03a87c02020-06-26 18:01:17 -070034# copy file list, remove incdir and pins_if, and flatten pathnames
35grep -Ev 'incdir|pins_if' ../build/*/*/*.scr | sed 's!.*/!!' > flist_gold
Zachary Snow42ae6fc2020-06-10 21:15:29 -040036
Nils Graf03a87c02020-06-26 18:01:17 -070037# generate revised flist by replacing '.sv' by '.v' and removing packages
Zachary Snowa07394d2020-07-25 17:22:44 -040038sed -e 's/.sv/.v/g' flist_gold | grep -v "_pkg.v" > flist_rev
lowRISC Contributors802543a2019-08-31 12:12:56 +010039
40#-------------------------------------------------------------------------
41# convert all RTL files to Verilog
42#-------------------------------------------------------------------------
Nils Graf03a87c02020-06-26 18:01:17 -070043
Nils Graf03a87c02020-06-26 18:01:17 -070044printf "\nSV2V VERSION:\n"
45sv2v --version
46
47printf "\nSV2V ERRORS:\n"
48
Zachary Snowa07394d2020-07-25 17:22:44 -040049# drive strengths are not supported by Yosys
50sed -i.bak -e "s/VERILATOR/SYNTHESIS/" prim_generic_pad_wrapper.sv
51
Zachary Snowa07394d2020-07-25 17:22:44 -040052rm *.sv.bak
53
54sv2v -DSYNTHESIS *.sv +RTS -N4 > combined.v
Zachary Snow42ae6fc2020-06-10 21:15:29 -040055# split files up
56modules=`cat combined.v | grep "^module" | sed -e "s/^module //" | sed -e "s/ (//"`
57echo "$modules" > modules.txt # for debugging
58for module in $modules; do
59 sed -n "/^module $module /,/^endmodule/p" < combined.v > $module.v
lowRISC Contributors802543a2019-08-31 12:12:56 +010060done
Zachary Snow42ae6fc2020-06-10 21:15:29 -040061rm combined.v
lowRISC Contributors802543a2019-08-31 12:12:56 +010062
63#-------------------------------------------------------------------------
Philipp Wagner14a3fee2019-11-21 10:07:02 +000064# run LEC (generarted Verilog vs. original SystemVerilog)
Nils Graf03cf29f2019-09-18 16:06:17 -070065#-------------------------------------------------------------------------
66printf "\n\nLEC RESULTS:\n"
Nils Graf03a87c02020-06-26 18:01:17 -070067
Zachary Snowa07394d2020-07-25 17:22:44 -040068# all of top_earlgrey's submodules
Nils Graf03a87c02020-06-26 18:01:17 -070069declare -a modules=(
70 "rv_dm"
71 "spi_device"
72 "usbdev"
73 "flash_ctrl"
74 "tlul_adapter_sram"
75 "prim_rom_adv"
76 "prim_ram_1p_adv"
77 "uart"
78 "gpio"
79 "aes"
80 "hmac"
81 "pinmux"
Nils Graf03a87c02020-06-26 18:01:17 -070082 "alert_handler"
83 "pwrmgr"
84 "rstmgr"
85 "clkmgr"
Nils Graf03a87c02020-06-26 18:01:17 -070086 "rv_timer"
87 "rv_plic"
88 "rv_core_ibex"
89 "xbar_main"
90 "xbar_peri"
91 "flash_phy"
Nils Graf03a87c02020-06-26 18:01:17 -070092)
93
Zachary Snowa07394d2020-07-25 17:22:44 -040094# TODO: top_earlgrey appears to be too large for verification under the currrent
95# setup. Consider adding verification using `hier_compare`.
96
Nils Graf03a87c02020-06-26 18:01:17 -070097for module in "${modules[@]}"; do
98 export LEC_TOP="$module"
99
100 # run Conformal LEC
101 lec -xl -nogui -nobanner \
102 -dofile ../../hw/formal/lec_sv2v.do \
103 -logfile lec_${module}.log \
104 <<< "exit -force" > /dev/null 2>&1
Nils Graf03cf29f2019-09-18 16:06:17 -0700105
106 # summarize results
Zachary Snow42ae6fc2020-06-10 21:15:29 -0400107 result=`grep "Compare Results" lec_${module}.log 2>&1`
Nils Graf03cf29f2019-09-18 16:06:17 -0700108 if [ $? -ne 0 ]; then
109 result="CRASH"
110 else
111 result=`echo $result | awk '{ print $4 }'`
112 fi
Nils Graf03a87c02020-06-26 18:01:17 -0700113 printf "%-25s %s\n" $module $result
Nils Graf03cf29f2019-09-18 16:06:17 -0700114done
Nils Graf03cf29f2019-09-18 16:06:17 -0700115
116#-------------------------------------------------------------------------
lowRISC Contributors802543a2019-08-31 12:12:56 +0100117# run yosys
118#-------------------------------------------------------------------------
Nils Graf03cf29f2019-09-18 16:06:17 -0700119printf "\n\nYosys:\n"
Zachary Snow42ae6fc2020-06-10 21:15:29 -0400120yosys -QTqp "
Nils Graf03a87c02020-06-26 18:01:17 -0700121 read_verilog *.v;
122 hierarchy -check -top top_earlgrey;
123 synth_xilinx;
124 write_blif out.blif;
125 write_edif out.edif;
126 write_json out.json;
Zachary Snow42ae6fc2020-06-10 21:15:29 -0400127"
lowRISC Contributors802543a2019-08-31 12:12:56 +0100128
lowRISC Contributors802543a2019-08-31 12:12:56 +0100129# TODOs:
lowRISC Contributors802543a2019-08-31 12:12:56 +0100130# - add full yosys synthesis for all modules
131# - add final LEC check (RTL-versus-netlist)