| commit | 03cf29fad412aef17fb97f432461174c8a800451 | [log] [tgz] |
|---|---|---|
| author | Nils Graf <nilsg@google.com> | Wed Sep 18 16:06:17 2019 -0700 |
| committer | NilsGraf <49500697+NilsGraf@users.noreply.github.com> | Mon Oct 14 09:07:43 2019 -0700 |
| tree | 446bbb4ae73d183f031734ec13bc335fa6ba09d7 | |
| parent | c1453e8d587af2a00434f534e76f003b085b9cc3 [diff] |
[util/syn_yosys] Add LEC script to check Verilog generated by sv2v This PR adds an LEC script that compares the Verilog generated by sv2v against the original SystemVerilog. The script syn_yosys is updated to call this LEC script for each generated Verilog file.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository.
The project contains comprehensive documentation of all IPs and tools. You can either access it online or build it locally by following the steps below.
$ sudo apt install python3 python3-pip $ pip3 install --user -r python-requirements.txt
$ ./util/build_docs.py --preview
This compiles the documentation into ./opentitan-docs and starts a local server, which allows you to access the documentation at http://127.0.0.1:5500.
Have a look at CONTRIBUTING.md for guidelines how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).