)]}'
{
  "commit": "03cf29fad412aef17fb97f432461174c8a800451",
  "tree": "446bbb4ae73d183f031734ec13bc335fa6ba09d7",
  "parents": [
    "c1453e8d587af2a00434f534e76f003b085b9cc3"
  ],
  "author": {
    "name": "Nils Graf",
    "email": "nilsg@google.com",
    "time": "Wed Sep 18 16:06:17 2019 -0700"
  },
  "committer": {
    "name": "NilsGraf",
    "email": "49500697+NilsGraf@users.noreply.github.com",
    "time": "Mon Oct 14 09:07:43 2019 -0700"
  },
  "message": "[util/syn_yosys] Add LEC script to check Verilog generated by sv2v\n\nThis PR adds an LEC script that compares the Verilog generated by sv2v against the original SystemVerilog. The script syn_yosys is updated to call this LEC script for each generated Verilog file.\n",
  "tree_diff": [
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