lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
| 4 | // |
Michael Schaffner | 2608b59 | 2023-01-13 14:12:48 -0800 | [diff] [blame] | 5 | { |
| 6 | name: "rv_timer", |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 7 | human_name: "RISC-V Timer", |
Andreas Kurth | 218294b | 2023-02-07 19:03:35 +0100 | [diff] [blame] | 8 | one_line_desc: "Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers", |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 9 | one_paragraph_desc: ''' |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 10 | RISC-V Timer provides TileLink Uncached Light (TL-UL) memory-mapped registers `mtime` and `mtimecmp` which can be used as the machine-mode timer registers as defined in the RISC-V privileged spec v1.12. |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 11 | Additional parameters can be used to add optional features, such as prescaler, step increment size, threshold-triggered interrupts, additional 64-bit timers, and support for multiple independent harts. |
| 12 | ''' |
Michael Schaffner | 2608b59 | 2023-01-13 14:12:48 -0800 | [diff] [blame] | 13 | design_spec: "../doc", |
| 14 | dv_doc: "../doc/dv", |
| 15 | hw_checklist: "../doc/checklist", |
| 16 | sw_checklist: "sw/device/lib/dif/dif_rv_timer", |
| 17 | revisions: [ |
| 18 | { |
| 19 | version: "0.5", |
| 20 | life_stage: "L2", |
| 21 | design_stage: "D3", |
| 22 | verification_stage: "V3", |
| 23 | commit_id: "a4638684103da48c793301243759e9d1eb2cb9dc", |
| 24 | notes: "" |
| 25 | } |
| 26 | { |
| 27 | version: "1.0", |
| 28 | life_stage: "L1", |
| 29 | design_stage: "D3", |
| 30 | verification_stage: "V2", |
| 31 | dif_stage: "S2", |
| 32 | commit_id: "a25e162b8f91bd0ca32258c83d1d480f93327204", |
| 33 | notes: "D3 Reviewed @ 2022-07-28", |
| 34 | } |
| 35 | ] |
Rupert Swarbrick | d0cbfad | 2021-06-29 17:04:51 +0100 | [diff] [blame] | 36 | clocking: [{clock: "clk_i", reset: "rst_ni"}], |
Rupert Swarbrick | 6c83129 | 2021-02-25 17:08:53 +0000 | [diff] [blame] | 37 | bus_interfaces: [ |
| 38 | { protocol: "tlul", direction: "device" } |
| 39 | ], |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 40 | available_input_list: [ |
| 41 | ], |
| 42 | available_output_list: [ |
| 43 | ], |
| 44 | interrupt_list: [ |
Timothy Trippel | e6e9fb2 | 2021-10-13 00:51:52 +0000 | [diff] [blame] | 45 | { name: "timer_expired_hart0_timer0", |
| 46 | desc: "raised if hart0's timer0 expired (mtimecmp >= mtime)" |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 47 | }, |
| 48 | ], |
Michael Schaffner | 6fec3b5 | 2021-07-02 14:55:33 -0700 | [diff] [blame] | 49 | alert_list: [ |
| 50 | { name: "fatal_fault", |
| 51 | desc: ''' |
| 52 | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the RV_TIMER unit. |
| 53 | ''' |
| 54 | } |
| 55 | ], |
Eunchan Kim | c4873f3 | 2019-09-25 12:46:12 -0700 | [diff] [blame] | 56 | param_list: [ |
| 57 | { name: "N_HARTS", |
| 58 | desc: "Number of harts", |
| 59 | type: "int", |
| 60 | default: "1" |
| 61 | }, |
| 62 | { name: "N_TIMERS", |
| 63 | desc: "Number of timers per Hart", |
| 64 | type: "int", |
| 65 | default: "1" |
| 66 | } |
| 67 | ], |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 68 | no_auto_intr_regs: "true", |
Michael Schaffner | 1762693 | 2021-12-13 09:10:43 -0800 | [diff] [blame] | 69 | countermeasures: [ |
Eunchan Kim | a25e162 | 2022-07-29 15:54:34 -0700 | [diff] [blame] | 70 | { name: "BUS.INTEGRITY" |
Michael Schaffner | 1762693 | 2021-12-13 09:10:43 -0800 | [diff] [blame] | 71 | desc: "End-to-end bus integrity scheme." |
| 72 | } |
| 73 | ] |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 74 | regwidth: "32", |
| 75 | registers: [ |
| 76 | { multireg: { |
| 77 | name: "CTRL", |
| 78 | desc: "Control register", |
Eunchan Kim | c4873f3 | 2019-09-25 12:46:12 -0700 | [diff] [blame] | 79 | count: "N_HARTS", |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 80 | cname: "TIMER", |
| 81 | swaccess: "rw", |
| 82 | hwaccess: "hro", |
| 83 | fields: [ |
Cindy Chen | 85aca77 | 2020-02-26 14:29:56 -0800 | [diff] [blame] | 84 | { bits: "0", name: "active", |
| 85 | desc: "If 1, timer operates", |
| 86 | tags: [// prevent timer from being enabled |
| 87 | "excl:CsrNonInitTests:CsrExclWrite"] } |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 88 | ], |
| 89 | } |
| 90 | }, |
| 91 | { skipto: "0x100" }, |
Eunchan Kim | a25e162 | 2022-07-29 15:54:34 -0700 | [diff] [blame] | 92 | { multireg: { |
| 93 | name: "INTR_ENABLE0", |
| 94 | desc: "Interrupt Enable", |
| 95 | count: "N_TIMERS", |
| 96 | cname: "TIMER", |
| 97 | swaccess: "rw", |
| 98 | hwaccess: "hro", |
| 99 | fields: [ |
| 100 | { bits: "0", name: "IE", desc: "Interrupt Enable for timer" } |
| 101 | ] |
| 102 | } |
| 103 | }, // R: INTR_ENABLE0 |
| 104 | { multireg: { |
| 105 | name: "INTR_STATE0", |
| 106 | desc: "Interrupt Status", |
| 107 | count: "N_TIMERS", |
| 108 | cname: "TIMER", |
| 109 | swaccess: "rw1c", |
| 110 | hwaccess: "hrw", |
| 111 | fields: [ |
| 112 | { bits: "0", name: "IS", desc: "Interrupt status for timer", |
| 113 | tags: [// intr_state csr is affected by writes to other csrs - skip write-check |
| 114 | "excl:CsrNonInitTests:CsrExclWriteCheck"] } |
| 115 | ], |
| 116 | } |
| 117 | }, // R: INTR_STATE0 |
| 118 | { multireg: { |
| 119 | name: "INTR_TEST0", |
| 120 | desc: "Interrupt test register", |
| 121 | count: "N_TIMERS", |
| 122 | cname: "TIMER", |
| 123 | swaccess: "wo", |
| 124 | hwaccess: "hro", |
| 125 | hwext: "true", |
| 126 | hwqe: "true", |
| 127 | fields: [ |
| 128 | { bits: "0", name: "T", desc: "Interrupt test for timer", |
| 129 | tags: [// intr_test csr is WO which - it reads back 0s |
| 130 | "excl:CsrNonInitTests:CsrExclWrite"] } |
| 131 | ] |
| 132 | } |
| 133 | }, // R: INTR_TEST0 |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 134 | { name: "CFG0", |
| 135 | desc: "Configuration for Hart 0", |
| 136 | swaccess: "rw", |
| 137 | hwaccess: "hro", |
| 138 | fields: [ |
| 139 | { bits: "11:0", name: "prescale", desc: "Prescaler to generate tick" }, |
| 140 | { bits: "23:16", name: "step", resval: "0x1", desc: "Incremental value for each tick" }, |
| 141 | ], |
| 142 | }, |
| 143 | { name: "TIMER_V_LOWER0", |
| 144 | desc: "Timer value Lower", |
| 145 | swaccess: "rw", |
| 146 | hwaccess: "hrw", |
| 147 | fields: [ |
| 148 | { bits: "31:0", name: "v", desc: "Timer value [31:0]" }, |
| 149 | ], |
| 150 | }, |
| 151 | { name: "TIMER_V_UPPER0", |
| 152 | desc: "Timer value Upper", |
| 153 | swaccess: "rw", |
| 154 | hwaccess: "hrw", |
| 155 | fields: [ |
| 156 | { bits: "31:0", name: "v", desc: "Timer value [63:32]" }, |
| 157 | ], |
| 158 | }, |
| 159 | { name: "COMPARE_LOWER0_0", |
| 160 | desc: "Timer value Lower", |
| 161 | swaccess: "rw", |
| 162 | hwaccess: "hro", |
Eunchan Kim | 048702d | 2020-01-31 09:55:46 -0800 | [diff] [blame] | 163 | hwqe: "true", |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 164 | fields: [ |
| 165 | { bits: "31:0", name: "v", resval: "0xffffffff", desc: "Timer compare value [31:0]" }, |
| 166 | ], |
| 167 | }, |
| 168 | { name: "COMPARE_UPPER0_0", |
| 169 | desc: "Timer value Upper", |
| 170 | swaccess: "rw", |
| 171 | hwaccess: "hro", |
Eunchan Kim | 048702d | 2020-01-31 09:55:46 -0800 | [diff] [blame] | 172 | hwqe: "true", |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 173 | fields: [ |
| 174 | { bits: "31:0", name: "v", resval: "0xffffffff", desc: "Timer compare value [63:32]" }, |
| 175 | ], |
| 176 | }, |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 177 | ], |
| 178 | } |