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Tung Hoang38fe2332020-06-19 11:46:36 -07001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
Tung Hoang5b33cd22019-10-23 11:29:52 -07004{
5 name: "i2c"
Weicai Yanga0f1ab92020-10-01 17:57:44 -07006 import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
Cindy Chenda227f62021-06-16 10:42:42 -07007 "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
Weicai Yanga0f1ab92020-10-01 17:57:44 -07008 "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
Srikrishna Iyera463e172022-02-02 12:09:39 -08009 "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
10 "i2c_sec_cm_testplan.hjson"]
Srikrishna Iyer86169d02021-05-10 09:35:52 -070011 testpoints: [
Tung Hoanga63640e2021-02-28 15:20:22 -080012 //-----------------------------------------------
13 // Tests for I2C DUT in HOST mode
14 //-----------------------------------------------
Tung Hoang5b33cd22019-10-23 11:29:52 -070015 {
Tung Hoanga63640e2021-02-28 15:20:22 -080016 name: host_smoke
Tung Hoang38fe2332020-06-19 11:46:36 -070017 desc: '''
Tung Hoanga63640e2021-02-28 15:20:22 -080018 Smoke test in which random (rd/wr) transactions are
19 sent to the DUT and received asynchronously with scoreboard checks.
Tung Hoang5b33cd22019-10-23 11:29:52 -070020
21 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -080022 - Configure DUT/Agent to Host/Target mode respectively
23 - Enable DUT host
Tung Hoang38fe2332020-06-19 11:46:36 -070024 - Clear/Enable interrupt (if needed)
25 - Program OVRD, FDATA register
Srikrishna Iyere8713f42021-05-26 20:13:29 -070026 - Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent
27 delays
Tung Hoanga63640e2021-02-28 15:20:22 -080028 - Randomize address and data for read/write transactions sent to the agent by the DUT
Tung Hoang5b33cd22019-10-23 11:29:52 -070029
30 Checking:
Tung Hoang38fe2332020-06-19 11:46:36 -070031 - Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
32 - Read and write transfer matching
33 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070034 stage: V1
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +010035 tests: ["i2c_host_smoke"]
Tung Hoang5b33cd22019-10-23 11:29:52 -070036 }
37 {
Srikrishna Iyere8713f42021-05-26 20:13:29 -070038 name: host_error_intr
Tung Hoang7ab48ed2020-05-19 16:21:35 -070039 desc: '''
Tung Hoanga63640e2021-02-28 15:20:22 -080040 Test error interrupts are asserted by the Host DUT due to
Tung Hoangac559a02020-09-28 12:20:38 -070041 interference and unstable signals on bus.
Srikrishna Iyere8713f42021-05-26 20:13:29 -070042
Tung Hoang5b33cd22019-10-23 11:29:52 -070043 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -080044 - Configure DUT/Agent to Host/Target mode respectively
Tung Hoang333e5c62020-08-30 10:14:14 -070045 - In host transmit mode, device (target/host) forces sda or scl signal low within the
Srikrishna Iyere8713f42021-05-26 20:13:29 -070046 clock pulse of host scl that asserts `sda_interference` or `scl_interference`
47 interrupts
Tung Hoang333e5c62020-08-30 10:14:14 -070048 - In host receiving mode (data or ack bits), SDA signal is changed with the
49 clock pulse of host scl that asserts `intr_sda_unstable` interrupts
Tung Hoangac559a02020-09-28 12:20:38 -070050 - When error interrupt assertions are detected, dut, agent, and scoreboard will be
51 reset on-the-fly then new transaction can be continue programming
52
Tung Hoang5b33cd22019-10-23 11:29:52 -070053 Checking:
Tung Hoang333e5c62020-08-30 10:14:14 -070054 - Ensure all intr_scl_interference, intr_sda_interference, and
Tung Hoanga63640e2021-02-28 15:20:22 -080055 intr_sda_unstable interrupts are asserted and stay asserted until cleared
Tung Hoang333e5c62020-08-30 10:14:14 -070056 - Ensure IP operation get back normal after on-the-fly reset finished
Tung Hoang7ab48ed2020-05-19 16:21:35 -070057 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070058 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +010059 tests: ["i2c_host_error_intr"]
Tung Hoang5b33cd22019-10-23 11:29:52 -070060 }
61 {
Tung Hoanga63640e2021-02-28 15:20:22 -080062 name: host_stress_all
Tung Hoang7ab48ed2020-05-19 16:21:35 -070063 desc: '''
Tung Hoangac559a02020-09-28 12:20:38 -070064 Support vseq (context) switching with random reset in between.
Tung Hoang5b33cd22019-10-23 11:29:52 -070065
66 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -080067 - Configure DUT/Agent to Host/Target mode respectively
Tung Hoangac559a02020-09-28 12:20:38 -070068 - Combine above sequences in one test to run sequentially
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +010069 except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
Tung Hoangac559a02020-09-28 12:20:38 -070070 - Randomly add reset between each sequence
Tung Hoang5b33cd22019-10-23 11:29:52 -070071
72 Checking:
Tung Hoangac559a02020-09-28 12:20:38 -070073 - Ensure transactions are transmitted/received correctly,
74 - Ensure reset is handled correctly
Tung Hoang7ab48ed2020-05-19 16:21:35 -070075 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -070076 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +010077 tests: ["i2c_host_stress_all"]
Tung Hoangac559a02020-09-28 12:20:38 -070078 }
79 {
Tung Hoanga63640e2021-02-28 15:20:22 -080080 name: host_stress_all_with_rand_reset
Tung Hoangac559a02020-09-28 12:20:38 -070081 desc: '''
82 Support random reset in parallel with stress_all and tl_errors sequences.
83
84 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -080085 - Configure DUT/Agent to Host/Target mode respectively
Tung Hoangac559a02020-09-28 12:20:38 -070086 - Combine above sequences in one test to run sequentially
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +010087 except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
Tung Hoangac559a02020-09-28 12:20:38 -070088 - Randomly add reset within the sequences then switch to another one
89
90 Checking:
91 - Ensure transactions are transmitted/received correctly
92 - Ensure reset is handled correctly
93 '''
Jaedon Kima8a40692022-12-08 23:12:34 +000094 stage: V3
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +010095 tests: ["i2c_host_stress_all_with_rand_reset"]
Tung Hoang5b33cd22019-10-23 11:29:52 -070096 }
97 {
Tung Hoanga63640e2021-02-28 15:20:22 -080098 name: host_perf
Tung Hoang7ab48ed2020-05-19 16:21:35 -070099 desc: '''
Tung Hoanga63640e2021-02-28 15:20:22 -0800100 The Host DUT sends and receives transactions at max bandwidth.
Tung Hoang5b33cd22019-10-23 11:29:52 -0700101
102 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -0800103 - Configure DUT/Agent to Host/Target mode respectively
104 - Reduce access latency for all fifos
Srikrishna Iyere8713f42021-05-26 20:13:29 -0700105 - Issue long read/write back-to-back transactions
Tung Hoang38fe2332020-06-19 11:46:36 -0700106 - Read rx_fifo as soon as read data valid
Tung Hoange190b642020-07-12 00:34:31 -0700107 - Clear interrupt quickly
Tung Hoangac559a02020-09-28 12:20:38 -0700108
Tung Hoang5b33cd22019-10-23 11:29:52 -0700109 Checking:
Tung Hoangac559a02020-09-28 12:20:38 -0700110 - Ensure transactions are transmitted/received correctly
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700111 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700112 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100113 tests: ["i2c_host_perf"]
Tung Hoang5b33cd22019-10-23 11:29:52 -0700114 }
115 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800116 name: host_override
Tung Hoang38fe2332020-06-19 11:46:36 -0700117 desc: '''
118 Test SCL/SDA override.
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700119
120 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -0800121 - Configure DUT/Agent to Host/Target mode respectively
Tung Hoang38fe2332020-06-19 11:46:36 -0700122 - Program OVRD register
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700123
124 Checking:
Tung Hoang24752c82020-06-23 22:44:42 -0700125 - Ensure scl_o, sda_o are overridden
Tung Hoang38fe2332020-06-19 11:46:36 -0700126 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700127 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100128 tests: ["i2c_host_override"]
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700129 }
130 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800131 name: host_fifo_watermark
Tung Hoang38fe2332020-06-19 11:46:36 -0700132 desc: '''
Hoang Tung5ccfb262020-06-29 12:15:58 -0700133 Test the watermark interrupt of fmt_fifo and rx_fifo.
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700134
135 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -0800136 - Configure DUT/Agent to Host/Target mode respectively
Hoang Tung5ccfb262020-06-29 12:15:58 -0700137 - Program random fmt_fifo and rx_fifo watermark level
138 - Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700139
140 Checking:
Hoang Tung5ccfb262020-06-29 12:15:58 -0700141 - Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted
142 - Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared
143 - Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts
Tung Hoang38fe2332020-06-19 11:46:36 -0700144 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700145 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100146 tests: ["i2c_host_fifo_watermark"]
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700147 }
148 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800149 name: host_fifo_overflow
Tung Hoang02986542020-07-11 00:24:49 -0700150 desc: '''
Tung Hoanga63640e2021-02-28 15:20:22 -0800151 Test the overflow interrupt for fmt_fifo and rx_fifo.
Tung Hoang02986542020-07-11 00:24:49 -0700152
153 Stimulus:
Srikrishna Iyere8713f42021-05-26 20:13:29 -0700154 - Configure DUT/Agent to Host/Target mode respectively
155 - DUT keeps sending a number of format byte higher than the size of fmt_fifo and
156 rx_fifo depth
Tung Hoang02986542020-07-11 00:24:49 -0700157
158 Checking:
159 - Ensure excess format bytes are dropped
160 - Ensure fmt_overflow and rx_overflow interrupt are asserted
Tung Hoang02986542020-07-11 00:24:49 -0700161 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700162 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100163 tests: ["i2c_host_fifo_overflow"]
Tung Hoang02986542020-07-11 00:24:49 -0700164 }
165 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800166 name: host_fifo_reset
167 desc: '''
168 Test fmt_fifo and rx_fifo reset.
169
170 Stimulus:
171 - Configure DUT/Agent to Host/Target mode respectively
172 - Fill up the fmt_fifo with data to be sent out
173 - Reset the fifo randomly after a number of bytes shows up on fmt_fifo
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700174
175 Checking:
Tung Hoang38fe2332020-06-19 11:46:36 -0700176 - Ensure the remaining entries are not show up after fmt_fifo is reset
177 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700178 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100179 tests: ["i2c_host_fifo_reset_fmt", "i2c_host_fifo_reset_rx", "i2c_host_fifo_fmt_empty"]
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700180 }
181 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800182 name: host_fifo_full
Tung Hoang38fe2332020-06-19 11:46:36 -0700183 desc: '''
184 Test fmt_fifo and rx_fifo in full states.
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700185
186 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -0800187 - Configure DUT/Agent to Host/Target mode respectively
Tung Hoange3749bd2020-07-17 11:33:38 -0700188 - Send enough read and write requests to fmt_fifo
189 - Hold reading data from rx_fifo until rx fifo is full
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700190
191 Checking:
Tung Hoang38fe2332020-06-19 11:46:36 -0700192 - Check fifo full states by reading status register
193 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700194 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100195 tests: ["i2c_host_fifo_full"]
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700196 }
197 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800198 name: host_timeout
Tung Hoang38fe2332020-06-19 11:46:36 -0700199 desc: '''
Tung Hoanga63640e2021-02-28 15:20:22 -0800200 Test stretch_timeout interrupts.
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700201
202 Stimulus:
Tung Hoanga63640e2021-02-28 15:20:22 -0800203 - Configure DUT/Agent to Host/Target mode respectively
204 - Set timeout enable bit of TIMEOUT_CTRL register
205 - Program timeout values (higher than host scl clock pulse) into TIMEOUT_CTRL register
Srikrishna Iyere8713f42021-05-26 20:13:29 -0700206 - Configure agent to pull down target (device) scl after the bit 9 (ACK) is
207 transmitted
Tung Hoang7ab48ed2020-05-19 16:21:35 -0700208
209 Checking:
Tung Hoanga63640e2021-02-28 15:20:22 -0800210 - Ensure stretch_timeout is asserted and a correct number is received
211
Tung Hoang38fe2332020-06-19 11:46:36 -0700212 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700213 stage: V2
Jaedon Kimb55d2052022-11-28 23:57:22 +0000214 tests: ["i2c_host_stretch_timeout"]
Tung Hoang38fe2332020-06-19 11:46:36 -0700215 }
216 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800217 name: host_rx_oversample
Tung Hoang38fe2332020-06-19 11:46:36 -0700218 desc: '''
Tung Hoanga63640e2021-02-28 15:20:22 -0800219 Host mode: test oversampling on received channel.
Tung Hoang38fe2332020-06-19 11:46:36 -0700220
221 Stimulus:
222 - Use input clock to sample the target sda (sample with baud rate equal to 1)
223 - Drive scl_rx using input clock
224
225 Checking:
226 - Read rx data oversampled value and ensure it is same as driven value
227 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700228 stage: V2
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100229 tests: ["i2c_host_rx_oversample"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800230 }
231
232 //-----------------------------------------------
233 // Tests for I2C DUT in TARGET mode
234 //-----------------------------------------------
235 {
236 name: target_smoke
237 desc: '''
238 Smoke test in which random (rd/wr) transactions are
239 sent to the DUT and received asynchronously with scoreboard checks.
240
241 Stimulus:
242 - Configure DUT/Agent to Target/Host mode respectively
243 - Enable DUT target
244 - Clear/Enable interrupt (if needed)
Srikrishna Iyere8713f42021-05-26 20:13:29 -0700245 - Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent
246 delays
Tung Hoanga63640e2021-02-28 15:20:22 -0800247 - Generate random addresses which are programmed to the DUT (target)
248 and used for transaction sent by the agent (host)
249
250 Checking:
251 - Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START
252 - Read and write transfer matching
253 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700254 stage: V1
Jaedon Kim24294e02022-11-04 21:48:55 +0000255 tests: ["i2c_target_smoke"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800256 }
257 {
258 name: target_error_intr
259 desc: '''
Jaedon Kim005e5972022-12-09 14:41:04 +0000260 Test unexp_stop interrupt is asserted by the Target DUT,
Tung Hoanga63640e2021-02-28 15:20:22 -0800261
262 Stimulus:
263 - Configure DUT/Agent to Target/Host mode respectively
264 - Host agent send STOP after ACK
265
266 Checking:
267 - Ensure all acq_stop is asserted and stay asserted until cleared
268 - Ensure IP operation get back normal after on-the-fly reset finished
269 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700270 stage: V2
Jaedon Kim005e5972022-12-09 14:41:04 +0000271 tests: ["i2c_target_unexp_stop"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800272 }
273 {
274 name: target_stress_all
275 desc: '''
276 Support vseq (context) switching with random reset in between.
277
278 Stimulus:
279 - Configure DUT/Agent to Target/Host mode respectively
280 - Combine above sequences in one test to run sequentiall except csr sequence
281 - Randomly add reset between each sequence
282
283 Checking:
284 - Ensure transactions are transmitted/received correctly,
285 - Ensure reset is handled correctly
286 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700287 stage: V2
Jaedon Kim2fc3a7c2022-12-21 00:50:20 +0000288 tests: ["i2c_target_stress_all"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800289 }
290 {
291 name: target_stress_all_with_rand_reset
292 desc: '''
293 Support random reset in parallel with stress_all and tl_errors sequences.
294
295 Stimulus:
296 - Configure DUT/Agent to Target/Host mode respectively
297 - Combine above sequences in one test to run sequentially
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100298 except csr sequence
Tung Hoanga63640e2021-02-28 15:20:22 -0800299 - Randomly add reset within the sequences then switch to another one
300
301 Checking:
302 - Ensure transactions are transmitted/received correctly
303 - Ensure reset is handled correctly
304 '''
Jaedon Kimfbf63322022-12-15 19:32:43 +0000305 stage: V3
Viswanadha Bazawada74db12b2022-05-16 14:04:55 +0100306 tests: [""]
Tung Hoanga63640e2021-02-28 15:20:22 -0800307 }
308 {
309 name: target_perf
310 desc: '''
311 The Host Agent sends and receives transactions at max bandwidth.
312
313 Stimulus:
314 - Configure DUT/Agent to Target/Host mode respectively
315 - Reduce access latency for all fifos
316 - Issue long read/write back-to-back transactions
Jaedon Kimfbf63322022-12-15 19:32:43 +0000317 - Make all fifos accessible without any delay
Tung Hoanga63640e2021-02-28 15:20:22 -0800318 - Clear interrupt quickly
319
320 Checking:
321 - Ensure transactions are transmitted/received correctly
322 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700323 stage: V2
Jaedon Kimfbf63322022-12-15 19:32:43 +0000324 tests: ["i2c_target_perf"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800325 }
326 {
327 name: target_fifo_overflow
328 desc: '''
Jaedon Kim712f9582022-11-18 19:00:36 +0000329 Test the overflow interrupt for tx_fifo overflow.
Tung Hoanga63640e2021-02-28 15:20:22 -0800330
331 Stimulus:
332 - Configure DUT/Agent to Target/Host mode respectively
Jaedon Kim712f9582022-11-18 19:00:36 +0000333 - Agent keeps sending a number of format byte higher than the size of tx_fifo
Tung Hoanga63640e2021-02-28 15:20:22 -0800334 Checking:
335 - Ensure excess format bytes are dropped
Jaedon Kim712f9582022-11-18 19:00:36 +0000336 - Ensure tx_overflow interrupt are asserted
Tung Hoanga63640e2021-02-28 15:20:22 -0800337 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700338 stage: V2
Jaedon Kim712f9582022-11-18 19:00:36 +0000339 tests: ["i2c_target_tx_ovf"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800340 }
341 {
Viswanadha Bazawadaf89a2892022-05-16 12:44:53 +0100342 name: target_fifo_empty
343 desc: '''
344 Test tx_empty and tx_nonempty interrupt.
345
346 Stimulus:
347 - Configure DUT/Agent to Target/Host mode respectively
348 - Agent sends transaction to the DUT
349
350 Checking:
351 - During read transaction, ensure tx_empty interrupt is asserted when no data left
Jaedon Kim95fba942022-11-10 23:03:02 +0000352 in tx_fifo otherwise tx_empty interrupt must be de-asserted
Viswanadha Bazawadaf89a2892022-05-16 12:44:53 +0100353 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700354 stage: V2
Jaedon Kimb7c7b3f2022-11-30 04:27:10 +0000355 tests: ["i2c_target_stress_rd", "i2c_target_intr_smoke"]
Viswanadha Bazawadaf89a2892022-05-16 12:44:53 +0100356 }
357 {
Tung Hoanga63640e2021-02-28 15:20:22 -0800358 name: target_fifo_reset
359 desc: '''
360 Test tx_fifo and acq_fifo reset.
361
362 Stimulus:
363 - Configure DUT/Agent to Target/Host mode respectively
Jaedon Kim005e5972022-12-09 14:41:04 +0000364 - Run read write mixed traffic.
Jaedon Kim256bf762022-12-14 05:55:25 +0000365 - Assert reset any period between stop and the next start.
Tung Hoanga63640e2021-02-28 15:20:22 -0800366
367 Checking:
Jaedon Kim005e5972022-12-09 14:41:04 +0000368 - Ensure the remaining entries are not show up after each fifio is reset,
Tung Hoanga63640e2021-02-28 15:20:22 -0800369 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700370 stage: V2
Jaedon Kim256bf762022-12-14 05:55:25 +0000371 tests: ["i2c_target_fifo_reset_acq", "i2c_target_fifo_reset_tx"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800372 }
373 {
374 name: target_fifo_full
375 desc: '''
376 Test acq_fifo and tx_fifo in full states.
377
378 Stimulus:
379 - Configure DUT/Agent to Target/Host mode respectively
380 - Send enough read and write requests to acq_fifo
Jaedon Kim5230ce02022-11-16 17:36:17 +0000381 - Slow down acq fifo read process to trigger acq_full interrupt
Tung Hoanga63640e2021-02-28 15:20:22 -0800382
383 Checking:
384 - Check fifo full states by reading status register
385 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700386 stage: V2
Jaedon Kim5230ce02022-11-16 17:36:17 +0000387 tests: ["i2c_target_stress_wr", "i2c_target_intr_stress_wr"]
Tung Hoanga63640e2021-02-28 15:20:22 -0800388 }
389 {
390 name: target_timeout
391 desc: '''
392 Test host_timeout interrupts.
393
394 Stimulus:
395 - Configure DUT/Agent to Host/Target mode respectively
396 - Set timeout enable bit of HOST_TIMEOUT_CTRL register
397 - Agent stops sending clock during an ongoing transaction
398
399 Checking:
400 - Ensure host_timeout is asserted and a correct number is received
401
402 '''
Michael Schaffnerd1be61b2022-08-23 17:41:35 -0700403 stage: V2
Jaedon Kima8a40692022-12-08 23:12:34 +0000404 tests: ["i2c_target_timeout"]
Tung Hoang5b33cd22019-10-23 11:29:52 -0700405 }
Jaedon Kim95fba942022-11-10 23:03:02 +0000406 {
407 name: target_clock_stretch
408 desc: '''
409 Test clock stretch feature of DUT Target mode.
410 For the write and address transaction, when acq fifo is full, DUT starts to stretch clock.
411 For the read transaction, when dut receives read command, the tx fifo is empty,
412 DUT starts to stretch clock.
413 Using read / write mixed traffic, trigger stretch condition by slowing down acq / tx
414 fifo process.
415
416 Checking:
417 Ensure all read /write data received correct on the other side without dropping any data.
418 '''
419 stage: V2
420 tests: ["i2c_target_stretch"]
421 }
Jaedon Kim8635b172023-01-11 21:03:28 +0000422 {
423 name: bad_address
424 desc: '''
425 Test sends transactions with a randomized address including two legal (programmed) addresses.
426 Run this test with dut target mode.
427
428 Checking:
429 All transactions with illegal addresses should be dropped silently and should not disturb
430 transactions with legal address
431 '''
432 stage: V2
433 tests: ["i2c_target_bad_addr"]
434 }
435 {
436 name: runt_frame
437 desc: '''
438 Create tests to interrupt normal transaction by a new 'start' or reset.
439 Run those test with dut host and target mode if possible.
440
441 Checking:
442 Dut can accept a new transaction after discarding interrupted transaction.
443 '''
444 stage: V2
445 tests: ["i2c_target_hrst"]
446 }
Tung Hoang5b33cd22019-10-23 11:29:52 -0700447 ]
448}