Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 4 | { |
| 5 | name: "i2c" |
Weicai Yang | a0f1ab9 | 2020-10-01 17:57:44 -0700 | [diff] [blame] | 6 | import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", |
Cindy Chen | da227f6 | 2021-06-16 10:42:42 -0700 | [diff] [blame] | 7 | "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", |
Weicai Yang | a0f1ab9 | 2020-10-01 17:57:44 -0700 | [diff] [blame] | 8 | "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", |
Srikrishna Iyer | a463e17 | 2022-02-02 12:09:39 -0800 | [diff] [blame] | 9 | "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", |
| 10 | "i2c_sec_cm_testplan.hjson"] |
Srikrishna Iyer | 86169d0 | 2021-05-10 09:35:52 -0700 | [diff] [blame] | 11 | testpoints: [ |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 12 | //----------------------------------------------- |
| 13 | // Tests for I2C DUT in HOST mode |
| 14 | //----------------------------------------------- |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 15 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 16 | name: host_smoke |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 17 | desc: ''' |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 18 | Smoke test in which random (rd/wr) transactions are |
| 19 | sent to the DUT and received asynchronously with scoreboard checks. |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 20 | |
| 21 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 22 | - Configure DUT/Agent to Host/Target mode respectively |
| 23 | - Enable DUT host |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 24 | - Clear/Enable interrupt (if needed) |
| 25 | - Program OVRD, FDATA register |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 26 | - Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent |
| 27 | delays |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 28 | - Randomize address and data for read/write transactions sent to the agent by the DUT |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 29 | |
| 30 | Checking: |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 31 | - Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START |
| 32 | - Read and write transfer matching |
| 33 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 34 | stage: V1 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 35 | tests: ["i2c_host_smoke"] |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 36 | } |
| 37 | { |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 38 | name: host_error_intr |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 39 | desc: ''' |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 40 | Test error interrupts are asserted by the Host DUT due to |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 41 | interference and unstable signals on bus. |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 42 | |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 43 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 44 | - Configure DUT/Agent to Host/Target mode respectively |
Tung Hoang | 333e5c6 | 2020-08-30 10:14:14 -0700 | [diff] [blame] | 45 | - In host transmit mode, device (target/host) forces sda or scl signal low within the |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 46 | clock pulse of host scl that asserts `sda_interference` or `scl_interference` |
| 47 | interrupts |
Tung Hoang | 333e5c6 | 2020-08-30 10:14:14 -0700 | [diff] [blame] | 48 | - In host receiving mode (data or ack bits), SDA signal is changed with the |
| 49 | clock pulse of host scl that asserts `intr_sda_unstable` interrupts |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 50 | - When error interrupt assertions are detected, dut, agent, and scoreboard will be |
| 51 | reset on-the-fly then new transaction can be continue programming |
| 52 | |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 53 | Checking: |
Tung Hoang | 333e5c6 | 2020-08-30 10:14:14 -0700 | [diff] [blame] | 54 | - Ensure all intr_scl_interference, intr_sda_interference, and |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 55 | intr_sda_unstable interrupts are asserted and stay asserted until cleared |
Tung Hoang | 333e5c6 | 2020-08-30 10:14:14 -0700 | [diff] [blame] | 56 | - Ensure IP operation get back normal after on-the-fly reset finished |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 57 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 58 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 59 | tests: ["i2c_host_error_intr"] |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 60 | } |
| 61 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 62 | name: host_stress_all |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 63 | desc: ''' |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 64 | Support vseq (context) switching with random reset in between. |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 65 | |
| 66 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 67 | - Configure DUT/Agent to Host/Target mode respectively |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 68 | - Combine above sequences in one test to run sequentially |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 69 | except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays) |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 70 | - Randomly add reset between each sequence |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 71 | |
| 72 | Checking: |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 73 | - Ensure transactions are transmitted/received correctly, |
| 74 | - Ensure reset is handled correctly |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 75 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 76 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 77 | tests: ["i2c_host_stress_all"] |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 78 | } |
| 79 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 80 | name: host_stress_all_with_rand_reset |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 81 | desc: ''' |
| 82 | Support random reset in parallel with stress_all and tl_errors sequences. |
| 83 | |
| 84 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 85 | - Configure DUT/Agent to Host/Target mode respectively |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 86 | - Combine above sequences in one test to run sequentially |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 87 | except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays) |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 88 | - Randomly add reset within the sequences then switch to another one |
| 89 | |
| 90 | Checking: |
| 91 | - Ensure transactions are transmitted/received correctly |
| 92 | - Ensure reset is handled correctly |
| 93 | ''' |
Jaedon Kim | a8a4069 | 2022-12-08 23:12:34 +0000 | [diff] [blame] | 94 | stage: V3 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 95 | tests: ["i2c_host_stress_all_with_rand_reset"] |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 96 | } |
| 97 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 98 | name: host_perf |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 99 | desc: ''' |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 100 | The Host DUT sends and receives transactions at max bandwidth. |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 101 | |
| 102 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 103 | - Configure DUT/Agent to Host/Target mode respectively |
| 104 | - Reduce access latency for all fifos |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 105 | - Issue long read/write back-to-back transactions |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 106 | - Read rx_fifo as soon as read data valid |
Tung Hoang | e190b64 | 2020-07-12 00:34:31 -0700 | [diff] [blame] | 107 | - Clear interrupt quickly |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 108 | |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 109 | Checking: |
Tung Hoang | ac559a0 | 2020-09-28 12:20:38 -0700 | [diff] [blame] | 110 | - Ensure transactions are transmitted/received correctly |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 111 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 112 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 113 | tests: ["i2c_host_perf"] |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 114 | } |
| 115 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 116 | name: host_override |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 117 | desc: ''' |
| 118 | Test SCL/SDA override. |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 119 | |
| 120 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 121 | - Configure DUT/Agent to Host/Target mode respectively |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 122 | - Program OVRD register |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 123 | |
| 124 | Checking: |
Tung Hoang | 24752c8 | 2020-06-23 22:44:42 -0700 | [diff] [blame] | 125 | - Ensure scl_o, sda_o are overridden |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 126 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 127 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 128 | tests: ["i2c_host_override"] |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 129 | } |
| 130 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 131 | name: host_fifo_watermark |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 132 | desc: ''' |
Hoang Tung | 5ccfb26 | 2020-06-29 12:15:58 -0700 | [diff] [blame] | 133 | Test the watermark interrupt of fmt_fifo and rx_fifo. |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 134 | |
| 135 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 136 | - Configure DUT/Agent to Host/Target mode respectively |
Hoang Tung | 5ccfb26 | 2020-06-29 12:15:58 -0700 | [diff] [blame] | 137 | - Program random fmt_fifo and rx_fifo watermark level |
| 138 | - Write data quickly to fmt_fifo and rx_fifo for triggering watermark interrupts |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 139 | |
| 140 | Checking: |
Hoang Tung | 5ccfb26 | 2020-06-29 12:15:58 -0700 | [diff] [blame] | 141 | - Ensure the fmt_fifo and rx_fifo watermark interrupts are asserted |
| 142 | - Ensure the fmt_fifo and rx_fifo watermark interrupts stay asserted until cleared |
| 143 | - Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 144 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 145 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 146 | tests: ["i2c_host_fifo_watermark"] |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 147 | } |
| 148 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 149 | name: host_fifo_overflow |
Tung Hoang | 0298654 | 2020-07-11 00:24:49 -0700 | [diff] [blame] | 150 | desc: ''' |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 151 | Test the overflow interrupt for fmt_fifo and rx_fifo. |
Tung Hoang | 0298654 | 2020-07-11 00:24:49 -0700 | [diff] [blame] | 152 | |
| 153 | Stimulus: |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 154 | - Configure DUT/Agent to Host/Target mode respectively |
| 155 | - DUT keeps sending a number of format byte higher than the size of fmt_fifo and |
| 156 | rx_fifo depth |
Tung Hoang | 0298654 | 2020-07-11 00:24:49 -0700 | [diff] [blame] | 157 | |
| 158 | Checking: |
| 159 | - Ensure excess format bytes are dropped |
| 160 | - Ensure fmt_overflow and rx_overflow interrupt are asserted |
Tung Hoang | 0298654 | 2020-07-11 00:24:49 -0700 | [diff] [blame] | 161 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 162 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 163 | tests: ["i2c_host_fifo_overflow"] |
Tung Hoang | 0298654 | 2020-07-11 00:24:49 -0700 | [diff] [blame] | 164 | } |
| 165 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 166 | name: host_fifo_reset |
| 167 | desc: ''' |
| 168 | Test fmt_fifo and rx_fifo reset. |
| 169 | |
| 170 | Stimulus: |
| 171 | - Configure DUT/Agent to Host/Target mode respectively |
| 172 | - Fill up the fmt_fifo with data to be sent out |
| 173 | - Reset the fifo randomly after a number of bytes shows up on fmt_fifo |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 174 | |
| 175 | Checking: |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 176 | - Ensure the remaining entries are not show up after fmt_fifo is reset |
| 177 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 178 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 179 | tests: ["i2c_host_fifo_reset_fmt", "i2c_host_fifo_reset_rx", "i2c_host_fifo_fmt_empty"] |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 180 | } |
| 181 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 182 | name: host_fifo_full |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 183 | desc: ''' |
| 184 | Test fmt_fifo and rx_fifo in full states. |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 185 | |
| 186 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 187 | - Configure DUT/Agent to Host/Target mode respectively |
Tung Hoang | e3749bd | 2020-07-17 11:33:38 -0700 | [diff] [blame] | 188 | - Send enough read and write requests to fmt_fifo |
| 189 | - Hold reading data from rx_fifo until rx fifo is full |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 190 | |
| 191 | Checking: |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 192 | - Check fifo full states by reading status register |
| 193 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 194 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 195 | tests: ["i2c_host_fifo_full"] |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 196 | } |
| 197 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 198 | name: host_timeout |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 199 | desc: ''' |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 200 | Test stretch_timeout interrupts. |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 201 | |
| 202 | Stimulus: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 203 | - Configure DUT/Agent to Host/Target mode respectively |
| 204 | - Set timeout enable bit of TIMEOUT_CTRL register |
| 205 | - Program timeout values (higher than host scl clock pulse) into TIMEOUT_CTRL register |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 206 | - Configure agent to pull down target (device) scl after the bit 9 (ACK) is |
| 207 | transmitted |
Tung Hoang | 7ab48ed | 2020-05-19 16:21:35 -0700 | [diff] [blame] | 208 | |
| 209 | Checking: |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 210 | - Ensure stretch_timeout is asserted and a correct number is received |
| 211 | |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 212 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 213 | stage: V2 |
Jaedon Kim | b55d205 | 2022-11-28 23:57:22 +0000 | [diff] [blame] | 214 | tests: ["i2c_host_stretch_timeout"] |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 215 | } |
| 216 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 217 | name: host_rx_oversample |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 218 | desc: ''' |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 219 | Host mode: test oversampling on received channel. |
Tung Hoang | 38fe233 | 2020-06-19 11:46:36 -0700 | [diff] [blame] | 220 | |
| 221 | Stimulus: |
| 222 | - Use input clock to sample the target sda (sample with baud rate equal to 1) |
| 223 | - Drive scl_rx using input clock |
| 224 | |
| 225 | Checking: |
| 226 | - Read rx data oversampled value and ensure it is same as driven value |
| 227 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 228 | stage: V2 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 229 | tests: ["i2c_host_rx_oversample"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | //----------------------------------------------- |
| 233 | // Tests for I2C DUT in TARGET mode |
| 234 | //----------------------------------------------- |
| 235 | { |
| 236 | name: target_smoke |
| 237 | desc: ''' |
| 238 | Smoke test in which random (rd/wr) transactions are |
| 239 | sent to the DUT and received asynchronously with scoreboard checks. |
| 240 | |
| 241 | Stimulus: |
| 242 | - Configure DUT/Agent to Target/Host mode respectively |
| 243 | - Enable DUT target |
| 244 | - Clear/Enable interrupt (if needed) |
Srikrishna Iyer | e8713f4 | 2021-05-26 20:13:29 -0700 | [diff] [blame] | 245 | - Randomize I2C timing in TIMING 0-4 registers and other parameters such as TL agent |
| 246 | delays |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 247 | - Generate random addresses which are programmed to the DUT (target) |
| 248 | and used for transaction sent by the agent (host) |
| 249 | |
| 250 | Checking: |
| 251 | - Check the timing behavior of START, STOP, ACK, NACK, and "repeated" START |
| 252 | - Read and write transfer matching |
| 253 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 254 | stage: V1 |
Jaedon Kim | 24294e0 | 2022-11-04 21:48:55 +0000 | [diff] [blame] | 255 | tests: ["i2c_target_smoke"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 256 | } |
| 257 | { |
| 258 | name: target_error_intr |
| 259 | desc: ''' |
Jaedon Kim | 005e597 | 2022-12-09 14:41:04 +0000 | [diff] [blame] | 260 | Test unexp_stop interrupt is asserted by the Target DUT, |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 261 | |
| 262 | Stimulus: |
| 263 | - Configure DUT/Agent to Target/Host mode respectively |
| 264 | - Host agent send STOP after ACK |
| 265 | |
| 266 | Checking: |
| 267 | - Ensure all acq_stop is asserted and stay asserted until cleared |
| 268 | - Ensure IP operation get back normal after on-the-fly reset finished |
| 269 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 270 | stage: V2 |
Jaedon Kim | 005e597 | 2022-12-09 14:41:04 +0000 | [diff] [blame] | 271 | tests: ["i2c_target_unexp_stop"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 272 | } |
| 273 | { |
| 274 | name: target_stress_all |
| 275 | desc: ''' |
| 276 | Support vseq (context) switching with random reset in between. |
| 277 | |
| 278 | Stimulus: |
| 279 | - Configure DUT/Agent to Target/Host mode respectively |
| 280 | - Combine above sequences in one test to run sequentiall except csr sequence |
| 281 | - Randomly add reset between each sequence |
| 282 | |
| 283 | Checking: |
| 284 | - Ensure transactions are transmitted/received correctly, |
| 285 | - Ensure reset is handled correctly |
| 286 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 287 | stage: V2 |
Jaedon Kim | 2fc3a7c | 2022-12-21 00:50:20 +0000 | [diff] [blame] | 288 | tests: ["i2c_target_stress_all"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 289 | } |
| 290 | { |
| 291 | name: target_stress_all_with_rand_reset |
| 292 | desc: ''' |
| 293 | Support random reset in parallel with stress_all and tl_errors sequences. |
| 294 | |
| 295 | Stimulus: |
| 296 | - Configure DUT/Agent to Target/Host mode respectively |
| 297 | - Combine above sequences in one test to run sequentially |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 298 | except csr sequence |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 299 | - Randomly add reset within the sequences then switch to another one |
| 300 | |
| 301 | Checking: |
| 302 | - Ensure transactions are transmitted/received correctly |
| 303 | - Ensure reset is handled correctly |
| 304 | ''' |
Jaedon Kim | fbf6332 | 2022-12-15 19:32:43 +0000 | [diff] [blame] | 305 | stage: V3 |
Viswanadha Bazawada | 74db12b | 2022-05-16 14:04:55 +0100 | [diff] [blame] | 306 | tests: [""] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 307 | } |
| 308 | { |
| 309 | name: target_perf |
| 310 | desc: ''' |
| 311 | The Host Agent sends and receives transactions at max bandwidth. |
| 312 | |
| 313 | Stimulus: |
| 314 | - Configure DUT/Agent to Target/Host mode respectively |
| 315 | - Reduce access latency for all fifos |
| 316 | - Issue long read/write back-to-back transactions |
Jaedon Kim | fbf6332 | 2022-12-15 19:32:43 +0000 | [diff] [blame] | 317 | - Make all fifos accessible without any delay |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 318 | - Clear interrupt quickly |
| 319 | |
| 320 | Checking: |
| 321 | - Ensure transactions are transmitted/received correctly |
| 322 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 323 | stage: V2 |
Jaedon Kim | fbf6332 | 2022-12-15 19:32:43 +0000 | [diff] [blame] | 324 | tests: ["i2c_target_perf"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 325 | } |
| 326 | { |
| 327 | name: target_fifo_overflow |
| 328 | desc: ''' |
Jaedon Kim | 712f958 | 2022-11-18 19:00:36 +0000 | [diff] [blame] | 329 | Test the overflow interrupt for tx_fifo overflow. |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 330 | |
| 331 | Stimulus: |
| 332 | - Configure DUT/Agent to Target/Host mode respectively |
Jaedon Kim | 712f958 | 2022-11-18 19:00:36 +0000 | [diff] [blame] | 333 | - Agent keeps sending a number of format byte higher than the size of tx_fifo |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 334 | Checking: |
| 335 | - Ensure excess format bytes are dropped |
Jaedon Kim | 712f958 | 2022-11-18 19:00:36 +0000 | [diff] [blame] | 336 | - Ensure tx_overflow interrupt are asserted |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 337 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 338 | stage: V2 |
Jaedon Kim | 712f958 | 2022-11-18 19:00:36 +0000 | [diff] [blame] | 339 | tests: ["i2c_target_tx_ovf"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 340 | } |
| 341 | { |
Viswanadha Bazawada | f89a289 | 2022-05-16 12:44:53 +0100 | [diff] [blame] | 342 | name: target_fifo_empty |
| 343 | desc: ''' |
| 344 | Test tx_empty and tx_nonempty interrupt. |
| 345 | |
| 346 | Stimulus: |
| 347 | - Configure DUT/Agent to Target/Host mode respectively |
| 348 | - Agent sends transaction to the DUT |
| 349 | |
| 350 | Checking: |
| 351 | - During read transaction, ensure tx_empty interrupt is asserted when no data left |
Jaedon Kim | 95fba94 | 2022-11-10 23:03:02 +0000 | [diff] [blame] | 352 | in tx_fifo otherwise tx_empty interrupt must be de-asserted |
Viswanadha Bazawada | f89a289 | 2022-05-16 12:44:53 +0100 | [diff] [blame] | 353 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 354 | stage: V2 |
Jaedon Kim | b7c7b3f | 2022-11-30 04:27:10 +0000 | [diff] [blame] | 355 | tests: ["i2c_target_stress_rd", "i2c_target_intr_smoke"] |
Viswanadha Bazawada | f89a289 | 2022-05-16 12:44:53 +0100 | [diff] [blame] | 356 | } |
| 357 | { |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 358 | name: target_fifo_reset |
| 359 | desc: ''' |
| 360 | Test tx_fifo and acq_fifo reset. |
| 361 | |
| 362 | Stimulus: |
| 363 | - Configure DUT/Agent to Target/Host mode respectively |
Jaedon Kim | 005e597 | 2022-12-09 14:41:04 +0000 | [diff] [blame] | 364 | - Run read write mixed traffic. |
Jaedon Kim | 256bf76 | 2022-12-14 05:55:25 +0000 | [diff] [blame] | 365 | - Assert reset any period between stop and the next start. |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 366 | |
| 367 | Checking: |
Jaedon Kim | 005e597 | 2022-12-09 14:41:04 +0000 | [diff] [blame] | 368 | - Ensure the remaining entries are not show up after each fifio is reset, |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 369 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 370 | stage: V2 |
Jaedon Kim | 256bf76 | 2022-12-14 05:55:25 +0000 | [diff] [blame] | 371 | tests: ["i2c_target_fifo_reset_acq", "i2c_target_fifo_reset_tx"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 372 | } |
| 373 | { |
| 374 | name: target_fifo_full |
| 375 | desc: ''' |
| 376 | Test acq_fifo and tx_fifo in full states. |
| 377 | |
| 378 | Stimulus: |
| 379 | - Configure DUT/Agent to Target/Host mode respectively |
| 380 | - Send enough read and write requests to acq_fifo |
Jaedon Kim | 5230ce0 | 2022-11-16 17:36:17 +0000 | [diff] [blame] | 381 | - Slow down acq fifo read process to trigger acq_full interrupt |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 382 | |
| 383 | Checking: |
| 384 | - Check fifo full states by reading status register |
| 385 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 386 | stage: V2 |
Jaedon Kim | 5230ce0 | 2022-11-16 17:36:17 +0000 | [diff] [blame] | 387 | tests: ["i2c_target_stress_wr", "i2c_target_intr_stress_wr"] |
Tung Hoang | a63640e | 2021-02-28 15:20:22 -0800 | [diff] [blame] | 388 | } |
| 389 | { |
| 390 | name: target_timeout |
| 391 | desc: ''' |
| 392 | Test host_timeout interrupts. |
| 393 | |
| 394 | Stimulus: |
| 395 | - Configure DUT/Agent to Host/Target mode respectively |
| 396 | - Set timeout enable bit of HOST_TIMEOUT_CTRL register |
| 397 | - Agent stops sending clock during an ongoing transaction |
| 398 | |
| 399 | Checking: |
| 400 | - Ensure host_timeout is asserted and a correct number is received |
| 401 | |
| 402 | ''' |
Michael Schaffner | d1be61b | 2022-08-23 17:41:35 -0700 | [diff] [blame] | 403 | stage: V2 |
Jaedon Kim | a8a4069 | 2022-12-08 23:12:34 +0000 | [diff] [blame] | 404 | tests: ["i2c_target_timeout"] |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 405 | } |
Jaedon Kim | 95fba94 | 2022-11-10 23:03:02 +0000 | [diff] [blame] | 406 | { |
| 407 | name: target_clock_stretch |
| 408 | desc: ''' |
| 409 | Test clock stretch feature of DUT Target mode. |
| 410 | For the write and address transaction, when acq fifo is full, DUT starts to stretch clock. |
| 411 | For the read transaction, when dut receives read command, the tx fifo is empty, |
| 412 | DUT starts to stretch clock. |
| 413 | Using read / write mixed traffic, trigger stretch condition by slowing down acq / tx |
| 414 | fifo process. |
| 415 | |
| 416 | Checking: |
| 417 | Ensure all read /write data received correct on the other side without dropping any data. |
| 418 | ''' |
| 419 | stage: V2 |
| 420 | tests: ["i2c_target_stretch"] |
| 421 | } |
Jaedon Kim | 8635b17 | 2023-01-11 21:03:28 +0000 | [diff] [blame] | 422 | { |
| 423 | name: bad_address |
| 424 | desc: ''' |
| 425 | Test sends transactions with a randomized address including two legal (programmed) addresses. |
| 426 | Run this test with dut target mode. |
| 427 | |
| 428 | Checking: |
| 429 | All transactions with illegal addresses should be dropped silently and should not disturb |
| 430 | transactions with legal address |
| 431 | ''' |
| 432 | stage: V2 |
| 433 | tests: ["i2c_target_bad_addr"] |
| 434 | } |
| 435 | { |
| 436 | name: runt_frame |
| 437 | desc: ''' |
| 438 | Create tests to interrupt normal transaction by a new 'start' or reset. |
| 439 | Run those test with dut host and target mode if possible. |
| 440 | |
| 441 | Checking: |
| 442 | Dut can accept a new transaction after discarding interrupted transaction. |
| 443 | ''' |
| 444 | stage: V2 |
| 445 | tests: ["i2c_target_hrst"] |
| 446 | } |
Tung Hoang | 5b33cd2 | 2019-10-23 11:29:52 -0700 | [diff] [blame] | 447 | ] |
| 448 | } |