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Pirmin Vogel99f09892019-09-10 14:55:54 +01001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// AES top-level wrapper
6
Greg Chadwickcf423082020-02-05 16:52:23 +00007`include "prim_assert.sv"
8
Pirmin Vogel0193aba2020-08-17 15:10:57 +02009module aes
10 import aes_pkg::*;
11 import aes_reg_pkg::*;
12#(
Pirmin Vogel73804152020-09-16 17:24:00 +020013 parameter bit AES192Enable = 1, // Can be 0 (disable), or 1 (enable).
Pirmin Vogel2e6a6c62021-03-23 15:43:08 +010014 parameter bit Masking = 1, // Can be 0 (no masking), or
Pirmin Vogel73804152020-09-16 17:24:00 +020015 // 1 (first-order masking) of the cipher
16 // core. Masking requires the use of a
17 // masked S-Box, see SBoxImpl parameter.
Pirmin Vogel2e6a6c62021-03-23 15:43:08 +010018 parameter sbox_impl_e SBoxImpl = SBoxImplDom, // See aes_pkg.sv
Pirmin Vogel73804152020-09-16 17:24:00 +020019 parameter int unsigned SecStartTriggerDelay = 0, // Manual start trigger delay, useful for
20 // SCA measurements. A value of e.g. 40
21 // allows the processor to go into sleep
22 // before AES starts operation.
Pirmin Vogel4429c362020-10-02 17:54:11 +020023 parameter bit SecAllowForcingMasks = 0, // Allow forcing masks to 0 using
24 // FORCE_ZERO_MASK bit in Control Register.
25 // Useful for SCA only.
Pirmin Vogel95cea452021-03-02 08:54:01 +010026 parameter bit SecSkipPRNGReseeding = 0, // The current SCA setup doesn't provide enough
27 // resources to implement the infrastucture
28 // required for PRNG reseeding (CSRNG, EDN).
29 // To enable SCA resistance evaluations, we
30 // need to skip reseeding requests.
31 // Useful for SCA only.
Pirmin Vogel62f79b82020-12-08 11:58:48 +010032 parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
33 parameter clearing_lfsr_seed_t RndCnstClearingLfsrSeed = RndCnstClearingLfsrSeedDefault,
34 parameter clearing_lfsr_perm_t RndCnstClearingLfsrPerm = RndCnstClearingLfsrPermDefault,
Pirmin Vogel116ecac2021-03-19 11:21:42 +010035 parameter clearing_lfsr_perm_t RndCnstClearingSharePerm = RndCnstClearingSharePermDefault,
Pirmin Vogel62f79b82020-12-08 11:58:48 +010036 parameter masking_lfsr_seed_t RndCnstMaskingLfsrSeed = RndCnstMaskingLfsrSeedDefault,
37 parameter mskg_chunk_lfsr_perm_t RndCnstMskgChunkLfsrPerm = RndCnstMskgChunkLfsrPermDefault
Pirmin Vogel99f09892019-09-10 14:55:54 +010038) (
Pirmin Vogel0799dba2020-09-18 14:43:35 +020039 input logic clk_i,
40 input logic rst_ni,
Timothy Chene83d30f2021-07-22 18:19:39 -070041 input logic rst_shadowed_ni,
Pirmin Vogel99f09892019-09-10 14:55:54 +010042
Pirmin Vogela2d411d2020-07-13 17:33:42 +020043 // Idle indicator for clock manager
Pirmin Vogel0799dba2020-09-18 14:43:35 +020044 output logic idle_o,
Pirmin Vogela2d411d2020-07-13 17:33:42 +020045
Pirmin Vogel144ca842021-02-26 15:46:43 +010046 // Life cycle
47 input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i,
48
Pirmin Vogel95cea452021-03-02 08:54:01 +010049 // Entropy distribution network (EDN) interface
50 input logic clk_edn_i,
51 input logic rst_edn_ni,
52 output edn_pkg::edn_req_t edn_o,
53 input edn_pkg::edn_rsp_t edn_i,
54
Pirmin Vogel992f9332021-09-08 09:02:18 +020055 // Key manager (keymgr) key sideload interface
56 input keymgr_pkg::hw_key_req_t keymgr_key_i,
57
Pirmin Vogel96386a12020-03-30 17:56:12 +020058 // Bus interface
Pirmin Vogel0799dba2020-09-18 14:43:35 +020059 input tlul_pkg::tl_h2d_t tl_i,
60 output tlul_pkg::tl_d2h_t tl_o,
Pirmin Vogelbe4bcb72020-04-17 14:43:45 +020061
62 // Alerts
Pirmin Vogel4a6b06b2020-07-20 15:54:49 +020063 input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
64 output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o
Pirmin Vogel99f09892019-09-10 14:55:54 +010065);
66
Pirmin Vogel95cea452021-03-02 08:54:01 +010067 localparam int unsigned EntropyWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
Pirmin Vogel99f09892019-09-10 14:55:54 +010068
Pirmin Vogel95cea452021-03-02 08:54:01 +010069 // Signals
70 aes_reg2hw_t reg2hw;
71 aes_hw2reg_t hw2reg;
72
73 logic [NumAlerts-1:0] alert;
Cindy Chenf309ea52021-04-01 18:16:57 -070074 lc_ctrl_pkg::lc_tx_t lc_escalate_en;
Pirmin Vogelbe4bcb72020-04-17 14:43:45 +020075
Pirmin Vogel95cea452021-03-02 08:54:01 +010076 logic edn_req;
77 logic edn_ack;
78 logic [EntropyWidth-1:0] edn_data;
79 logic unused_edn_fips;
80 logic entropy_clearing_req, entropy_masking_req;
81 logic entropy_clearing_ack, entropy_masking_ack;
82
83 ////////////
84 // Inputs //
85 ////////////
86
87 // Register interface
Michael Schaffner2f0c4202021-06-04 18:09:59 -070088 logic intg_err_alert;
Weicai Yang9f6311f2020-06-09 16:04:35 -070089 aes_reg_top u_reg (
Pirmin Vogel99f09892019-09-10 14:55:54 +010090 .clk_i,
91 .rst_ni,
92 .tl_i,
93 .tl_o,
94 .reg2hw,
Pirmin Vogel49f36532019-10-06 14:48:26 +010095 .hw2reg,
Michael Schaffner2f0c4202021-06-04 18:09:59 -070096 .intg_err_o(intg_err_alert),
Pirmin Vogel3e220242019-10-18 15:42:10 +010097 .devmode_i(1'b1)
Pirmin Vogel99f09892019-09-10 14:55:54 +010098 );
99
Pirmin Vogel95cea452021-03-02 08:54:01 +0100100 // Synchronize life cycle input
Pirmin Vogel144ca842021-02-26 15:46:43 +0100101 prim_lc_sync #(
102 .NumCopies (1)
103 ) u_prim_lc_sync (
104 .clk_i,
105 .rst_ni,
106 .lc_en_i ( lc_escalate_en_i ),
107 .lc_en_o ( lc_escalate_en )
108 );
109
Pirmin Vogel95cea452021-03-02 08:54:01 +0100110 // Synchronize EDN interface
111 prim_sync_reqack_data #(
112 .Width(EntropyWidth),
113 .DataSrc2Dst(1'b0),
114 .DataReg(1'b0)
115 ) u_prim_sync_reqack_data (
Pirmin Vogel231f7722021-07-16 11:33:07 +0200116 .clk_src_i ( clk_i ),
117 .rst_src_ni ( rst_ni ),
118 .clk_dst_i ( clk_edn_i ),
119 .rst_dst_ni ( rst_edn_ni ),
120 .req_chk_i ( lc_escalate_en == lc_ctrl_pkg::Off ),
121 .src_req_i ( edn_req ),
122 .src_ack_o ( edn_ack ),
123 .dst_req_o ( edn_o.edn_req ),
124 .dst_ack_i ( edn_i.edn_ack ),
125 .data_i ( edn_i.edn_bus ),
126 .data_o ( edn_data )
Pirmin Vogel95cea452021-03-02 08:54:01 +0100127 );
128 // We don't track whether the entropy is pre-FIPS or not inside AES.
129 assign unused_edn_fips = edn_i.edn_fips;
130
131 //////////
132 // Core //
133 //////////
134
135 // Entropy distribution
136 // Internally, we have up to two PRNGs that share the EDN interface for reseeding. Here, we just
137 // arbitrate the requests. Upsizing of the entropy to the correct width is performed inside the
138 // PRNGs.
139 // Reseed operations for the clearing PRNG are initiated by software. Reseed operations for the
140 // masking PRNG are automatically initiated. Reseeding operations of the two PRNGs are not
141 // expected to take place simultaneously.
142 assign edn_req = entropy_clearing_req | entropy_masking_req;
143 // Only forward ACK to PRNG currently requesting entropy. Give higher priority to clearing PRNG.
144 assign entropy_clearing_ack = entropy_clearing_req & edn_ack;
145 assign entropy_masking_ack = ~entropy_clearing_req & entropy_masking_req & edn_ack;
146
147 // AES core
Pirmin Vogel99f09892019-09-10 14:55:54 +0100148 aes_core #(
Pirmin Vogel62f79b82020-12-08 11:58:48 +0100149 .AES192Enable ( AES192Enable ),
150 .Masking ( Masking ),
151 .SBoxImpl ( SBoxImpl ),
152 .SecStartTriggerDelay ( SecStartTriggerDelay ),
153 .SecAllowForcingMasks ( SecAllowForcingMasks ),
Pirmin Vogel95cea452021-03-02 08:54:01 +0100154 .SecSkipPRNGReseeding ( SecSkipPRNGReseeding ),
155 .EntropyWidth ( EntropyWidth ),
Pirmin Vogel62f79b82020-12-08 11:58:48 +0100156 .RndCnstClearingLfsrSeed ( RndCnstClearingLfsrSeed ),
157 .RndCnstClearingLfsrPerm ( RndCnstClearingLfsrPerm ),
Pirmin Vogel116ecac2021-03-19 11:21:42 +0100158 .RndCnstClearingSharePerm ( RndCnstClearingSharePerm ),
Pirmin Vogel62f79b82020-12-08 11:58:48 +0100159 .RndCnstMaskingLfsrSeed ( RndCnstMaskingLfsrSeed ),
160 .RndCnstMskgChunkLfsrPerm ( RndCnstMskgChunkLfsrPerm )
Pirmin Vogel4a6b06b2020-07-20 15:54:49 +0200161 ) u_aes_core (
Pirmin Vogel95cea452021-03-02 08:54:01 +0100162 .clk_i ( clk_i ),
163 .rst_ni ( rst_ni ),
Timothy Chene83d30f2021-07-22 18:19:39 -0700164 .rst_shadowed_ni ( rst_shadowed_ni ),
Pirmin Vogel95cea452021-03-02 08:54:01 +0100165 .entropy_clearing_req_o ( entropy_clearing_req ),
166 .entropy_clearing_ack_i ( entropy_clearing_ack ),
167 .entropy_clearing_i ( edn_data ),
168 .entropy_masking_req_o ( entropy_masking_req ),
169 .entropy_masking_ack_i ( entropy_masking_ack ),
170 .entropy_masking_i ( edn_data ),
Pirmin Vogel0799dba2020-09-18 14:43:35 +0200171
Pirmin Vogel992f9332021-09-08 09:02:18 +0200172 .keymgr_key_i ( keymgr_key_i ),
173
Cindy Chenf309ea52021-04-01 18:16:57 -0700174 .lc_escalate_en_i ( lc_escalate_en ),
Pirmin Vogel144ca842021-02-26 15:46:43 +0100175
Michael Schaffner2f0c4202021-06-04 18:09:59 -0700176 .intg_err_alert_i ( intg_err_alert ),
Pirmin Vogel95cea452021-03-02 08:54:01 +0100177 .alert_recov_o ( alert[0] ),
178 .alert_fatal_o ( alert[1] ),
Pirmin Vogel0799dba2020-09-18 14:43:35 +0200179
Pirmin Vogel95cea452021-03-02 08:54:01 +0100180 .reg2hw ( reg2hw ),
181 .hw2reg ( hw2reg )
Pirmin Vogel96386a12020-03-30 17:56:12 +0200182 );
183
Pirmin Vogela2d411d2020-07-13 17:33:42 +0200184 assign idle_o = hw2reg.status.idle.d;
185
Pirmin Vogel95cea452021-03-02 08:54:01 +0100186 ////////////
187 // Alerts //
188 ////////////
189
Michael Schaffner4c650142020-10-26 20:08:19 -0700190 logic [NumAlerts-1:0] alert_test;
191 assign alert_test = {
Pirmin Vogel4c22cf22021-01-21 13:44:05 +0100192 reg2hw.alert_test.fatal_fault.q &
193 reg2hw.alert_test.fatal_fault.qe,
194 reg2hw.alert_test.recov_ctrl_update_err.q &
195 reg2hw.alert_test.recov_ctrl_update_err.qe
Michael Schaffner4c650142020-10-26 20:08:19 -0700196 };
197
Pirmin Vogelbe4bcb72020-04-17 14:43:45 +0200198 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
199 prim_alert_sender #(
Michael Schaffner8d279502021-01-15 20:08:28 -0800200 .AsyncOn(AlertAsyncOn[i]),
Pirmin Vogel4c22cf22021-01-21 13:44:05 +0100201 .IsFatal(i)
Michael Schaffner8d279502021-01-15 20:08:28 -0800202 ) u_prim_alert_sender (
203 .clk_i,
204 .rst_ni,
205 .alert_test_i ( alert_test[i] ),
206 .alert_req_i ( alert[i] ),
207 .alert_ack_o ( ),
208 .alert_state_o ( ),
209 .alert_rx_i ( alert_rx_i[i] ),
210 .alert_tx_o ( alert_tx_o[i] )
Pirmin Vogelbe4bcb72020-04-17 14:43:45 +0200211 );
212 end
213
Pirmin Vogel95cea452021-03-02 08:54:01 +0100214 ////////////////
215 // Assertions //
216 ////////////////
217
Pirmin Vogelfde954f2019-10-18 15:45:44 +0100218 // All outputs should have a known value after reset
Greg Chadwick46ede4b2020-01-14 12:46:39 +0000219 `ASSERT_KNOWN(TlODValidKnown, tl_o.d_valid)
220 `ASSERT_KNOWN(TlOAReadyKnown, tl_o.a_ready)
Pirmin Vogela2d411d2020-07-13 17:33:42 +0200221 `ASSERT_KNOWN(IdleKnown, idle_o)
Pirmin Vogel95cea452021-03-02 08:54:01 +0100222 `ASSERT_KNOWN(EdnReqKnown, edn_o)
Pirmin Vogelbe4bcb72020-04-17 14:43:45 +0200223 `ASSERT_KNOWN(AlertTxKnown, alert_tx_o)
Pirmin Vogelfde954f2019-10-18 15:45:44 +0100224
Pirmin Vogel99f09892019-09-10 14:55:54 +0100225endmodule