hw/ip/pwm/data/pwm_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
    name: "pwm"
    import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                       "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                       "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                       "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                       "pwm_sec_cm_testplan.hjson"],
    testpoints: [
        {
            name: smoke
            desc: '''
            pwm_smoke tests pulse and blink mode for a single channel

            Stimulus:
              - configure the envionment for one PWM channel
              - program the duty cycle a and b values
              - configure  the ClkDiv and Resn

            Checking:
              - ensure pulses are generated correctly in pulse or blink mode

            '''
      stage: V1
      tests: ["pwm_smoke"]
    }
    {
      name: dutycycle
      desc: '''
            Verify different duty cycle settings in Pulse, Blink and Heart Beat mode.

            '''
      stage: V2
      tests: ["pwm_rand_output"]
    }
    {
      name: pulse
      desc: '''
            Verify the pulse mode of the PWM
            by de-asserting blink_en field in the PWM_PARAM register
            '''
      stage: V2
      tests: ["pwm_rand_output"]
    }
    {
      name: blink
      desc: '''
            Verify the blink mode of the PWM
            by asserting the blink_en field in the PWM_PARAM register
            '''
      stage: V2
      tests: ["pwm_rand_output"]
    }
    {
      name: heartbeat
      desc: '''
            Verify the Heart Beat mode of the PWM
            by asserting the blink_en and HTBT field in the PWM_PARAM register
            '''
        stage: V2
        tests: ["pwm_rand_output"]
    }
   {
      name: resolution
      desc: '''
            Verify the PWM generates correct duty cycle for different resolution settings
            '''
        stage: V2
        tests: ["pwm_rand_output"]
    }
    {
      name: multi_channel
      desc: '''
            Verifies that PWM correctly generates pulses on multiple channels concurrently
            '''
        stage: V2
        tests: ["pwm_rand_output"]
    }
    {
      name: polarity
      desc: '''
            Verify that the polarity of the pulse can be inverted by setting the invert channel bit in the invert register
            '''
        stage: V2
        tests: ["pwm_rand_output"]
    }
    {
      name: phase
      desc: '''
            Check that the relative phase between pulses matches the setting in the phase_delay field in the PWM_PARAM register.
            '''
        stage: V2
        tests: ["pwm_rand_output"]
    }
    {
      name: lowpower
      desc: '''
            Verify the PWM can continue when the chip is in low power mode.
            Stimulus:
                - start PWM on one or more channels
                - stop the TL UL clock

            Checks:
                - Ensure pulses are still generated when in LP mode
            '''
        stage: V2
        tests: ["pwm_rand_output"]
    }
    {
      name: perf
      desc: '''
            Checking ip operation at min/max bandwidth

            Stimulus:
                - Program timing registers (CLK_DIV, DC_RESN) to high/low values (slow/fast data rate)
                - Program other required registers for pwm operation
                - Start pwm channels

            Checks:
                - Ensure the output pulses are correctly modulated for all channels
            '''
      stage: V2
      tests: ["pwm_perf"]
    }
    {
      name: stress_all
      desc: '''
            Combine above sequences in one test then randomly select for running

            Stimulus:
                - Start sequences and randomly add reset between each sequence

            Checking:
                - All sequences should be finished and checked by the scoreboard
            '''
      stage: V2
      tests: ["pwm_stress_all"]
    }
  ]

 covergroups: [
    {
     name: regwen_cg
      desc: '''
            Covers that an attempt to write wen REG enable was made and was unsuccessful
            '''
    }
    {
     name: cfg_cg
      desc: '''
            Covers that valid settings for the PWM.CFG register has been tested.
            This includes values for:
                - clk_div
                - dc_resn
                - cntr_en
            '''
    }
    {
     name: pwm_en_cg
      desc: '''
            Covers that both runs with a single PWM channel and multiple channels has been tested.
            Verifies both when the channels are enabled for parallel behavior (activated at the same time)
            and activated individually
            '''
    }
    {
     name: invert_cg
      desc: '''
            Covers that channels have been tested with different polarity
            Also cover that a mix channels with invert enabled and disabled concurrently have been tested.
                '''
    }
    {
     name: pwm_param_cg
      desc: '''
            Covers that both pulse, blink and heart beat mode have been tested.
            Also covers that.
            - various phase delays have been tested
            - different delays on different concurrent channels
            '''
    }
    {
     name: duty_cycle_cg
      desc: '''
            Covers that a good range of combinations of values for A and B have been send.
            Also cover that multiple channels can run concurrently with different settings for A and B.
            Cover these cases:
                - A > B
                - A < B
                - A == B
            '''
    }
    {
     name: blink_param_cg
      desc: '''
            Covers that a good range of combinations of values for X and Y have been seend.
            Also cover that multiple channels can run concurrently with different settings for X and Y.
            '''
    }
    {
     name: lowpower_cg
      desc: '''
            Covers that the DUT will continue to produce pulses with TL clock disabled (low power mode)
            '''
    }
    {
     name: clock_cg
      desc: '''
            Cover that a range of frequencies have been tested for the PWM clock including a clock that matches the TL clk.
            '''
    }
    {
     name: overwrite_conf_cg
      desc: '''
            Cover that a the PWM configuration cannot be altered while a channel is active
            '''
    }
  ]
}