[i2c] Wire up integrity alert
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
index 148d67a..37789c4 100644
--- a/hw/ip/i2c/data/i2c.hjson
+++ b/hw/ip/i2c/data/i2c.hjson
@@ -62,7 +62,14 @@
{ name: "host_timeout"
desc: "raised if the host stops sending the clock during an ongoing transaction."
}
- ]
+ ],
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the I2C unit.
+ '''
+ }
+ ],
// REGISTER definition
regwidth: "32"
diff --git a/hw/ip/i2c/dv/env/i2c_env_cfg.sv b/hw/ip/i2c/dv/env/i2c_env_cfg.sv
index 032384e..8c7ec61 100644
--- a/hw/ip/i2c/dv/env/i2c_env_cfg.sv
+++ b/hw/ip/i2c/dv/env/i2c_env_cfg.sv
@@ -20,6 +20,7 @@
`uvm_object_new
virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+ list_of_alerts = i2c_env_pkg::LIST_OF_ALERTS;
super.initialize(csr_base_addr);
// create i2c_agent_cfg
diff --git a/hw/ip/i2c/dv/env/i2c_env_pkg.sv b/hw/ip/i2c/dv/env/i2c_env_pkg.sv
index 2fbd624..5d73f7b 100644
--- a/hw/ip/i2c/dv/env/i2c_env_pkg.sv
+++ b/hw/ip/i2c/dv/env/i2c_env_pkg.sv
@@ -48,6 +48,10 @@
parameter uint I2C_FMT_FIFO_DEPTH = 32;
parameter uint I2C_RX_FIFO_DEPTH = 32;
+ // alerts
+ parameter uint NUM_ALERTS = 1;
+ parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
+
// package sources
`include "i2c_seq_cfg.sv"
`include "i2c_env_cfg.sv"
diff --git a/hw/ip/i2c/dv/tb/tb.sv b/hw/ip/i2c/dv/tb/tb.sv
index 9827595..666ee33 100644
--- a/hw/ip/i2c/dv/tb/tb.sv
+++ b/hw/ip/i2c/dv/tb/tb.sv
@@ -48,6 +48,8 @@
tl_if tl_if(.clk(clk_i), .rst_n(rst_ni));
i2c_if i2c_if();
+ `DV_ALERT_IF_CONNECT
+
// dut
i2c dut (
.clk_i (clk_i ),
@@ -56,6 +58,9 @@
.tl_i (tl_if.h2d ),
.tl_o (tl_if.d2h ),
+ .alert_rx_i (alert_rx ),
+ .alert_tx_o (alert_tx ),
+
.cio_scl_i (cio_scl_i ),
.cio_scl_o (cio_scl_o ),
.cio_scl_en_o (cio_scl_en_o ),
diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv
index 03038e6..8f0d084 100644
--- a/hw/ip/i2c/rtl/i2c.sv
+++ b/hw/ip/i2c/rtl/i2c.sv
@@ -6,7 +6,11 @@
`include "prim_assert.sv"
-module i2c (
+module i2c
+ import i2c_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
input clk_i,
input rst_ni,
@@ -14,6 +18,10 @@
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
// Generic IO
input cio_scl_i,
output logic cio_scl_o,
@@ -46,6 +54,8 @@
i2c_reg2hw_t reg2hw;
i2c_hw2reg_t hw2reg;
+ logic [NumAlerts-1:0] alert_test, alerts;
+
i2c_reg_top u_reg (
.clk_i,
.rst_ni,
@@ -53,10 +63,31 @@
.tl_o,
.reg2hw,
.hw2reg,
- .intg_err_o(),
+ .intg_err_o(alerts[0]),
.devmode_i(1'b1)
);
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[0] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
logic scl_int;
logic sda_int;
@@ -101,6 +132,7 @@
`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
`ASSERT_KNOWN(CioSclKnownO_A, cio_scl_o)
`ASSERT_KNOWN(CioSclEnKnownO_A, cio_scl_en_o)
`ASSERT_KNOWN(CioSdaKnownO_A, cio_sda_o)
diff --git a/hw/ip/i2c/rtl/i2c_reg_pkg.sv b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
index 78f84c1..0f0b652 100644
--- a/hw/ip/i2c/rtl/i2c_reg_pkg.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
@@ -6,6 +6,9 @@
package i2c_reg_pkg;
+ // Param list
+ parameter int NumAlerts = 1;
+
// Address widths within the block
parameter int BlockAw = 7;
@@ -183,6 +186,11 @@
} i2c_reg2hw_intr_test_reg_t;
typedef struct packed {
+ logic q;
+ logic qe;
+ } i2c_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
struct packed {
logic q;
} enablehost;
@@ -519,9 +527,10 @@
// Register -> HW type
typedef struct packed {
- i2c_reg2hw_intr_state_reg_t intr_state; // [389:374]
- i2c_reg2hw_intr_enable_reg_t intr_enable; // [373:358]
- i2c_reg2hw_intr_test_reg_t intr_test; // [357:326]
+ i2c_reg2hw_intr_state_reg_t intr_state; // [391:376]
+ i2c_reg2hw_intr_enable_reg_t intr_enable; // [375:360]
+ i2c_reg2hw_intr_test_reg_t intr_test; // [359:328]
+ i2c_reg2hw_alert_test_reg_t alert_test; // [327:326]
i2c_reg2hw_ctrl_reg_t ctrl; // [325:323]
i2c_reg2hw_rdata_reg_t rdata; // [322:314]
i2c_reg2hw_fdata_reg_t fdata; // [313:295]
@@ -555,25 +564,26 @@
parameter logic [BlockAw-1:0] I2C_INTR_STATE_OFFSET = 7'h 0;
parameter logic [BlockAw-1:0] I2C_INTR_ENABLE_OFFSET = 7'h 4;
parameter logic [BlockAw-1:0] I2C_INTR_TEST_OFFSET = 7'h 8;
- parameter logic [BlockAw-1:0] I2C_CTRL_OFFSET = 7'h c;
- parameter logic [BlockAw-1:0] I2C_STATUS_OFFSET = 7'h 10;
- parameter logic [BlockAw-1:0] I2C_RDATA_OFFSET = 7'h 14;
- parameter logic [BlockAw-1:0] I2C_FDATA_OFFSET = 7'h 18;
- parameter logic [BlockAw-1:0] I2C_FIFO_CTRL_OFFSET = 7'h 1c;
- parameter logic [BlockAw-1:0] I2C_FIFO_STATUS_OFFSET = 7'h 20;
- parameter logic [BlockAw-1:0] I2C_OVRD_OFFSET = 7'h 24;
- parameter logic [BlockAw-1:0] I2C_VAL_OFFSET = 7'h 28;
- parameter logic [BlockAw-1:0] I2C_TIMING0_OFFSET = 7'h 2c;
- parameter logic [BlockAw-1:0] I2C_TIMING1_OFFSET = 7'h 30;
- parameter logic [BlockAw-1:0] I2C_TIMING2_OFFSET = 7'h 34;
- parameter logic [BlockAw-1:0] I2C_TIMING3_OFFSET = 7'h 38;
- parameter logic [BlockAw-1:0] I2C_TIMING4_OFFSET = 7'h 3c;
- parameter logic [BlockAw-1:0] I2C_TIMEOUT_CTRL_OFFSET = 7'h 40;
- parameter logic [BlockAw-1:0] I2C_TARGET_ID_OFFSET = 7'h 44;
- parameter logic [BlockAw-1:0] I2C_ACQDATA_OFFSET = 7'h 48;
- parameter logic [BlockAw-1:0] I2C_TXDATA_OFFSET = 7'h 4c;
- parameter logic [BlockAw-1:0] I2C_STRETCH_CTRL_OFFSET = 7'h 50;
- parameter logic [BlockAw-1:0] I2C_HOST_TIMEOUT_CTRL_OFFSET = 7'h 54;
+ parameter logic [BlockAw-1:0] I2C_ALERT_TEST_OFFSET = 7'h c;
+ parameter logic [BlockAw-1:0] I2C_CTRL_OFFSET = 7'h 10;
+ parameter logic [BlockAw-1:0] I2C_STATUS_OFFSET = 7'h 14;
+ parameter logic [BlockAw-1:0] I2C_RDATA_OFFSET = 7'h 18;
+ parameter logic [BlockAw-1:0] I2C_FDATA_OFFSET = 7'h 1c;
+ parameter logic [BlockAw-1:0] I2C_FIFO_CTRL_OFFSET = 7'h 20;
+ parameter logic [BlockAw-1:0] I2C_FIFO_STATUS_OFFSET = 7'h 24;
+ parameter logic [BlockAw-1:0] I2C_OVRD_OFFSET = 7'h 28;
+ parameter logic [BlockAw-1:0] I2C_VAL_OFFSET = 7'h 2c;
+ parameter logic [BlockAw-1:0] I2C_TIMING0_OFFSET = 7'h 30;
+ parameter logic [BlockAw-1:0] I2C_TIMING1_OFFSET = 7'h 34;
+ parameter logic [BlockAw-1:0] I2C_TIMING2_OFFSET = 7'h 38;
+ parameter logic [BlockAw-1:0] I2C_TIMING3_OFFSET = 7'h 3c;
+ parameter logic [BlockAw-1:0] I2C_TIMING4_OFFSET = 7'h 40;
+ parameter logic [BlockAw-1:0] I2C_TIMEOUT_CTRL_OFFSET = 7'h 44;
+ parameter logic [BlockAw-1:0] I2C_TARGET_ID_OFFSET = 7'h 48;
+ parameter logic [BlockAw-1:0] I2C_ACQDATA_OFFSET = 7'h 4c;
+ parameter logic [BlockAw-1:0] I2C_TXDATA_OFFSET = 7'h 50;
+ parameter logic [BlockAw-1:0] I2C_STRETCH_CTRL_OFFSET = 7'h 54;
+ parameter logic [BlockAw-1:0] I2C_HOST_TIMEOUT_CTRL_OFFSET = 7'h 58;
// Reset values for hwext registers and their fields
parameter logic [15:0] I2C_INTR_TEST_RESVAL = 16'h 0;
@@ -593,6 +603,8 @@
parameter logic [0:0] I2C_INTR_TEST_ACQ_OVERFLOW_RESVAL = 1'h 0;
parameter logic [0:0] I2C_INTR_TEST_ACK_STOP_RESVAL = 1'h 0;
parameter logic [0:0] I2C_INTR_TEST_HOST_TIMEOUT_RESVAL = 1'h 0;
+ parameter logic [0:0] I2C_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] I2C_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
parameter logic [9:0] I2C_STATUS_RESVAL = 10'h 33c;
parameter logic [0:0] I2C_STATUS_FMTEMPTY_RESVAL = 1'h 1;
parameter logic [0:0] I2C_STATUS_HOSTIDLE_RESVAL = 1'h 1;
@@ -610,6 +622,7 @@
I2C_INTR_STATE,
I2C_INTR_ENABLE,
I2C_INTR_TEST,
+ I2C_ALERT_TEST,
I2C_CTRL,
I2C_STATUS,
I2C_RDATA,
@@ -632,29 +645,30 @@
} i2c_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] I2C_PERMIT [22] = '{
+ parameter logic [3:0] I2C_PERMIT [23] = '{
4'b 0011, // index[ 0] I2C_INTR_STATE
4'b 0011, // index[ 1] I2C_INTR_ENABLE
4'b 0011, // index[ 2] I2C_INTR_TEST
- 4'b 0001, // index[ 3] I2C_CTRL
- 4'b 0011, // index[ 4] I2C_STATUS
- 4'b 0001, // index[ 5] I2C_RDATA
- 4'b 0011, // index[ 6] I2C_FDATA
- 4'b 0011, // index[ 7] I2C_FIFO_CTRL
- 4'b 1111, // index[ 8] I2C_FIFO_STATUS
- 4'b 0001, // index[ 9] I2C_OVRD
- 4'b 1111, // index[10] I2C_VAL
- 4'b 1111, // index[11] I2C_TIMING0
- 4'b 1111, // index[12] I2C_TIMING1
- 4'b 1111, // index[13] I2C_TIMING2
- 4'b 1111, // index[14] I2C_TIMING3
- 4'b 1111, // index[15] I2C_TIMING4
- 4'b 1111, // index[16] I2C_TIMEOUT_CTRL
- 4'b 1111, // index[17] I2C_TARGET_ID
- 4'b 0011, // index[18] I2C_ACQDATA
- 4'b 0001, // index[19] I2C_TXDATA
- 4'b 0001, // index[20] I2C_STRETCH_CTRL
- 4'b 1111 // index[21] I2C_HOST_TIMEOUT_CTRL
+ 4'b 0001, // index[ 3] I2C_ALERT_TEST
+ 4'b 0001, // index[ 4] I2C_CTRL
+ 4'b 0011, // index[ 5] I2C_STATUS
+ 4'b 0001, // index[ 6] I2C_RDATA
+ 4'b 0011, // index[ 7] I2C_FDATA
+ 4'b 0011, // index[ 8] I2C_FIFO_CTRL
+ 4'b 1111, // index[ 9] I2C_FIFO_STATUS
+ 4'b 0001, // index[10] I2C_OVRD
+ 4'b 1111, // index[11] I2C_VAL
+ 4'b 1111, // index[12] I2C_TIMING0
+ 4'b 1111, // index[13] I2C_TIMING1
+ 4'b 1111, // index[14] I2C_TIMING2
+ 4'b 1111, // index[15] I2C_TIMING3
+ 4'b 1111, // index[16] I2C_TIMING4
+ 4'b 1111, // index[17] I2C_TIMEOUT_CTRL
+ 4'b 1111, // index[18] I2C_TARGET_ID
+ 4'b 0011, // index[19] I2C_ACQDATA
+ 4'b 0001, // index[20] I2C_TXDATA
+ 4'b 0001, // index[21] I2C_STRETCH_CTRL
+ 4'b 1111 // index[22] I2C_HOST_TIMEOUT_CTRL
};
endpackage
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index c9eb1a7..5d9fdb3 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -232,6 +232,8 @@
logic intr_test_ack_stop_we;
logic intr_test_host_timeout_wd;
logic intr_test_host_timeout_we;
+ logic alert_test_wd;
+ logic alert_test_we;
logic ctrl_enablehost_qs;
logic ctrl_enablehost_wd;
logic ctrl_enablehost_we;
@@ -1459,6 +1461,22 @@
);
+ // R[alert_test]: V(True)
+
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
// R[ctrl]: V(False)
// F[enablehost]: 0:0
@@ -2821,31 +2839,32 @@
- logic [21:0] addr_hit;
+ logic [22:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == I2C_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == I2C_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == I2C_INTR_TEST_OFFSET);
- addr_hit[ 3] = (reg_addr == I2C_CTRL_OFFSET);
- addr_hit[ 4] = (reg_addr == I2C_STATUS_OFFSET);
- addr_hit[ 5] = (reg_addr == I2C_RDATA_OFFSET);
- addr_hit[ 6] = (reg_addr == I2C_FDATA_OFFSET);
- addr_hit[ 7] = (reg_addr == I2C_FIFO_CTRL_OFFSET);
- addr_hit[ 8] = (reg_addr == I2C_FIFO_STATUS_OFFSET);
- addr_hit[ 9] = (reg_addr == I2C_OVRD_OFFSET);
- addr_hit[10] = (reg_addr == I2C_VAL_OFFSET);
- addr_hit[11] = (reg_addr == I2C_TIMING0_OFFSET);
- addr_hit[12] = (reg_addr == I2C_TIMING1_OFFSET);
- addr_hit[13] = (reg_addr == I2C_TIMING2_OFFSET);
- addr_hit[14] = (reg_addr == I2C_TIMING3_OFFSET);
- addr_hit[15] = (reg_addr == I2C_TIMING4_OFFSET);
- addr_hit[16] = (reg_addr == I2C_TIMEOUT_CTRL_OFFSET);
- addr_hit[17] = (reg_addr == I2C_TARGET_ID_OFFSET);
- addr_hit[18] = (reg_addr == I2C_ACQDATA_OFFSET);
- addr_hit[19] = (reg_addr == I2C_TXDATA_OFFSET);
- addr_hit[20] = (reg_addr == I2C_STRETCH_CTRL_OFFSET);
- addr_hit[21] = (reg_addr == I2C_HOST_TIMEOUT_CTRL_OFFSET);
+ addr_hit[ 3] = (reg_addr == I2C_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == I2C_CTRL_OFFSET);
+ addr_hit[ 5] = (reg_addr == I2C_STATUS_OFFSET);
+ addr_hit[ 6] = (reg_addr == I2C_RDATA_OFFSET);
+ addr_hit[ 7] = (reg_addr == I2C_FDATA_OFFSET);
+ addr_hit[ 8] = (reg_addr == I2C_FIFO_CTRL_OFFSET);
+ addr_hit[ 9] = (reg_addr == I2C_FIFO_STATUS_OFFSET);
+ addr_hit[10] = (reg_addr == I2C_OVRD_OFFSET);
+ addr_hit[11] = (reg_addr == I2C_VAL_OFFSET);
+ addr_hit[12] = (reg_addr == I2C_TIMING0_OFFSET);
+ addr_hit[13] = (reg_addr == I2C_TIMING1_OFFSET);
+ addr_hit[14] = (reg_addr == I2C_TIMING2_OFFSET);
+ addr_hit[15] = (reg_addr == I2C_TIMING3_OFFSET);
+ addr_hit[16] = (reg_addr == I2C_TIMING4_OFFSET);
+ addr_hit[17] = (reg_addr == I2C_TIMEOUT_CTRL_OFFSET);
+ addr_hit[18] = (reg_addr == I2C_TARGET_ID_OFFSET);
+ addr_hit[19] = (reg_addr == I2C_ACQDATA_OFFSET);
+ addr_hit[20] = (reg_addr == I2C_TXDATA_OFFSET);
+ addr_hit[21] = (reg_addr == I2C_STRETCH_CTRL_OFFSET);
+ addr_hit[22] = (reg_addr == I2C_HOST_TIMEOUT_CTRL_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -2874,7 +2893,8 @@
(addr_hit[18] & (|(I2C_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(I2C_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(I2C_PERMIT[20] & ~reg_be))) |
- (addr_hit[21] & (|(I2C_PERMIT[21] & ~reg_be)))));
+ (addr_hit[21] & (|(I2C_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(I2C_PERMIT[22] & ~reg_be)))));
end
assign intr_state_fmt_watermark_we = addr_hit[0] & reg_we & !reg_error;
@@ -3021,162 +3041,165 @@
assign intr_test_host_timeout_we = addr_hit[2] & reg_we & !reg_error;
assign intr_test_host_timeout_wd = reg_wdata[15];
- assign ctrl_enablehost_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_test_wd = reg_wdata[0];
+
+ assign ctrl_enablehost_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_enablehost_wd = reg_wdata[0];
- assign ctrl_enabletarget_we = addr_hit[3] & reg_we & !reg_error;
+ assign ctrl_enabletarget_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_enabletarget_wd = reg_wdata[1];
- assign ctrl_llpbk_we = addr_hit[3] & reg_we & !reg_error;
+ assign ctrl_llpbk_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_llpbk_wd = reg_wdata[2];
- assign status_fmtfull_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_fmtfull_re = addr_hit[5] & reg_re & !reg_error;
- assign status_rxfull_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_rxfull_re = addr_hit[5] & reg_re & !reg_error;
- assign status_fmtempty_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_fmtempty_re = addr_hit[5] & reg_re & !reg_error;
- assign status_hostidle_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_hostidle_re = addr_hit[5] & reg_re & !reg_error;
- assign status_targetidle_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_targetidle_re = addr_hit[5] & reg_re & !reg_error;
- assign status_rxempty_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_rxempty_re = addr_hit[5] & reg_re & !reg_error;
- assign status_txfull_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_txfull_re = addr_hit[5] & reg_re & !reg_error;
- assign status_acqfull_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_acqfull_re = addr_hit[5] & reg_re & !reg_error;
- assign status_txempty_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_txempty_re = addr_hit[5] & reg_re & !reg_error;
- assign status_acqempty_re = addr_hit[4] & reg_re & !reg_error;
+ assign status_acqempty_re = addr_hit[5] & reg_re & !reg_error;
- assign rdata_re = addr_hit[5] & reg_re & !reg_error;
+ assign rdata_re = addr_hit[6] & reg_re & !reg_error;
- assign fdata_fbyte_we = addr_hit[6] & reg_we & !reg_error;
+ assign fdata_fbyte_we = addr_hit[7] & reg_we & !reg_error;
assign fdata_fbyte_wd = reg_wdata[7:0];
- assign fdata_start_we = addr_hit[6] & reg_we & !reg_error;
+ assign fdata_start_we = addr_hit[7] & reg_we & !reg_error;
assign fdata_start_wd = reg_wdata[8];
- assign fdata_stop_we = addr_hit[6] & reg_we & !reg_error;
+ assign fdata_stop_we = addr_hit[7] & reg_we & !reg_error;
assign fdata_stop_wd = reg_wdata[9];
- assign fdata_read_we = addr_hit[6] & reg_we & !reg_error;
+ assign fdata_read_we = addr_hit[7] & reg_we & !reg_error;
assign fdata_read_wd = reg_wdata[10];
- assign fdata_rcont_we = addr_hit[6] & reg_we & !reg_error;
+ assign fdata_rcont_we = addr_hit[7] & reg_we & !reg_error;
assign fdata_rcont_wd = reg_wdata[11];
- assign fdata_nakok_we = addr_hit[6] & reg_we & !reg_error;
+ assign fdata_nakok_we = addr_hit[7] & reg_we & !reg_error;
assign fdata_nakok_wd = reg_wdata[12];
- assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & !reg_error;
+ assign fifo_ctrl_rxrst_we = addr_hit[8] & reg_we & !reg_error;
assign fifo_ctrl_rxrst_wd = reg_wdata[0];
- assign fifo_ctrl_fmtrst_we = addr_hit[7] & reg_we & !reg_error;
+ assign fifo_ctrl_fmtrst_we = addr_hit[8] & reg_we & !reg_error;
assign fifo_ctrl_fmtrst_wd = reg_wdata[1];
- assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & !reg_error;
+ assign fifo_ctrl_rxilvl_we = addr_hit[8] & reg_we & !reg_error;
assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
- assign fifo_ctrl_fmtilvl_we = addr_hit[7] & reg_we & !reg_error;
+ assign fifo_ctrl_fmtilvl_we = addr_hit[8] & reg_we & !reg_error;
assign fifo_ctrl_fmtilvl_wd = reg_wdata[6:5];
- assign fifo_ctrl_acqrst_we = addr_hit[7] & reg_we & !reg_error;
+ assign fifo_ctrl_acqrst_we = addr_hit[8] & reg_we & !reg_error;
assign fifo_ctrl_acqrst_wd = reg_wdata[7];
- assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & !reg_error;
+ assign fifo_ctrl_txrst_we = addr_hit[8] & reg_we & !reg_error;
assign fifo_ctrl_txrst_wd = reg_wdata[8];
- assign fifo_status_fmtlvl_re = addr_hit[8] & reg_re & !reg_error;
+ assign fifo_status_fmtlvl_re = addr_hit[9] & reg_re & !reg_error;
- assign fifo_status_txlvl_re = addr_hit[8] & reg_re & !reg_error;
+ assign fifo_status_txlvl_re = addr_hit[9] & reg_re & !reg_error;
- assign fifo_status_rxlvl_re = addr_hit[8] & reg_re & !reg_error;
+ assign fifo_status_rxlvl_re = addr_hit[9] & reg_re & !reg_error;
- assign fifo_status_acqlvl_re = addr_hit[8] & reg_re & !reg_error;
+ assign fifo_status_acqlvl_re = addr_hit[9] & reg_re & !reg_error;
- assign ovrd_txovrden_we = addr_hit[9] & reg_we & !reg_error;
+ assign ovrd_txovrden_we = addr_hit[10] & reg_we & !reg_error;
assign ovrd_txovrden_wd = reg_wdata[0];
- assign ovrd_sclval_we = addr_hit[9] & reg_we & !reg_error;
+ assign ovrd_sclval_we = addr_hit[10] & reg_we & !reg_error;
assign ovrd_sclval_wd = reg_wdata[1];
- assign ovrd_sdaval_we = addr_hit[9] & reg_we & !reg_error;
+ assign ovrd_sdaval_we = addr_hit[10] & reg_we & !reg_error;
assign ovrd_sdaval_wd = reg_wdata[2];
- assign val_scl_rx_re = addr_hit[10] & reg_re & !reg_error;
+ assign val_scl_rx_re = addr_hit[11] & reg_re & !reg_error;
- assign val_sda_rx_re = addr_hit[10] & reg_re & !reg_error;
+ assign val_sda_rx_re = addr_hit[11] & reg_re & !reg_error;
- assign timing0_thigh_we = addr_hit[11] & reg_we & !reg_error;
+ assign timing0_thigh_we = addr_hit[12] & reg_we & !reg_error;
assign timing0_thigh_wd = reg_wdata[15:0];
- assign timing0_tlow_we = addr_hit[11] & reg_we & !reg_error;
+ assign timing0_tlow_we = addr_hit[12] & reg_we & !reg_error;
assign timing0_tlow_wd = reg_wdata[31:16];
- assign timing1_t_r_we = addr_hit[12] & reg_we & !reg_error;
+ assign timing1_t_r_we = addr_hit[13] & reg_we & !reg_error;
assign timing1_t_r_wd = reg_wdata[15:0];
- assign timing1_t_f_we = addr_hit[12] & reg_we & !reg_error;
+ assign timing1_t_f_we = addr_hit[13] & reg_we & !reg_error;
assign timing1_t_f_wd = reg_wdata[31:16];
- assign timing2_tsu_sta_we = addr_hit[13] & reg_we & !reg_error;
+ assign timing2_tsu_sta_we = addr_hit[14] & reg_we & !reg_error;
assign timing2_tsu_sta_wd = reg_wdata[15:0];
- assign timing2_thd_sta_we = addr_hit[13] & reg_we & !reg_error;
+ assign timing2_thd_sta_we = addr_hit[14] & reg_we & !reg_error;
assign timing2_thd_sta_wd = reg_wdata[31:16];
- assign timing3_tsu_dat_we = addr_hit[14] & reg_we & !reg_error;
+ assign timing3_tsu_dat_we = addr_hit[15] & reg_we & !reg_error;
assign timing3_tsu_dat_wd = reg_wdata[15:0];
- assign timing3_thd_dat_we = addr_hit[14] & reg_we & !reg_error;
+ assign timing3_thd_dat_we = addr_hit[15] & reg_we & !reg_error;
assign timing3_thd_dat_wd = reg_wdata[31:16];
- assign timing4_tsu_sto_we = addr_hit[15] & reg_we & !reg_error;
+ assign timing4_tsu_sto_we = addr_hit[16] & reg_we & !reg_error;
assign timing4_tsu_sto_wd = reg_wdata[15:0];
- assign timing4_t_buf_we = addr_hit[15] & reg_we & !reg_error;
+ assign timing4_t_buf_we = addr_hit[16] & reg_we & !reg_error;
assign timing4_t_buf_wd = reg_wdata[31:16];
- assign timeout_ctrl_val_we = addr_hit[16] & reg_we & !reg_error;
+ assign timeout_ctrl_val_we = addr_hit[17] & reg_we & !reg_error;
assign timeout_ctrl_val_wd = reg_wdata[30:0];
- assign timeout_ctrl_en_we = addr_hit[16] & reg_we & !reg_error;
+ assign timeout_ctrl_en_we = addr_hit[17] & reg_we & !reg_error;
assign timeout_ctrl_en_wd = reg_wdata[31];
- assign target_id_address0_we = addr_hit[17] & reg_we & !reg_error;
+ assign target_id_address0_we = addr_hit[18] & reg_we & !reg_error;
assign target_id_address0_wd = reg_wdata[6:0];
- assign target_id_mask0_we = addr_hit[17] & reg_we & !reg_error;
+ assign target_id_mask0_we = addr_hit[18] & reg_we & !reg_error;
assign target_id_mask0_wd = reg_wdata[13:7];
- assign target_id_address1_we = addr_hit[17] & reg_we & !reg_error;
+ assign target_id_address1_we = addr_hit[18] & reg_we & !reg_error;
assign target_id_address1_wd = reg_wdata[20:14];
- assign target_id_mask1_we = addr_hit[17] & reg_we & !reg_error;
+ assign target_id_mask1_we = addr_hit[18] & reg_we & !reg_error;
assign target_id_mask1_wd = reg_wdata[27:21];
- assign acqdata_abyte_re = addr_hit[18] & reg_re & !reg_error;
+ assign acqdata_abyte_re = addr_hit[19] & reg_re & !reg_error;
- assign acqdata_signal_re = addr_hit[18] & reg_re & !reg_error;
+ assign acqdata_signal_re = addr_hit[19] & reg_re & !reg_error;
- assign txdata_we = addr_hit[19] & reg_we & !reg_error;
+ assign txdata_we = addr_hit[20] & reg_we & !reg_error;
assign txdata_wd = reg_wdata[7:0];
- assign stretch_ctrl_en_addr_tx_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_en_addr_tx_we = addr_hit[21] & reg_we & !reg_error;
assign stretch_ctrl_en_addr_tx_wd = reg_wdata[0];
- assign stretch_ctrl_en_addr_acq_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_en_addr_acq_we = addr_hit[21] & reg_we & !reg_error;
assign stretch_ctrl_en_addr_acq_wd = reg_wdata[1];
- assign stretch_ctrl_stop_tx_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_stop_tx_we = addr_hit[21] & reg_we & !reg_error;
assign stretch_ctrl_stop_tx_wd = reg_wdata[2];
- assign stretch_ctrl_stop_acq_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_stop_acq_we = addr_hit[21] & reg_we & !reg_error;
assign stretch_ctrl_stop_acq_wd = reg_wdata[3];
- assign host_timeout_ctrl_we = addr_hit[21] & reg_we & !reg_error;
+ assign host_timeout_ctrl_we = addr_hit[22] & reg_we & !reg_error;
assign host_timeout_ctrl_wd = reg_wdata[31:0];
// Read data return
@@ -3241,12 +3264,16 @@
end
addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[4]: begin
reg_rdata_next[0] = ctrl_enablehost_qs;
reg_rdata_next[1] = ctrl_enabletarget_qs;
reg_rdata_next[2] = ctrl_llpbk_qs;
end
- addr_hit[4]: begin
+ addr_hit[5]: begin
reg_rdata_next[0] = status_fmtfull_qs;
reg_rdata_next[1] = status_rxfull_qs;
reg_rdata_next[2] = status_fmtempty_qs;
@@ -3259,11 +3286,11 @@
reg_rdata_next[9] = status_acqempty_qs;
end
- addr_hit[5]: begin
+ addr_hit[6]: begin
reg_rdata_next[7:0] = rdata_qs;
end
- addr_hit[6]: begin
+ addr_hit[7]: begin
reg_rdata_next[7:0] = '0;
reg_rdata_next[8] = '0;
reg_rdata_next[9] = '0;
@@ -3272,7 +3299,7 @@
reg_rdata_next[12] = '0;
end
- addr_hit[7]: begin
+ addr_hit[8]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
@@ -3281,78 +3308,78 @@
reg_rdata_next[8] = '0;
end
- addr_hit[8]: begin
+ addr_hit[9]: begin
reg_rdata_next[6:0] = fifo_status_fmtlvl_qs;
reg_rdata_next[14:8] = fifo_status_txlvl_qs;
reg_rdata_next[22:16] = fifo_status_rxlvl_qs;
reg_rdata_next[30:24] = fifo_status_acqlvl_qs;
end
- addr_hit[9]: begin
+ addr_hit[10]: begin
reg_rdata_next[0] = ovrd_txovrden_qs;
reg_rdata_next[1] = ovrd_sclval_qs;
reg_rdata_next[2] = ovrd_sdaval_qs;
end
- addr_hit[10]: begin
+ addr_hit[11]: begin
reg_rdata_next[15:0] = val_scl_rx_qs;
reg_rdata_next[31:16] = val_sda_rx_qs;
end
- addr_hit[11]: begin
+ addr_hit[12]: begin
reg_rdata_next[15:0] = timing0_thigh_qs;
reg_rdata_next[31:16] = timing0_tlow_qs;
end
- addr_hit[12]: begin
+ addr_hit[13]: begin
reg_rdata_next[15:0] = timing1_t_r_qs;
reg_rdata_next[31:16] = timing1_t_f_qs;
end
- addr_hit[13]: begin
+ addr_hit[14]: begin
reg_rdata_next[15:0] = timing2_tsu_sta_qs;
reg_rdata_next[31:16] = timing2_thd_sta_qs;
end
- addr_hit[14]: begin
+ addr_hit[15]: begin
reg_rdata_next[15:0] = timing3_tsu_dat_qs;
reg_rdata_next[31:16] = timing3_thd_dat_qs;
end
- addr_hit[15]: begin
+ addr_hit[16]: begin
reg_rdata_next[15:0] = timing4_tsu_sto_qs;
reg_rdata_next[31:16] = timing4_t_buf_qs;
end
- addr_hit[16]: begin
+ addr_hit[17]: begin
reg_rdata_next[30:0] = timeout_ctrl_val_qs;
reg_rdata_next[31] = timeout_ctrl_en_qs;
end
- addr_hit[17]: begin
+ addr_hit[18]: begin
reg_rdata_next[6:0] = target_id_address0_qs;
reg_rdata_next[13:7] = target_id_mask0_qs;
reg_rdata_next[20:14] = target_id_address1_qs;
reg_rdata_next[27:21] = target_id_mask1_qs;
end
- addr_hit[18]: begin
+ addr_hit[19]: begin
reg_rdata_next[7:0] = acqdata_abyte_qs;
reg_rdata_next[9:8] = acqdata_signal_qs;
end
- addr_hit[19]: begin
+ addr_hit[20]: begin
reg_rdata_next[7:0] = '0;
end
- addr_hit[20]: begin
+ addr_hit[21]: begin
reg_rdata_next[0] = stretch_ctrl_en_addr_tx_qs;
reg_rdata_next[1] = stretch_ctrl_en_addr_acq_qs;
reg_rdata_next[2] = stretch_ctrl_stop_tx_qs;
reg_rdata_next[3] = stretch_ctrl_stop_acq_qs;
end
- addr_hit[21]: begin
+ addr_hit[22]: begin
reg_rdata_next[31:0] = host_timeout_ctrl_qs;
end
diff --git a/hw/ip/spi_host/data/spi_host.hjson b/hw/ip/spi_host/data/spi_host.hjson
index 5fa1bd4..2e8d982 100644
--- a/hw/ip/spi_host/data/spi_host.hjson
+++ b/hw/ip/spi_host/data/spi_host.hjson
@@ -18,6 +18,13 @@
width: "1"
}
]
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the KMAC unit.
+ '''
+ }
+ ],
regwidth: "32",
scan: "true",
param_list: [
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 33d3f0e..f66b45b 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -11530,6 +11530,9 @@
spi_device
spi_host0
spi_host1
+ i2c0
+ i2c1
+ i2c2
pattgen
otp_ctrl
lc_ctrl
@@ -11608,6 +11611,27 @@
module_name: spi_host1
}
{
+ name: i2c0_fatal_fault
+ width: 1
+ type: alert
+ async: "0"
+ module_name: i2c0
+ }
+ {
+ name: i2c1_fatal_fault
+ width: 1
+ type: alert
+ async: "0"
+ module_name: i2c1
+ }
+ {
+ name: i2c2_fatal_fault
+ width: 1
+ type: alert
+ async: "0"
+ module_name: i2c2
+ }
+ {
name: pattgen_fatal_fault
width: 1
type: alert
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 965dfa4..0e41d92 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -12,43 +12,46 @@
assign alert_if[5].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0];
assign alert_if[6].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
assign alert_if[7].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
-assign alert_if[8].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
-assign alert_if[9].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[29].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[30].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[31].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
-assign alert_if[32].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[33].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[34].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[37].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[43].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[44].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[45].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[46].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[47].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_i2c1.alert_tx_o[0];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_i2c2.alert_tx_o[0];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
+assign alert_if[31].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[32].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[33].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[48].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[49].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[50].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 003512c..fd7e2dc 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -13,6 +13,9 @@
"spi_device_fatal_fault",
"spi_host0_fatal_fault",
"spi_host1_fatal_fault",
+ "i2c0_fatal_fault",
+ "i2c1_fatal_fault",
+ "i2c2_fatal_fault",
"pattgen_fatal_fault",
"otp_ctrl_fatal_macro_error",
"otp_ctrl_fatal_check_error",
@@ -55,4 +58,4 @@
"rom_ctrl_fatal"
};
-parameter uint NUM_ALERTS = 48;
+parameter uint NUM_ALERTS = 51;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 433586c..6451fe7 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "48",
+ default: "51",
local: "true"
},
{ name: "EscCntDw",
@@ -66,7 +66,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "48'b111111111111111111110000000000000000000000000000",
+ default: "51'b111111111111111111110000000000000000000000000000000",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 7c5cbf6..c203709 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 48;
+ parameter int NAlerts = 51;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
- parameter logic [NAlerts-1:0] AsyncOn = 48'b111111111111111111110000000000000000000000000000;
+ parameter logic [NAlerts-1:0] AsyncOn = 51'b111111111111111111110000000000000000000000000000000;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -458,15 +458,15 @@
// Register -> HW type
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [1068:1065]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1064:1061]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [1060:1053]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1052:1029]
- alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1028:1028]
- alert_handler_reg2hw_alert_regwen_mreg_t [47:0] alert_regwen; // [1027:980]
- alert_handler_reg2hw_alert_en_mreg_t [47:0] alert_en; // [979:932]
- alert_handler_reg2hw_alert_class_mreg_t [47:0] alert_class; // [931:836]
- alert_handler_reg2hw_alert_cause_mreg_t [47:0] alert_cause; // [835:788]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [1083:1080]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1079:1076]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [1075:1068]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1067:1044]
+ alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1043:1043]
+ alert_handler_reg2hw_alert_regwen_mreg_t [50:0] alert_regwen; // [1042:992]
+ alert_handler_reg2hw_alert_en_mreg_t [50:0] alert_en; // [991:941]
+ alert_handler_reg2hw_alert_class_mreg_t [50:0] alert_class; // [940:839]
+ alert_handler_reg2hw_alert_cause_mreg_t [50:0] alert_cause; // [838:788]
alert_handler_reg2hw_loc_alert_en_mreg_t [4:0] loc_alert_en; // [787:783]
alert_handler_reg2hw_loc_alert_class_mreg_t [4:0] loc_alert_class; // [782:773]
alert_handler_reg2hw_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [772:768]
@@ -506,8 +506,8 @@
// HW -> register type
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [325:318]
- alert_handler_hw2reg_alert_cause_mreg_t [47:0] alert_cause; // [317:222]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [331:324]
+ alert_handler_hw2reg_alert_cause_mreg_t [50:0] alert_cause; // [323:222]
alert_handler_hw2reg_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [221:212]
alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -582,222 +582,234 @@
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_45_OFFSET = 11'h cc;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_46_OFFSET = 11'h d0;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_47_OFFSET = 11'h d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 100;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 104;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 108;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 10c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 110;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 114;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 118;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 11c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 120;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 124;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 128;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 12c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 130;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 134;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 138;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 13c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 140;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 144;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 148;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 14c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 150;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 154;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 158;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 15c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 160;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 164;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 168;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 16c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 170;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 174;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 178;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 17c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 180;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 184;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 188;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 18c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 190;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 194;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 198;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 19c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 1a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 1a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 1a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 1ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 1b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 1b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 1b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 1bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 1c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 1c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 1c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 1cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 1d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 1d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 1d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 1dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 1e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 1e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 1e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 1ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 1f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 1f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 1f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 1fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 200;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 204;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 208;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 20c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 210;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 214;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 218;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 21c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 220;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 224;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 228;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 22c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 230;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 234;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 238;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 23c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 240;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 244;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 248;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 24c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 250;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 254;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 258;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 25c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 260;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 264;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 268;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 26c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 270;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 274;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 278;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 27c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 280;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 284;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 288;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 28c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 290;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 294;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 298;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 29c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 2a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 2a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 2a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 2ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 2b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 2b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 2b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 2bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 2c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 2c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 2c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 2cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 2d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 2d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 2d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 2dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 2e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 2e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 2e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 2ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 2f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 2f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 2f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 2fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 300;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 304;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 308;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 30c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 310;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 314;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 318;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 31c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 320;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 324;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 328;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 32c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 330;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 334;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 338;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 33c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 340;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 344;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 348;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 34c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 350;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 354;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 358;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 35c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 360;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 364;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 368;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 36c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 370;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 374;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 378;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 37c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 380;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 384;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 388;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 38c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 390;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 394;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 398;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 39c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 3a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 3a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 3a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 3ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 3b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 3b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 3b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 3bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 3c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 3c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 3c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 3cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 3d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 3d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 3d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 3dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 3e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 3e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 3e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 3ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 3f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 3f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 3f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 3fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 400;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 404;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 408;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 40c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 410;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 414;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 418;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 41c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 420;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 424;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 428;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 42c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 430;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 434;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_48_OFFSET = 11'h d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_49_OFFSET = 11'h dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_50_OFFSET = 11'h e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h 100;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h 104;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h 108;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 10c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 110;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 114;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 118;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 11c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 120;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 124;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 128;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 12c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 130;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 134;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 138;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 13c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 140;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 144;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 148;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 14c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 150;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 154;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 158;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 15c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 160;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 164;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 168;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 16c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 170;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 174;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 178;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 17c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 180;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 184;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 188;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 18c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 190;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 194;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 198;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 19c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 1a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_48_OFFSET = 11'h 1a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_49_OFFSET = 11'h 1a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_50_OFFSET = 11'h 1ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 1b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 1b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 1b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 1bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 1c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 1c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 1c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 1cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 1d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 1d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 1d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 1dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 1e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 1e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 1e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 1ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 1f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 1f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 1f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 1fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 200;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 204;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 208;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 20c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 210;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 214;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 218;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 21c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 220;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 224;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 228;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 22c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 230;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 234;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 238;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 23c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 240;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 244;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 248;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 24c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 250;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 254;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 258;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 25c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 260;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 264;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 268;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 26c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_48_OFFSET = 11'h 270;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_49_OFFSET = 11'h 274;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_50_OFFSET = 11'h 278;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 27c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 280;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 284;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 288;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 28c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 290;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 294;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 298;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 29c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 2a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 2a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 2a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 2ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 2b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 2b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 2b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 2bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 2c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 2c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 2c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 2cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 2d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 2d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 2d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 2dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 2e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 2e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 2e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 2ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 2f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 2f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 2f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 2fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 300;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 304;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 308;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 30c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 310;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 314;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 318;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 31c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 320;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 324;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 328;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 32c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 330;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 334;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 338;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 33c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 340;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 344;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 348;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 34c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 350;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 354;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 358;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 35c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 360;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 364;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 368;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 36c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 370;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 374;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 378;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 37c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 380;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 384;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 388;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 38c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 390;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 394;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 398;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 39c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 3a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 3a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 3a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 3ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 3b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 3b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 3bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 3c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 3c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 3c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 3cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 3d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 3d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 3d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 3dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 3e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 3e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 3e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 3ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 3f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 3f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 3f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 3fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 400;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 404;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 408;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 40c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 410;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 414;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 418;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 41c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 420;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 424;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 428;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 42c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 430;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 434;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 438;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 43c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 440;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 444;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 448;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 44c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 450;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 454;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 458;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 45c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 460;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 464;
// Reset values for hwext registers and their fields
parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -874,6 +886,9 @@
ALERT_HANDLER_ALERT_REGWEN_45,
ALERT_HANDLER_ALERT_REGWEN_46,
ALERT_HANDLER_ALERT_REGWEN_47,
+ ALERT_HANDLER_ALERT_REGWEN_48,
+ ALERT_HANDLER_ALERT_REGWEN_49,
+ ALERT_HANDLER_ALERT_REGWEN_50,
ALERT_HANDLER_ALERT_EN_0,
ALERT_HANDLER_ALERT_EN_1,
ALERT_HANDLER_ALERT_EN_2,
@@ -922,6 +937,9 @@
ALERT_HANDLER_ALERT_EN_45,
ALERT_HANDLER_ALERT_EN_46,
ALERT_HANDLER_ALERT_EN_47,
+ ALERT_HANDLER_ALERT_EN_48,
+ ALERT_HANDLER_ALERT_EN_49,
+ ALERT_HANDLER_ALERT_EN_50,
ALERT_HANDLER_ALERT_CLASS_0,
ALERT_HANDLER_ALERT_CLASS_1,
ALERT_HANDLER_ALERT_CLASS_2,
@@ -970,6 +988,9 @@
ALERT_HANDLER_ALERT_CLASS_45,
ALERT_HANDLER_ALERT_CLASS_46,
ALERT_HANDLER_ALERT_CLASS_47,
+ ALERT_HANDLER_ALERT_CLASS_48,
+ ALERT_HANDLER_ALERT_CLASS_49,
+ ALERT_HANDLER_ALERT_CLASS_50,
ALERT_HANDLER_ALERT_CAUSE_0,
ALERT_HANDLER_ALERT_CAUSE_1,
ALERT_HANDLER_ALERT_CAUSE_2,
@@ -1018,6 +1039,9 @@
ALERT_HANDLER_ALERT_CAUSE_45,
ALERT_HANDLER_ALERT_CAUSE_46,
ALERT_HANDLER_ALERT_CAUSE_47,
+ ALERT_HANDLER_ALERT_CAUSE_48,
+ ALERT_HANDLER_ALERT_CAUSE_49,
+ ALERT_HANDLER_ALERT_CAUSE_50,
ALERT_HANDLER_LOC_ALERT_REGWEN_0,
ALERT_HANDLER_LOC_ALERT_REGWEN_1,
ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1093,7 +1117,7 @@
} alert_handler_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ALERT_HANDLER_PERMIT [270] = '{
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [282] = '{
4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
@@ -1148,222 +1172,234 @@
4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_REGWEN_45
4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_REGWEN_46
4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_REGWEN_47
- 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_0
- 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_1
- 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_2
- 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_3
- 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_4
- 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_5
- 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_6
- 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_7
- 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_8
- 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_9
- 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_10
- 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_11
- 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_12
- 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_13
- 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_14
- 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_15
- 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_16
- 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_17
- 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_18
- 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_19
- 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_20
- 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_21
- 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_22
- 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_23
- 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_24
- 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_25
- 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_26
- 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_27
- 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_28
- 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_29
- 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_30
- 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_31
- 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_32
- 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_33
- 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_34
- 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_35
- 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_36
- 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_37
- 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_38
- 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_39
- 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_40
- 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_41
- 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_42
- 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_43
- 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_44
- 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_45
- 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_46
- 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_47
- 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_0
- 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_1
- 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_2
- 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_3
- 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_4
- 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_5
- 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_6
- 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_7
- 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_8
- 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_9
- 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_10
- 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_11
- 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_12
- 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_13
- 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_14
- 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_15
- 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_16
- 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_17
- 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_18
- 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_19
- 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_20
- 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_21
- 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_22
- 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_23
- 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_24
- 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_25
- 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_26
- 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_27
- 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_28
- 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_29
- 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_30
- 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_31
- 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_32
- 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_33
- 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_34
- 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_35
- 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_36
- 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_37
- 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_38
- 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_39
- 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_40
- 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_41
- 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_42
- 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_43
- 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_44
- 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_45
- 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_46
- 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_47
- 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_0
- 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_1
- 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_2
- 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_3
- 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_4
- 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_5
- 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_6
- 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_7
- 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_8
- 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_9
- 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_10
- 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_11
- 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_12
- 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_13
- 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_14
- 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_15
- 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_16
- 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_17
- 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_18
- 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_19
- 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CAUSE_20
- 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CAUSE_21
- 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CAUSE_22
- 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CAUSE_23
- 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CAUSE_24
- 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CAUSE_25
- 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CAUSE_26
- 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CAUSE_27
- 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CAUSE_28
- 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CAUSE_29
- 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_30
- 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_31
- 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CAUSE_32
- 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CAUSE_33
- 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CAUSE_34
- 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CAUSE_35
- 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_36
- 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_37
- 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_38
- 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_39
- 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_40
- 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_41
- 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_42
- 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_43
- 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_44
- 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_45
- 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_46
- 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_47
- 4'b 0001, // index[198] ALERT_HANDLER_LOC_ALERT_REGWEN_0
- 4'b 0001, // index[199] ALERT_HANDLER_LOC_ALERT_REGWEN_1
- 4'b 0001, // index[200] ALERT_HANDLER_LOC_ALERT_REGWEN_2
- 4'b 0001, // index[201] ALERT_HANDLER_LOC_ALERT_REGWEN_3
- 4'b 0001, // index[202] ALERT_HANDLER_LOC_ALERT_REGWEN_4
- 4'b 0001, // index[203] ALERT_HANDLER_LOC_ALERT_EN_0
- 4'b 0001, // index[204] ALERT_HANDLER_LOC_ALERT_EN_1
- 4'b 0001, // index[205] ALERT_HANDLER_LOC_ALERT_EN_2
- 4'b 0001, // index[206] ALERT_HANDLER_LOC_ALERT_EN_3
- 4'b 0001, // index[207] ALERT_HANDLER_LOC_ALERT_EN_4
- 4'b 0001, // index[208] ALERT_HANDLER_LOC_ALERT_CLASS_0
- 4'b 0001, // index[209] ALERT_HANDLER_LOC_ALERT_CLASS_1
- 4'b 0001, // index[210] ALERT_HANDLER_LOC_ALERT_CLASS_2
- 4'b 0001, // index[211] ALERT_HANDLER_LOC_ALERT_CLASS_3
- 4'b 0001, // index[212] ALERT_HANDLER_LOC_ALERT_CLASS_4
- 4'b 0001, // index[213] ALERT_HANDLER_LOC_ALERT_CAUSE_0
- 4'b 0001, // index[214] ALERT_HANDLER_LOC_ALERT_CAUSE_1
- 4'b 0001, // index[215] ALERT_HANDLER_LOC_ALERT_CAUSE_2
- 4'b 0001, // index[216] ALERT_HANDLER_LOC_ALERT_CAUSE_3
- 4'b 0001, // index[217] ALERT_HANDLER_LOC_ALERT_CAUSE_4
- 4'b 0001, // index[218] ALERT_HANDLER_CLASSA_REGWEN
- 4'b 0011, // index[219] ALERT_HANDLER_CLASSA_CTRL
- 4'b 0001, // index[220] ALERT_HANDLER_CLASSA_CLR_REGWEN
- 4'b 0001, // index[221] ALERT_HANDLER_CLASSA_CLR
- 4'b 0011, // index[222] ALERT_HANDLER_CLASSA_ACCUM_CNT
- 4'b 0011, // index[223] ALERT_HANDLER_CLASSA_ACCUM_THRESH
- 4'b 1111, // index[224] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
- 4'b 1111, // index[225] ALERT_HANDLER_CLASSA_PHASE0_CYC
- 4'b 1111, // index[226] ALERT_HANDLER_CLASSA_PHASE1_CYC
- 4'b 1111, // index[227] ALERT_HANDLER_CLASSA_PHASE2_CYC
- 4'b 1111, // index[228] ALERT_HANDLER_CLASSA_PHASE3_CYC
- 4'b 1111, // index[229] ALERT_HANDLER_CLASSA_ESC_CNT
- 4'b 0001, // index[230] ALERT_HANDLER_CLASSA_STATE
- 4'b 0001, // index[231] ALERT_HANDLER_CLASSB_REGWEN
- 4'b 0011, // index[232] ALERT_HANDLER_CLASSB_CTRL
- 4'b 0001, // index[233] ALERT_HANDLER_CLASSB_CLR_REGWEN
- 4'b 0001, // index[234] ALERT_HANDLER_CLASSB_CLR
- 4'b 0011, // index[235] ALERT_HANDLER_CLASSB_ACCUM_CNT
- 4'b 0011, // index[236] ALERT_HANDLER_CLASSB_ACCUM_THRESH
- 4'b 1111, // index[237] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
- 4'b 1111, // index[238] ALERT_HANDLER_CLASSB_PHASE0_CYC
- 4'b 1111, // index[239] ALERT_HANDLER_CLASSB_PHASE1_CYC
- 4'b 1111, // index[240] ALERT_HANDLER_CLASSB_PHASE2_CYC
- 4'b 1111, // index[241] ALERT_HANDLER_CLASSB_PHASE3_CYC
- 4'b 1111, // index[242] ALERT_HANDLER_CLASSB_ESC_CNT
- 4'b 0001, // index[243] ALERT_HANDLER_CLASSB_STATE
- 4'b 0001, // index[244] ALERT_HANDLER_CLASSC_REGWEN
- 4'b 0011, // index[245] ALERT_HANDLER_CLASSC_CTRL
- 4'b 0001, // index[246] ALERT_HANDLER_CLASSC_CLR_REGWEN
- 4'b 0001, // index[247] ALERT_HANDLER_CLASSC_CLR
- 4'b 0011, // index[248] ALERT_HANDLER_CLASSC_ACCUM_CNT
- 4'b 0011, // index[249] ALERT_HANDLER_CLASSC_ACCUM_THRESH
- 4'b 1111, // index[250] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
- 4'b 1111, // index[251] ALERT_HANDLER_CLASSC_PHASE0_CYC
- 4'b 1111, // index[252] ALERT_HANDLER_CLASSC_PHASE1_CYC
- 4'b 1111, // index[253] ALERT_HANDLER_CLASSC_PHASE2_CYC
- 4'b 1111, // index[254] ALERT_HANDLER_CLASSC_PHASE3_CYC
- 4'b 1111, // index[255] ALERT_HANDLER_CLASSC_ESC_CNT
- 4'b 0001, // index[256] ALERT_HANDLER_CLASSC_STATE
- 4'b 0001, // index[257] ALERT_HANDLER_CLASSD_REGWEN
- 4'b 0011, // index[258] ALERT_HANDLER_CLASSD_CTRL
- 4'b 0001, // index[259] ALERT_HANDLER_CLASSD_CLR_REGWEN
- 4'b 0001, // index[260] ALERT_HANDLER_CLASSD_CLR
- 4'b 0011, // index[261] ALERT_HANDLER_CLASSD_ACCUM_CNT
- 4'b 0011, // index[262] ALERT_HANDLER_CLASSD_ACCUM_THRESH
- 4'b 1111, // index[263] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
- 4'b 1111, // index[264] ALERT_HANDLER_CLASSD_PHASE0_CYC
- 4'b 1111, // index[265] ALERT_HANDLER_CLASSD_PHASE1_CYC
- 4'b 1111, // index[266] ALERT_HANDLER_CLASSD_PHASE2_CYC
- 4'b 1111, // index[267] ALERT_HANDLER_CLASSD_PHASE3_CYC
- 4'b 1111, // index[268] ALERT_HANDLER_CLASSD_ESC_CNT
- 4'b 0001 // index[269] ALERT_HANDLER_CLASSD_STATE
+ 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_REGWEN_48
+ 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_REGWEN_49
+ 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_REGWEN_50
+ 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_0
+ 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_1
+ 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_2
+ 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_3
+ 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_4
+ 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_5
+ 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_6
+ 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_7
+ 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_8
+ 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_9
+ 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_10
+ 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_11
+ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_12
+ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_13
+ 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_14
+ 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_15
+ 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_16
+ 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_17
+ 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_18
+ 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_19
+ 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_20
+ 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_21
+ 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_22
+ 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_23
+ 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_24
+ 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_25
+ 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_26
+ 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_27
+ 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_28
+ 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_29
+ 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_30
+ 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_31
+ 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_32
+ 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_33
+ 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_34
+ 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_35
+ 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_36
+ 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_37
+ 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_38
+ 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_39
+ 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_40
+ 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_41
+ 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_42
+ 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_43
+ 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_44
+ 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_45
+ 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_46
+ 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_47
+ 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_48
+ 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_49
+ 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_50
+ 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_0
+ 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_1
+ 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_2
+ 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_3
+ 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_4
+ 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_5
+ 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_6
+ 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_7
+ 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_8
+ 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_9
+ 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_10
+ 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_11
+ 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_12
+ 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_13
+ 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_14
+ 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_15
+ 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_16
+ 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_17
+ 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_18
+ 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_19
+ 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_20
+ 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_21
+ 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_22
+ 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_23
+ 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_24
+ 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_25
+ 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_26
+ 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_27
+ 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_28
+ 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_29
+ 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_30
+ 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_31
+ 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_32
+ 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_33
+ 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_34
+ 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_35
+ 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_36
+ 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_37
+ 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_38
+ 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_39
+ 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_40
+ 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_41
+ 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_42
+ 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_43
+ 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_44
+ 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_45
+ 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_46
+ 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_47
+ 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_48
+ 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_49
+ 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_50
+ 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_0
+ 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_1
+ 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_2
+ 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_3
+ 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_4
+ 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_5
+ 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_6
+ 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_7
+ 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_8
+ 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_9
+ 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_10
+ 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CAUSE_11
+ 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CAUSE_12
+ 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CAUSE_13
+ 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CAUSE_14
+ 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CAUSE_15
+ 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CAUSE_16
+ 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CAUSE_17
+ 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CAUSE_18
+ 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CAUSE_19
+ 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CAUSE_20
+ 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_21
+ 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_22
+ 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CAUSE_23
+ 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CAUSE_24
+ 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CAUSE_25
+ 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CAUSE_26
+ 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_27
+ 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_28
+ 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_29
+ 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_30
+ 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_31
+ 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_32
+ 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_33
+ 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_34
+ 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_35
+ 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_36
+ 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_37
+ 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_38
+ 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_39
+ 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_40
+ 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_41
+ 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_42
+ 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_43
+ 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_44
+ 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_45
+ 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_46
+ 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_47
+ 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_48
+ 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_49
+ 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_50
+ 4'b 0001, // index[210] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+ 4'b 0001, // index[211] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+ 4'b 0001, // index[212] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+ 4'b 0001, // index[213] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+ 4'b 0001, // index[214] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+ 4'b 0001, // index[215] ALERT_HANDLER_LOC_ALERT_EN_0
+ 4'b 0001, // index[216] ALERT_HANDLER_LOC_ALERT_EN_1
+ 4'b 0001, // index[217] ALERT_HANDLER_LOC_ALERT_EN_2
+ 4'b 0001, // index[218] ALERT_HANDLER_LOC_ALERT_EN_3
+ 4'b 0001, // index[219] ALERT_HANDLER_LOC_ALERT_EN_4
+ 4'b 0001, // index[220] ALERT_HANDLER_LOC_ALERT_CLASS_0
+ 4'b 0001, // index[221] ALERT_HANDLER_LOC_ALERT_CLASS_1
+ 4'b 0001, // index[222] ALERT_HANDLER_LOC_ALERT_CLASS_2
+ 4'b 0001, // index[223] ALERT_HANDLER_LOC_ALERT_CLASS_3
+ 4'b 0001, // index[224] ALERT_HANDLER_LOC_ALERT_CLASS_4
+ 4'b 0001, // index[225] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+ 4'b 0001, // index[226] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+ 4'b 0001, // index[227] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+ 4'b 0001, // index[228] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+ 4'b 0001, // index[229] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+ 4'b 0001, // index[230] ALERT_HANDLER_CLASSA_REGWEN
+ 4'b 0011, // index[231] ALERT_HANDLER_CLASSA_CTRL
+ 4'b 0001, // index[232] ALERT_HANDLER_CLASSA_CLR_REGWEN
+ 4'b 0001, // index[233] ALERT_HANDLER_CLASSA_CLR
+ 4'b 0011, // index[234] ALERT_HANDLER_CLASSA_ACCUM_CNT
+ 4'b 0011, // index[235] ALERT_HANDLER_CLASSA_ACCUM_THRESH
+ 4'b 1111, // index[236] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
+ 4'b 1111, // index[237] ALERT_HANDLER_CLASSA_PHASE0_CYC
+ 4'b 1111, // index[238] ALERT_HANDLER_CLASSA_PHASE1_CYC
+ 4'b 1111, // index[239] ALERT_HANDLER_CLASSA_PHASE2_CYC
+ 4'b 1111, // index[240] ALERT_HANDLER_CLASSA_PHASE3_CYC
+ 4'b 1111, // index[241] ALERT_HANDLER_CLASSA_ESC_CNT
+ 4'b 0001, // index[242] ALERT_HANDLER_CLASSA_STATE
+ 4'b 0001, // index[243] ALERT_HANDLER_CLASSB_REGWEN
+ 4'b 0011, // index[244] ALERT_HANDLER_CLASSB_CTRL
+ 4'b 0001, // index[245] ALERT_HANDLER_CLASSB_CLR_REGWEN
+ 4'b 0001, // index[246] ALERT_HANDLER_CLASSB_CLR
+ 4'b 0011, // index[247] ALERT_HANDLER_CLASSB_ACCUM_CNT
+ 4'b 0011, // index[248] ALERT_HANDLER_CLASSB_ACCUM_THRESH
+ 4'b 1111, // index[249] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
+ 4'b 1111, // index[250] ALERT_HANDLER_CLASSB_PHASE0_CYC
+ 4'b 1111, // index[251] ALERT_HANDLER_CLASSB_PHASE1_CYC
+ 4'b 1111, // index[252] ALERT_HANDLER_CLASSB_PHASE2_CYC
+ 4'b 1111, // index[253] ALERT_HANDLER_CLASSB_PHASE3_CYC
+ 4'b 1111, // index[254] ALERT_HANDLER_CLASSB_ESC_CNT
+ 4'b 0001, // index[255] ALERT_HANDLER_CLASSB_STATE
+ 4'b 0001, // index[256] ALERT_HANDLER_CLASSC_REGWEN
+ 4'b 0011, // index[257] ALERT_HANDLER_CLASSC_CTRL
+ 4'b 0001, // index[258] ALERT_HANDLER_CLASSC_CLR_REGWEN
+ 4'b 0001, // index[259] ALERT_HANDLER_CLASSC_CLR
+ 4'b 0011, // index[260] ALERT_HANDLER_CLASSC_ACCUM_CNT
+ 4'b 0011, // index[261] ALERT_HANDLER_CLASSC_ACCUM_THRESH
+ 4'b 1111, // index[262] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
+ 4'b 1111, // index[263] ALERT_HANDLER_CLASSC_PHASE0_CYC
+ 4'b 1111, // index[264] ALERT_HANDLER_CLASSC_PHASE1_CYC
+ 4'b 1111, // index[265] ALERT_HANDLER_CLASSC_PHASE2_CYC
+ 4'b 1111, // index[266] ALERT_HANDLER_CLASSC_PHASE3_CYC
+ 4'b 1111, // index[267] ALERT_HANDLER_CLASSC_ESC_CNT
+ 4'b 0001, // index[268] ALERT_HANDLER_CLASSC_STATE
+ 4'b 0001, // index[269] ALERT_HANDLER_CLASSD_REGWEN
+ 4'b 0011, // index[270] ALERT_HANDLER_CLASSD_CTRL
+ 4'b 0001, // index[271] ALERT_HANDLER_CLASSD_CLR_REGWEN
+ 4'b 0001, // index[272] ALERT_HANDLER_CLASSD_CLR
+ 4'b 0011, // index[273] ALERT_HANDLER_CLASSD_ACCUM_CNT
+ 4'b 0011, // index[274] ALERT_HANDLER_CLASSD_ACCUM_THRESH
+ 4'b 1111, // index[275] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
+ 4'b 1111, // index[276] ALERT_HANDLER_CLASSD_PHASE0_CYC
+ 4'b 1111, // index[277] ALERT_HANDLER_CLASSD_PHASE1_CYC
+ 4'b 1111, // index[278] ALERT_HANDLER_CLASSD_PHASE2_CYC
+ 4'b 1111, // index[279] ALERT_HANDLER_CLASSD_PHASE3_CYC
+ 4'b 1111, // index[280] ALERT_HANDLER_CLASSD_ESC_CNT
+ 4'b 0001 // index[281] ALERT_HANDLER_CLASSD_STATE
};
endpackage
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index fe26b75..4fa5b7e 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -289,6 +289,15 @@
logic alert_regwen_47_qs;
logic alert_regwen_47_wd;
logic alert_regwen_47_we;
+ logic alert_regwen_48_qs;
+ logic alert_regwen_48_wd;
+ logic alert_regwen_48_we;
+ logic alert_regwen_49_qs;
+ logic alert_regwen_49_wd;
+ logic alert_regwen_49_we;
+ logic alert_regwen_50_qs;
+ logic alert_regwen_50_wd;
+ logic alert_regwen_50_we;
logic alert_en_0_qs;
logic alert_en_0_wd;
logic alert_en_0_we;
@@ -433,6 +442,15 @@
logic alert_en_47_qs;
logic alert_en_47_wd;
logic alert_en_47_we;
+ logic alert_en_48_qs;
+ logic alert_en_48_wd;
+ logic alert_en_48_we;
+ logic alert_en_49_qs;
+ logic alert_en_49_wd;
+ logic alert_en_49_we;
+ logic alert_en_50_qs;
+ logic alert_en_50_wd;
+ logic alert_en_50_we;
logic [1:0] alert_class_0_qs;
logic [1:0] alert_class_0_wd;
logic alert_class_0_we;
@@ -577,6 +595,15 @@
logic [1:0] alert_class_47_qs;
logic [1:0] alert_class_47_wd;
logic alert_class_47_we;
+ logic [1:0] alert_class_48_qs;
+ logic [1:0] alert_class_48_wd;
+ logic alert_class_48_we;
+ logic [1:0] alert_class_49_qs;
+ logic [1:0] alert_class_49_wd;
+ logic alert_class_49_we;
+ logic [1:0] alert_class_50_qs;
+ logic [1:0] alert_class_50_wd;
+ logic alert_class_50_we;
logic alert_cause_0_qs;
logic alert_cause_0_wd;
logic alert_cause_0_we;
@@ -721,6 +748,15 @@
logic alert_cause_47_qs;
logic alert_cause_47_wd;
logic alert_cause_47_we;
+ logic alert_cause_48_qs;
+ logic alert_cause_48_wd;
+ logic alert_cause_48_we;
+ logic alert_cause_49_qs;
+ logic alert_cause_49_wd;
+ logic alert_cause_49_we;
+ logic alert_cause_50_qs;
+ logic alert_cause_50_wd;
+ logic alert_cause_50_we;
logic loc_alert_regwen_0_qs;
logic loc_alert_regwen_0_wd;
logic loc_alert_regwen_0_we;
@@ -2683,6 +2719,87 @@
.qs (alert_regwen_47_qs)
);
+ // Subregister 48 of Multireg alert_regwen
+ // R[alert_regwen_48]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_48_we),
+ .wd (alert_regwen_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[48].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_48_qs)
+ );
+
+ // Subregister 49 of Multireg alert_regwen
+ // R[alert_regwen_49]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_49_we),
+ .wd (alert_regwen_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[49].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_49_qs)
+ );
+
+ // Subregister 50 of Multireg alert_regwen
+ // R[alert_regwen_50]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_50_we),
+ .wd (alert_regwen_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[50].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_50_qs)
+ );
+
// Subregister 0 of Multireg alert_en
@@ -3981,6 +4098,87 @@
.qs (alert_en_47_qs)
);
+ // Subregister 48 of Multireg alert_en
+ // R[alert_en_48]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_en_48_we & alert_regwen_48_qs),
+ .wd (alert_en_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[48].q),
+
+ // to register interface (read)
+ .qs (alert_en_48_qs)
+ );
+
+ // Subregister 49 of Multireg alert_en
+ // R[alert_en_49]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_en_49_we & alert_regwen_49_qs),
+ .wd (alert_en_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[49].q),
+
+ // to register interface (read)
+ .qs (alert_en_49_qs)
+ );
+
+ // Subregister 50 of Multireg alert_en
+ // R[alert_en_50]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_en_50_we & alert_regwen_50_qs),
+ .wd (alert_en_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[50].q),
+
+ // to register interface (read)
+ .qs (alert_en_50_qs)
+ );
+
// Subregister 0 of Multireg alert_class
@@ -5279,6 +5477,87 @@
.qs (alert_class_47_qs)
);
+ // Subregister 48 of Multireg alert_class
+ // R[alert_class_48]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_class_48_we & alert_regwen_48_qs),
+ .wd (alert_class_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[48].q),
+
+ // to register interface (read)
+ .qs (alert_class_48_qs)
+ );
+
+ // Subregister 49 of Multireg alert_class
+ // R[alert_class_49]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_class_49_we & alert_regwen_49_qs),
+ .wd (alert_class_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[49].q),
+
+ // to register interface (read)
+ .qs (alert_class_49_qs)
+ );
+
+ // Subregister 50 of Multireg alert_class
+ // R[alert_class_50]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_class_50_we & alert_regwen_50_qs),
+ .wd (alert_class_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[50].q),
+
+ // to register interface (read)
+ .qs (alert_class_50_qs)
+ );
+
// Subregister 0 of Multireg alert_cause
@@ -6577,6 +6856,87 @@
.qs (alert_cause_47_qs)
);
+ // Subregister 48 of Multireg alert_cause
+ // R[alert_cause_48]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_48_we),
+ .wd (alert_cause_48_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[48].de),
+ .d (hw2reg.alert_cause[48].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[48].q),
+
+ // to register interface (read)
+ .qs (alert_cause_48_qs)
+ );
+
+ // Subregister 49 of Multireg alert_cause
+ // R[alert_cause_49]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_49_we),
+ .wd (alert_cause_49_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[49].de),
+ .d (hw2reg.alert_cause[49].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[49].q),
+
+ // to register interface (read)
+ .qs (alert_cause_49_qs)
+ );
+
+ // Subregister 50 of Multireg alert_cause
+ // R[alert_cause_50]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_50_we),
+ .wd (alert_cause_50_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[50].de),
+ .d (hw2reg.alert_cause[50].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[50].q),
+
+ // to register interface (read)
+ .qs (alert_cause_50_qs)
+ );
+
// Subregister 0 of Multireg loc_alert_regwen
@@ -9340,7 +9700,7 @@
- logic [269:0] addr_hit;
+ logic [281:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -9397,222 +9757,234 @@
addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_45_OFFSET);
addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_46_OFFSET);
addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_47_OFFSET);
- addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
- addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
- addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
- addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
- addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
- addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
- addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
- addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
- addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
- addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
- addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
- addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
- addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
- addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
- addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
- addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
- addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
- addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
- addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
- addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
- addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
- addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
- addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
- addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
- addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
- addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
- addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
- addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
- addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
- addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
- addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
- addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
- addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
- addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
- addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
- addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
- addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
- addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
- addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
- addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
- addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
- addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET);
- addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET);
- addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET);
- addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET);
- addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET);
- addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET);
- addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET);
- addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
- addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
- addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
- addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
- addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
- addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
- addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
- addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
- addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
- addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
- addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
- addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
- addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
- addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
- addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
- addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
- addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
- addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
- addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
- addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
- addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
- addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
- addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
- addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
- addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
- addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
- addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
- addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
- addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
- addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
- addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
- addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
- addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
- addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
- addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
- addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
- addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
- addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
- addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
- addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
- addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
- addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET);
- addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET);
- addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET);
- addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET);
- addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET);
- addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET);
- addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET);
- addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
- addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
- addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
- addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
- addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
- addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
- addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
- addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
- addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
- addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
- addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
- addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
- addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
- addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
- addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
- addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
- addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
- addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
- addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
- addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
- addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
- addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
- addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
- addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
- addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
- addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
- addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
- addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
- addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
- addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
- addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
- addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
- addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
- addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
- addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
- addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
- addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
- addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
- addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
- addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
- addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
- addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
- addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
- addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
- addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
- addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
- addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
- addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
- addr_hit[198] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
- addr_hit[199] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
- addr_hit[200] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
- addr_hit[201] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
- addr_hit[202] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
- addr_hit[203] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
- addr_hit[204] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
- addr_hit[205] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
- addr_hit[206] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
- addr_hit[207] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
- addr_hit[208] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
- addr_hit[209] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
- addr_hit[210] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
- addr_hit[211] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
- addr_hit[212] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
- addr_hit[213] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
- addr_hit[214] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
- addr_hit[215] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
- addr_hit[216] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
- addr_hit[217] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
- addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
- addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
- addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
- addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
- addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
- addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
- addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
- addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
- addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
- addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
- addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
- addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
- addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
- addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
- addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
- addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
- addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
- addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
- addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
- addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
- addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
- addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
- addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
- addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
- addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
- addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
- addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
- addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
- addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
- addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
- addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
- addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
- addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
- addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
- addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
- addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
- addr_hit[254] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
- addr_hit[255] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
- addr_hit[256] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
- addr_hit[257] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
- addr_hit[258] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
- addr_hit[259] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
- addr_hit[260] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
- addr_hit[261] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
- addr_hit[262] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
- addr_hit[263] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
- addr_hit[264] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
- addr_hit[265] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
- addr_hit[266] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
- addr_hit[267] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
- addr_hit[268] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
- addr_hit[269] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_48_OFFSET);
+ addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_49_OFFSET);
+ addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_50_OFFSET);
+ addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
+ addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
+ addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
+ addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
+ addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
+ addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
+ addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
+ addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
+ addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
+ addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
+ addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
+ addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
+ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
+ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
+ addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
+ addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
+ addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
+ addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
+ addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
+ addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
+ addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
+ addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
+ addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
+ addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
+ addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
+ addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
+ addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
+ addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
+ addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
+ addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
+ addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
+ addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
+ addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
+ addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
+ addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
+ addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
+ addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
+ addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
+ addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
+ addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
+ addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
+ addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET);
+ addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET);
+ addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET);
+ addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET);
+ addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET);
+ addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET);
+ addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET);
+ addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_48_OFFSET);
+ addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_49_OFFSET);
+ addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_50_OFFSET);
+ addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
+ addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
+ addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
+ addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
+ addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
+ addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
+ addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
+ addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
+ addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
+ addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
+ addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
+ addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
+ addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
+ addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
+ addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
+ addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
+ addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
+ addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
+ addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
+ addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
+ addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
+ addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
+ addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
+ addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
+ addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
+ addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
+ addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
+ addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
+ addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
+ addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
+ addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
+ addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
+ addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
+ addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
+ addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
+ addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
+ addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
+ addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
+ addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
+ addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
+ addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
+ addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET);
+ addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET);
+ addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET);
+ addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET);
+ addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET);
+ addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET);
+ addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET);
+ addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_48_OFFSET);
+ addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_49_OFFSET);
+ addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_50_OFFSET);
+ addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+ addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+ addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+ addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+ addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+ addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+ addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+ addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+ addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+ addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+ addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+ addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+ addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+ addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+ addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+ addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+ addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+ addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+ addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+ addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+ addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+ addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+ addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+ addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+ addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+ addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+ addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+ addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+ addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+ addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+ addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+ addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+ addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+ addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+ addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+ addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+ addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+ addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+ addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+ addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+ addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+ addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+ addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+ addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+ addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+ addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+ addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+ addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+ addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
+ addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
+ addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
+ addr_hit[210] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+ addr_hit[211] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+ addr_hit[212] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+ addr_hit[213] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+ addr_hit[214] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+ addr_hit[215] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
+ addr_hit[216] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
+ addr_hit[217] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
+ addr_hit[218] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
+ addr_hit[219] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
+ addr_hit[220] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
+ addr_hit[221] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
+ addr_hit[222] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
+ addr_hit[223] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
+ addr_hit[224] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
+ addr_hit[225] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+ addr_hit[226] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+ addr_hit[227] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+ addr_hit[228] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+ addr_hit[229] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+ addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+ addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+ addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+ addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+ addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+ addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+ addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+ addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+ addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+ addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+ addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+ addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+ addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+ addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+ addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+ addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+ addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+ addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+ addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+ addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+ addr_hit[254] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[255] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[256] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+ addr_hit[257] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+ addr_hit[258] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+ addr_hit[259] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+ addr_hit[260] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[261] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+ addr_hit[262] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+ addr_hit[263] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+ addr_hit[264] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+ addr_hit[265] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+ addr_hit[266] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+ addr_hit[267] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[268] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[269] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+ addr_hit[270] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+ addr_hit[271] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+ addr_hit[272] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+ addr_hit[273] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[274] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+ addr_hit[275] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+ addr_hit[276] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+ addr_hit[277] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+ addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+ addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+ addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -9889,7 +10261,19 @@
(addr_hit[266] & (|(ALERT_HANDLER_PERMIT[266] & ~reg_be))) |
(addr_hit[267] & (|(ALERT_HANDLER_PERMIT[267] & ~reg_be))) |
(addr_hit[268] & (|(ALERT_HANDLER_PERMIT[268] & ~reg_be))) |
- (addr_hit[269] & (|(ALERT_HANDLER_PERMIT[269] & ~reg_be)))));
+ (addr_hit[269] & (|(ALERT_HANDLER_PERMIT[269] & ~reg_be))) |
+ (addr_hit[270] & (|(ALERT_HANDLER_PERMIT[270] & ~reg_be))) |
+ (addr_hit[271] & (|(ALERT_HANDLER_PERMIT[271] & ~reg_be))) |
+ (addr_hit[272] & (|(ALERT_HANDLER_PERMIT[272] & ~reg_be))) |
+ (addr_hit[273] & (|(ALERT_HANDLER_PERMIT[273] & ~reg_be))) |
+ (addr_hit[274] & (|(ALERT_HANDLER_PERMIT[274] & ~reg_be))) |
+ (addr_hit[275] & (|(ALERT_HANDLER_PERMIT[275] & ~reg_be))) |
+ (addr_hit[276] & (|(ALERT_HANDLER_PERMIT[276] & ~reg_be))) |
+ (addr_hit[277] & (|(ALERT_HANDLER_PERMIT[277] & ~reg_be))) |
+ (addr_hit[278] & (|(ALERT_HANDLER_PERMIT[278] & ~reg_be))) |
+ (addr_hit[279] & (|(ALERT_HANDLER_PERMIT[279] & ~reg_be))) |
+ (addr_hit[280] & (|(ALERT_HANDLER_PERMIT[280] & ~reg_be))) |
+ (addr_hit[281] & (|(ALERT_HANDLER_PERMIT[281] & ~reg_be)))));
end
assign intr_state_classa_we = addr_hit[0] & reg_we & !reg_error;
@@ -10081,749 +10465,785 @@
assign alert_regwen_47_we = addr_hit[53] & reg_we & !reg_error;
assign alert_regwen_47_wd = reg_wdata[0];
- assign alert_en_0_we = addr_hit[54] & reg_we & !reg_error;
+ assign alert_regwen_48_we = addr_hit[54] & reg_we & !reg_error;
+ assign alert_regwen_48_wd = reg_wdata[0];
+
+ assign alert_regwen_49_we = addr_hit[55] & reg_we & !reg_error;
+ assign alert_regwen_49_wd = reg_wdata[0];
+
+ assign alert_regwen_50_we = addr_hit[56] & reg_we & !reg_error;
+ assign alert_regwen_50_wd = reg_wdata[0];
+
+ assign alert_en_0_we = addr_hit[57] & reg_we & !reg_error;
assign alert_en_0_wd = reg_wdata[0];
- assign alert_en_1_we = addr_hit[55] & reg_we & !reg_error;
+ assign alert_en_1_we = addr_hit[58] & reg_we & !reg_error;
assign alert_en_1_wd = reg_wdata[0];
- assign alert_en_2_we = addr_hit[56] & reg_we & !reg_error;
+ assign alert_en_2_we = addr_hit[59] & reg_we & !reg_error;
assign alert_en_2_wd = reg_wdata[0];
- assign alert_en_3_we = addr_hit[57] & reg_we & !reg_error;
+ assign alert_en_3_we = addr_hit[60] & reg_we & !reg_error;
assign alert_en_3_wd = reg_wdata[0];
- assign alert_en_4_we = addr_hit[58] & reg_we & !reg_error;
+ assign alert_en_4_we = addr_hit[61] & reg_we & !reg_error;
assign alert_en_4_wd = reg_wdata[0];
- assign alert_en_5_we = addr_hit[59] & reg_we & !reg_error;
+ assign alert_en_5_we = addr_hit[62] & reg_we & !reg_error;
assign alert_en_5_wd = reg_wdata[0];
- assign alert_en_6_we = addr_hit[60] & reg_we & !reg_error;
+ assign alert_en_6_we = addr_hit[63] & reg_we & !reg_error;
assign alert_en_6_wd = reg_wdata[0];
- assign alert_en_7_we = addr_hit[61] & reg_we & !reg_error;
+ assign alert_en_7_we = addr_hit[64] & reg_we & !reg_error;
assign alert_en_7_wd = reg_wdata[0];
- assign alert_en_8_we = addr_hit[62] & reg_we & !reg_error;
+ assign alert_en_8_we = addr_hit[65] & reg_we & !reg_error;
assign alert_en_8_wd = reg_wdata[0];
- assign alert_en_9_we = addr_hit[63] & reg_we & !reg_error;
+ assign alert_en_9_we = addr_hit[66] & reg_we & !reg_error;
assign alert_en_9_wd = reg_wdata[0];
- assign alert_en_10_we = addr_hit[64] & reg_we & !reg_error;
+ assign alert_en_10_we = addr_hit[67] & reg_we & !reg_error;
assign alert_en_10_wd = reg_wdata[0];
- assign alert_en_11_we = addr_hit[65] & reg_we & !reg_error;
+ assign alert_en_11_we = addr_hit[68] & reg_we & !reg_error;
assign alert_en_11_wd = reg_wdata[0];
- assign alert_en_12_we = addr_hit[66] & reg_we & !reg_error;
+ assign alert_en_12_we = addr_hit[69] & reg_we & !reg_error;
assign alert_en_12_wd = reg_wdata[0];
- assign alert_en_13_we = addr_hit[67] & reg_we & !reg_error;
+ assign alert_en_13_we = addr_hit[70] & reg_we & !reg_error;
assign alert_en_13_wd = reg_wdata[0];
- assign alert_en_14_we = addr_hit[68] & reg_we & !reg_error;
+ assign alert_en_14_we = addr_hit[71] & reg_we & !reg_error;
assign alert_en_14_wd = reg_wdata[0];
- assign alert_en_15_we = addr_hit[69] & reg_we & !reg_error;
+ assign alert_en_15_we = addr_hit[72] & reg_we & !reg_error;
assign alert_en_15_wd = reg_wdata[0];
- assign alert_en_16_we = addr_hit[70] & reg_we & !reg_error;
+ assign alert_en_16_we = addr_hit[73] & reg_we & !reg_error;
assign alert_en_16_wd = reg_wdata[0];
- assign alert_en_17_we = addr_hit[71] & reg_we & !reg_error;
+ assign alert_en_17_we = addr_hit[74] & reg_we & !reg_error;
assign alert_en_17_wd = reg_wdata[0];
- assign alert_en_18_we = addr_hit[72] & reg_we & !reg_error;
+ assign alert_en_18_we = addr_hit[75] & reg_we & !reg_error;
assign alert_en_18_wd = reg_wdata[0];
- assign alert_en_19_we = addr_hit[73] & reg_we & !reg_error;
+ assign alert_en_19_we = addr_hit[76] & reg_we & !reg_error;
assign alert_en_19_wd = reg_wdata[0];
- assign alert_en_20_we = addr_hit[74] & reg_we & !reg_error;
+ assign alert_en_20_we = addr_hit[77] & reg_we & !reg_error;
assign alert_en_20_wd = reg_wdata[0];
- assign alert_en_21_we = addr_hit[75] & reg_we & !reg_error;
+ assign alert_en_21_we = addr_hit[78] & reg_we & !reg_error;
assign alert_en_21_wd = reg_wdata[0];
- assign alert_en_22_we = addr_hit[76] & reg_we & !reg_error;
+ assign alert_en_22_we = addr_hit[79] & reg_we & !reg_error;
assign alert_en_22_wd = reg_wdata[0];
- assign alert_en_23_we = addr_hit[77] & reg_we & !reg_error;
+ assign alert_en_23_we = addr_hit[80] & reg_we & !reg_error;
assign alert_en_23_wd = reg_wdata[0];
- assign alert_en_24_we = addr_hit[78] & reg_we & !reg_error;
+ assign alert_en_24_we = addr_hit[81] & reg_we & !reg_error;
assign alert_en_24_wd = reg_wdata[0];
- assign alert_en_25_we = addr_hit[79] & reg_we & !reg_error;
+ assign alert_en_25_we = addr_hit[82] & reg_we & !reg_error;
assign alert_en_25_wd = reg_wdata[0];
- assign alert_en_26_we = addr_hit[80] & reg_we & !reg_error;
+ assign alert_en_26_we = addr_hit[83] & reg_we & !reg_error;
assign alert_en_26_wd = reg_wdata[0];
- assign alert_en_27_we = addr_hit[81] & reg_we & !reg_error;
+ assign alert_en_27_we = addr_hit[84] & reg_we & !reg_error;
assign alert_en_27_wd = reg_wdata[0];
- assign alert_en_28_we = addr_hit[82] & reg_we & !reg_error;
+ assign alert_en_28_we = addr_hit[85] & reg_we & !reg_error;
assign alert_en_28_wd = reg_wdata[0];
- assign alert_en_29_we = addr_hit[83] & reg_we & !reg_error;
+ assign alert_en_29_we = addr_hit[86] & reg_we & !reg_error;
assign alert_en_29_wd = reg_wdata[0];
- assign alert_en_30_we = addr_hit[84] & reg_we & !reg_error;
+ assign alert_en_30_we = addr_hit[87] & reg_we & !reg_error;
assign alert_en_30_wd = reg_wdata[0];
- assign alert_en_31_we = addr_hit[85] & reg_we & !reg_error;
+ assign alert_en_31_we = addr_hit[88] & reg_we & !reg_error;
assign alert_en_31_wd = reg_wdata[0];
- assign alert_en_32_we = addr_hit[86] & reg_we & !reg_error;
+ assign alert_en_32_we = addr_hit[89] & reg_we & !reg_error;
assign alert_en_32_wd = reg_wdata[0];
- assign alert_en_33_we = addr_hit[87] & reg_we & !reg_error;
+ assign alert_en_33_we = addr_hit[90] & reg_we & !reg_error;
assign alert_en_33_wd = reg_wdata[0];
- assign alert_en_34_we = addr_hit[88] & reg_we & !reg_error;
+ assign alert_en_34_we = addr_hit[91] & reg_we & !reg_error;
assign alert_en_34_wd = reg_wdata[0];
- assign alert_en_35_we = addr_hit[89] & reg_we & !reg_error;
+ assign alert_en_35_we = addr_hit[92] & reg_we & !reg_error;
assign alert_en_35_wd = reg_wdata[0];
- assign alert_en_36_we = addr_hit[90] & reg_we & !reg_error;
+ assign alert_en_36_we = addr_hit[93] & reg_we & !reg_error;
assign alert_en_36_wd = reg_wdata[0];
- assign alert_en_37_we = addr_hit[91] & reg_we & !reg_error;
+ assign alert_en_37_we = addr_hit[94] & reg_we & !reg_error;
assign alert_en_37_wd = reg_wdata[0];
- assign alert_en_38_we = addr_hit[92] & reg_we & !reg_error;
+ assign alert_en_38_we = addr_hit[95] & reg_we & !reg_error;
assign alert_en_38_wd = reg_wdata[0];
- assign alert_en_39_we = addr_hit[93] & reg_we & !reg_error;
+ assign alert_en_39_we = addr_hit[96] & reg_we & !reg_error;
assign alert_en_39_wd = reg_wdata[0];
- assign alert_en_40_we = addr_hit[94] & reg_we & !reg_error;
+ assign alert_en_40_we = addr_hit[97] & reg_we & !reg_error;
assign alert_en_40_wd = reg_wdata[0];
- assign alert_en_41_we = addr_hit[95] & reg_we & !reg_error;
+ assign alert_en_41_we = addr_hit[98] & reg_we & !reg_error;
assign alert_en_41_wd = reg_wdata[0];
- assign alert_en_42_we = addr_hit[96] & reg_we & !reg_error;
+ assign alert_en_42_we = addr_hit[99] & reg_we & !reg_error;
assign alert_en_42_wd = reg_wdata[0];
- assign alert_en_43_we = addr_hit[97] & reg_we & !reg_error;
+ assign alert_en_43_we = addr_hit[100] & reg_we & !reg_error;
assign alert_en_43_wd = reg_wdata[0];
- assign alert_en_44_we = addr_hit[98] & reg_we & !reg_error;
+ assign alert_en_44_we = addr_hit[101] & reg_we & !reg_error;
assign alert_en_44_wd = reg_wdata[0];
- assign alert_en_45_we = addr_hit[99] & reg_we & !reg_error;
+ assign alert_en_45_we = addr_hit[102] & reg_we & !reg_error;
assign alert_en_45_wd = reg_wdata[0];
- assign alert_en_46_we = addr_hit[100] & reg_we & !reg_error;
+ assign alert_en_46_we = addr_hit[103] & reg_we & !reg_error;
assign alert_en_46_wd = reg_wdata[0];
- assign alert_en_47_we = addr_hit[101] & reg_we & !reg_error;
+ assign alert_en_47_we = addr_hit[104] & reg_we & !reg_error;
assign alert_en_47_wd = reg_wdata[0];
- assign alert_class_0_we = addr_hit[102] & reg_we & !reg_error;
+ assign alert_en_48_we = addr_hit[105] & reg_we & !reg_error;
+ assign alert_en_48_wd = reg_wdata[0];
+
+ assign alert_en_49_we = addr_hit[106] & reg_we & !reg_error;
+ assign alert_en_49_wd = reg_wdata[0];
+
+ assign alert_en_50_we = addr_hit[107] & reg_we & !reg_error;
+ assign alert_en_50_wd = reg_wdata[0];
+
+ assign alert_class_0_we = addr_hit[108] & reg_we & !reg_error;
assign alert_class_0_wd = reg_wdata[1:0];
- assign alert_class_1_we = addr_hit[103] & reg_we & !reg_error;
+ assign alert_class_1_we = addr_hit[109] & reg_we & !reg_error;
assign alert_class_1_wd = reg_wdata[1:0];
- assign alert_class_2_we = addr_hit[104] & reg_we & !reg_error;
+ assign alert_class_2_we = addr_hit[110] & reg_we & !reg_error;
assign alert_class_2_wd = reg_wdata[1:0];
- assign alert_class_3_we = addr_hit[105] & reg_we & !reg_error;
+ assign alert_class_3_we = addr_hit[111] & reg_we & !reg_error;
assign alert_class_3_wd = reg_wdata[1:0];
- assign alert_class_4_we = addr_hit[106] & reg_we & !reg_error;
+ assign alert_class_4_we = addr_hit[112] & reg_we & !reg_error;
assign alert_class_4_wd = reg_wdata[1:0];
- assign alert_class_5_we = addr_hit[107] & reg_we & !reg_error;
+ assign alert_class_5_we = addr_hit[113] & reg_we & !reg_error;
assign alert_class_5_wd = reg_wdata[1:0];
- assign alert_class_6_we = addr_hit[108] & reg_we & !reg_error;
+ assign alert_class_6_we = addr_hit[114] & reg_we & !reg_error;
assign alert_class_6_wd = reg_wdata[1:0];
- assign alert_class_7_we = addr_hit[109] & reg_we & !reg_error;
+ assign alert_class_7_we = addr_hit[115] & reg_we & !reg_error;
assign alert_class_7_wd = reg_wdata[1:0];
- assign alert_class_8_we = addr_hit[110] & reg_we & !reg_error;
+ assign alert_class_8_we = addr_hit[116] & reg_we & !reg_error;
assign alert_class_8_wd = reg_wdata[1:0];
- assign alert_class_9_we = addr_hit[111] & reg_we & !reg_error;
+ assign alert_class_9_we = addr_hit[117] & reg_we & !reg_error;
assign alert_class_9_wd = reg_wdata[1:0];
- assign alert_class_10_we = addr_hit[112] & reg_we & !reg_error;
+ assign alert_class_10_we = addr_hit[118] & reg_we & !reg_error;
assign alert_class_10_wd = reg_wdata[1:0];
- assign alert_class_11_we = addr_hit[113] & reg_we & !reg_error;
+ assign alert_class_11_we = addr_hit[119] & reg_we & !reg_error;
assign alert_class_11_wd = reg_wdata[1:0];
- assign alert_class_12_we = addr_hit[114] & reg_we & !reg_error;
+ assign alert_class_12_we = addr_hit[120] & reg_we & !reg_error;
assign alert_class_12_wd = reg_wdata[1:0];
- assign alert_class_13_we = addr_hit[115] & reg_we & !reg_error;
+ assign alert_class_13_we = addr_hit[121] & reg_we & !reg_error;
assign alert_class_13_wd = reg_wdata[1:0];
- assign alert_class_14_we = addr_hit[116] & reg_we & !reg_error;
+ assign alert_class_14_we = addr_hit[122] & reg_we & !reg_error;
assign alert_class_14_wd = reg_wdata[1:0];
- assign alert_class_15_we = addr_hit[117] & reg_we & !reg_error;
+ assign alert_class_15_we = addr_hit[123] & reg_we & !reg_error;
assign alert_class_15_wd = reg_wdata[1:0];
- assign alert_class_16_we = addr_hit[118] & reg_we & !reg_error;
+ assign alert_class_16_we = addr_hit[124] & reg_we & !reg_error;
assign alert_class_16_wd = reg_wdata[1:0];
- assign alert_class_17_we = addr_hit[119] & reg_we & !reg_error;
+ assign alert_class_17_we = addr_hit[125] & reg_we & !reg_error;
assign alert_class_17_wd = reg_wdata[1:0];
- assign alert_class_18_we = addr_hit[120] & reg_we & !reg_error;
+ assign alert_class_18_we = addr_hit[126] & reg_we & !reg_error;
assign alert_class_18_wd = reg_wdata[1:0];
- assign alert_class_19_we = addr_hit[121] & reg_we & !reg_error;
+ assign alert_class_19_we = addr_hit[127] & reg_we & !reg_error;
assign alert_class_19_wd = reg_wdata[1:0];
- assign alert_class_20_we = addr_hit[122] & reg_we & !reg_error;
+ assign alert_class_20_we = addr_hit[128] & reg_we & !reg_error;
assign alert_class_20_wd = reg_wdata[1:0];
- assign alert_class_21_we = addr_hit[123] & reg_we & !reg_error;
+ assign alert_class_21_we = addr_hit[129] & reg_we & !reg_error;
assign alert_class_21_wd = reg_wdata[1:0];
- assign alert_class_22_we = addr_hit[124] & reg_we & !reg_error;
+ assign alert_class_22_we = addr_hit[130] & reg_we & !reg_error;
assign alert_class_22_wd = reg_wdata[1:0];
- assign alert_class_23_we = addr_hit[125] & reg_we & !reg_error;
+ assign alert_class_23_we = addr_hit[131] & reg_we & !reg_error;
assign alert_class_23_wd = reg_wdata[1:0];
- assign alert_class_24_we = addr_hit[126] & reg_we & !reg_error;
+ assign alert_class_24_we = addr_hit[132] & reg_we & !reg_error;
assign alert_class_24_wd = reg_wdata[1:0];
- assign alert_class_25_we = addr_hit[127] & reg_we & !reg_error;
+ assign alert_class_25_we = addr_hit[133] & reg_we & !reg_error;
assign alert_class_25_wd = reg_wdata[1:0];
- assign alert_class_26_we = addr_hit[128] & reg_we & !reg_error;
+ assign alert_class_26_we = addr_hit[134] & reg_we & !reg_error;
assign alert_class_26_wd = reg_wdata[1:0];
- assign alert_class_27_we = addr_hit[129] & reg_we & !reg_error;
+ assign alert_class_27_we = addr_hit[135] & reg_we & !reg_error;
assign alert_class_27_wd = reg_wdata[1:0];
- assign alert_class_28_we = addr_hit[130] & reg_we & !reg_error;
+ assign alert_class_28_we = addr_hit[136] & reg_we & !reg_error;
assign alert_class_28_wd = reg_wdata[1:0];
- assign alert_class_29_we = addr_hit[131] & reg_we & !reg_error;
+ assign alert_class_29_we = addr_hit[137] & reg_we & !reg_error;
assign alert_class_29_wd = reg_wdata[1:0];
- assign alert_class_30_we = addr_hit[132] & reg_we & !reg_error;
+ assign alert_class_30_we = addr_hit[138] & reg_we & !reg_error;
assign alert_class_30_wd = reg_wdata[1:0];
- assign alert_class_31_we = addr_hit[133] & reg_we & !reg_error;
+ assign alert_class_31_we = addr_hit[139] & reg_we & !reg_error;
assign alert_class_31_wd = reg_wdata[1:0];
- assign alert_class_32_we = addr_hit[134] & reg_we & !reg_error;
+ assign alert_class_32_we = addr_hit[140] & reg_we & !reg_error;
assign alert_class_32_wd = reg_wdata[1:0];
- assign alert_class_33_we = addr_hit[135] & reg_we & !reg_error;
+ assign alert_class_33_we = addr_hit[141] & reg_we & !reg_error;
assign alert_class_33_wd = reg_wdata[1:0];
- assign alert_class_34_we = addr_hit[136] & reg_we & !reg_error;
+ assign alert_class_34_we = addr_hit[142] & reg_we & !reg_error;
assign alert_class_34_wd = reg_wdata[1:0];
- assign alert_class_35_we = addr_hit[137] & reg_we & !reg_error;
+ assign alert_class_35_we = addr_hit[143] & reg_we & !reg_error;
assign alert_class_35_wd = reg_wdata[1:0];
- assign alert_class_36_we = addr_hit[138] & reg_we & !reg_error;
+ assign alert_class_36_we = addr_hit[144] & reg_we & !reg_error;
assign alert_class_36_wd = reg_wdata[1:0];
- assign alert_class_37_we = addr_hit[139] & reg_we & !reg_error;
+ assign alert_class_37_we = addr_hit[145] & reg_we & !reg_error;
assign alert_class_37_wd = reg_wdata[1:0];
- assign alert_class_38_we = addr_hit[140] & reg_we & !reg_error;
+ assign alert_class_38_we = addr_hit[146] & reg_we & !reg_error;
assign alert_class_38_wd = reg_wdata[1:0];
- assign alert_class_39_we = addr_hit[141] & reg_we & !reg_error;
+ assign alert_class_39_we = addr_hit[147] & reg_we & !reg_error;
assign alert_class_39_wd = reg_wdata[1:0];
- assign alert_class_40_we = addr_hit[142] & reg_we & !reg_error;
+ assign alert_class_40_we = addr_hit[148] & reg_we & !reg_error;
assign alert_class_40_wd = reg_wdata[1:0];
- assign alert_class_41_we = addr_hit[143] & reg_we & !reg_error;
+ assign alert_class_41_we = addr_hit[149] & reg_we & !reg_error;
assign alert_class_41_wd = reg_wdata[1:0];
- assign alert_class_42_we = addr_hit[144] & reg_we & !reg_error;
+ assign alert_class_42_we = addr_hit[150] & reg_we & !reg_error;
assign alert_class_42_wd = reg_wdata[1:0];
- assign alert_class_43_we = addr_hit[145] & reg_we & !reg_error;
+ assign alert_class_43_we = addr_hit[151] & reg_we & !reg_error;
assign alert_class_43_wd = reg_wdata[1:0];
- assign alert_class_44_we = addr_hit[146] & reg_we & !reg_error;
+ assign alert_class_44_we = addr_hit[152] & reg_we & !reg_error;
assign alert_class_44_wd = reg_wdata[1:0];
- assign alert_class_45_we = addr_hit[147] & reg_we & !reg_error;
+ assign alert_class_45_we = addr_hit[153] & reg_we & !reg_error;
assign alert_class_45_wd = reg_wdata[1:0];
- assign alert_class_46_we = addr_hit[148] & reg_we & !reg_error;
+ assign alert_class_46_we = addr_hit[154] & reg_we & !reg_error;
assign alert_class_46_wd = reg_wdata[1:0];
- assign alert_class_47_we = addr_hit[149] & reg_we & !reg_error;
+ assign alert_class_47_we = addr_hit[155] & reg_we & !reg_error;
assign alert_class_47_wd = reg_wdata[1:0];
- assign alert_cause_0_we = addr_hit[150] & reg_we & !reg_error;
+ assign alert_class_48_we = addr_hit[156] & reg_we & !reg_error;
+ assign alert_class_48_wd = reg_wdata[1:0];
+
+ assign alert_class_49_we = addr_hit[157] & reg_we & !reg_error;
+ assign alert_class_49_wd = reg_wdata[1:0];
+
+ assign alert_class_50_we = addr_hit[158] & reg_we & !reg_error;
+ assign alert_class_50_wd = reg_wdata[1:0];
+
+ assign alert_cause_0_we = addr_hit[159] & reg_we & !reg_error;
assign alert_cause_0_wd = reg_wdata[0];
- assign alert_cause_1_we = addr_hit[151] & reg_we & !reg_error;
+ assign alert_cause_1_we = addr_hit[160] & reg_we & !reg_error;
assign alert_cause_1_wd = reg_wdata[0];
- assign alert_cause_2_we = addr_hit[152] & reg_we & !reg_error;
+ assign alert_cause_2_we = addr_hit[161] & reg_we & !reg_error;
assign alert_cause_2_wd = reg_wdata[0];
- assign alert_cause_3_we = addr_hit[153] & reg_we & !reg_error;
+ assign alert_cause_3_we = addr_hit[162] & reg_we & !reg_error;
assign alert_cause_3_wd = reg_wdata[0];
- assign alert_cause_4_we = addr_hit[154] & reg_we & !reg_error;
+ assign alert_cause_4_we = addr_hit[163] & reg_we & !reg_error;
assign alert_cause_4_wd = reg_wdata[0];
- assign alert_cause_5_we = addr_hit[155] & reg_we & !reg_error;
+ assign alert_cause_5_we = addr_hit[164] & reg_we & !reg_error;
assign alert_cause_5_wd = reg_wdata[0];
- assign alert_cause_6_we = addr_hit[156] & reg_we & !reg_error;
+ assign alert_cause_6_we = addr_hit[165] & reg_we & !reg_error;
assign alert_cause_6_wd = reg_wdata[0];
- assign alert_cause_7_we = addr_hit[157] & reg_we & !reg_error;
+ assign alert_cause_7_we = addr_hit[166] & reg_we & !reg_error;
assign alert_cause_7_wd = reg_wdata[0];
- assign alert_cause_8_we = addr_hit[158] & reg_we & !reg_error;
+ assign alert_cause_8_we = addr_hit[167] & reg_we & !reg_error;
assign alert_cause_8_wd = reg_wdata[0];
- assign alert_cause_9_we = addr_hit[159] & reg_we & !reg_error;
+ assign alert_cause_9_we = addr_hit[168] & reg_we & !reg_error;
assign alert_cause_9_wd = reg_wdata[0];
- assign alert_cause_10_we = addr_hit[160] & reg_we & !reg_error;
+ assign alert_cause_10_we = addr_hit[169] & reg_we & !reg_error;
assign alert_cause_10_wd = reg_wdata[0];
- assign alert_cause_11_we = addr_hit[161] & reg_we & !reg_error;
+ assign alert_cause_11_we = addr_hit[170] & reg_we & !reg_error;
assign alert_cause_11_wd = reg_wdata[0];
- assign alert_cause_12_we = addr_hit[162] & reg_we & !reg_error;
+ assign alert_cause_12_we = addr_hit[171] & reg_we & !reg_error;
assign alert_cause_12_wd = reg_wdata[0];
- assign alert_cause_13_we = addr_hit[163] & reg_we & !reg_error;
+ assign alert_cause_13_we = addr_hit[172] & reg_we & !reg_error;
assign alert_cause_13_wd = reg_wdata[0];
- assign alert_cause_14_we = addr_hit[164] & reg_we & !reg_error;
+ assign alert_cause_14_we = addr_hit[173] & reg_we & !reg_error;
assign alert_cause_14_wd = reg_wdata[0];
- assign alert_cause_15_we = addr_hit[165] & reg_we & !reg_error;
+ assign alert_cause_15_we = addr_hit[174] & reg_we & !reg_error;
assign alert_cause_15_wd = reg_wdata[0];
- assign alert_cause_16_we = addr_hit[166] & reg_we & !reg_error;
+ assign alert_cause_16_we = addr_hit[175] & reg_we & !reg_error;
assign alert_cause_16_wd = reg_wdata[0];
- assign alert_cause_17_we = addr_hit[167] & reg_we & !reg_error;
+ assign alert_cause_17_we = addr_hit[176] & reg_we & !reg_error;
assign alert_cause_17_wd = reg_wdata[0];
- assign alert_cause_18_we = addr_hit[168] & reg_we & !reg_error;
+ assign alert_cause_18_we = addr_hit[177] & reg_we & !reg_error;
assign alert_cause_18_wd = reg_wdata[0];
- assign alert_cause_19_we = addr_hit[169] & reg_we & !reg_error;
+ assign alert_cause_19_we = addr_hit[178] & reg_we & !reg_error;
assign alert_cause_19_wd = reg_wdata[0];
- assign alert_cause_20_we = addr_hit[170] & reg_we & !reg_error;
+ assign alert_cause_20_we = addr_hit[179] & reg_we & !reg_error;
assign alert_cause_20_wd = reg_wdata[0];
- assign alert_cause_21_we = addr_hit[171] & reg_we & !reg_error;
+ assign alert_cause_21_we = addr_hit[180] & reg_we & !reg_error;
assign alert_cause_21_wd = reg_wdata[0];
- assign alert_cause_22_we = addr_hit[172] & reg_we & !reg_error;
+ assign alert_cause_22_we = addr_hit[181] & reg_we & !reg_error;
assign alert_cause_22_wd = reg_wdata[0];
- assign alert_cause_23_we = addr_hit[173] & reg_we & !reg_error;
+ assign alert_cause_23_we = addr_hit[182] & reg_we & !reg_error;
assign alert_cause_23_wd = reg_wdata[0];
- assign alert_cause_24_we = addr_hit[174] & reg_we & !reg_error;
+ assign alert_cause_24_we = addr_hit[183] & reg_we & !reg_error;
assign alert_cause_24_wd = reg_wdata[0];
- assign alert_cause_25_we = addr_hit[175] & reg_we & !reg_error;
+ assign alert_cause_25_we = addr_hit[184] & reg_we & !reg_error;
assign alert_cause_25_wd = reg_wdata[0];
- assign alert_cause_26_we = addr_hit[176] & reg_we & !reg_error;
+ assign alert_cause_26_we = addr_hit[185] & reg_we & !reg_error;
assign alert_cause_26_wd = reg_wdata[0];
- assign alert_cause_27_we = addr_hit[177] & reg_we & !reg_error;
+ assign alert_cause_27_we = addr_hit[186] & reg_we & !reg_error;
assign alert_cause_27_wd = reg_wdata[0];
- assign alert_cause_28_we = addr_hit[178] & reg_we & !reg_error;
+ assign alert_cause_28_we = addr_hit[187] & reg_we & !reg_error;
assign alert_cause_28_wd = reg_wdata[0];
- assign alert_cause_29_we = addr_hit[179] & reg_we & !reg_error;
+ assign alert_cause_29_we = addr_hit[188] & reg_we & !reg_error;
assign alert_cause_29_wd = reg_wdata[0];
- assign alert_cause_30_we = addr_hit[180] & reg_we & !reg_error;
+ assign alert_cause_30_we = addr_hit[189] & reg_we & !reg_error;
assign alert_cause_30_wd = reg_wdata[0];
- assign alert_cause_31_we = addr_hit[181] & reg_we & !reg_error;
+ assign alert_cause_31_we = addr_hit[190] & reg_we & !reg_error;
assign alert_cause_31_wd = reg_wdata[0];
- assign alert_cause_32_we = addr_hit[182] & reg_we & !reg_error;
+ assign alert_cause_32_we = addr_hit[191] & reg_we & !reg_error;
assign alert_cause_32_wd = reg_wdata[0];
- assign alert_cause_33_we = addr_hit[183] & reg_we & !reg_error;
+ assign alert_cause_33_we = addr_hit[192] & reg_we & !reg_error;
assign alert_cause_33_wd = reg_wdata[0];
- assign alert_cause_34_we = addr_hit[184] & reg_we & !reg_error;
+ assign alert_cause_34_we = addr_hit[193] & reg_we & !reg_error;
assign alert_cause_34_wd = reg_wdata[0];
- assign alert_cause_35_we = addr_hit[185] & reg_we & !reg_error;
+ assign alert_cause_35_we = addr_hit[194] & reg_we & !reg_error;
assign alert_cause_35_wd = reg_wdata[0];
- assign alert_cause_36_we = addr_hit[186] & reg_we & !reg_error;
+ assign alert_cause_36_we = addr_hit[195] & reg_we & !reg_error;
assign alert_cause_36_wd = reg_wdata[0];
- assign alert_cause_37_we = addr_hit[187] & reg_we & !reg_error;
+ assign alert_cause_37_we = addr_hit[196] & reg_we & !reg_error;
assign alert_cause_37_wd = reg_wdata[0];
- assign alert_cause_38_we = addr_hit[188] & reg_we & !reg_error;
+ assign alert_cause_38_we = addr_hit[197] & reg_we & !reg_error;
assign alert_cause_38_wd = reg_wdata[0];
- assign alert_cause_39_we = addr_hit[189] & reg_we & !reg_error;
+ assign alert_cause_39_we = addr_hit[198] & reg_we & !reg_error;
assign alert_cause_39_wd = reg_wdata[0];
- assign alert_cause_40_we = addr_hit[190] & reg_we & !reg_error;
+ assign alert_cause_40_we = addr_hit[199] & reg_we & !reg_error;
assign alert_cause_40_wd = reg_wdata[0];
- assign alert_cause_41_we = addr_hit[191] & reg_we & !reg_error;
+ assign alert_cause_41_we = addr_hit[200] & reg_we & !reg_error;
assign alert_cause_41_wd = reg_wdata[0];
- assign alert_cause_42_we = addr_hit[192] & reg_we & !reg_error;
+ assign alert_cause_42_we = addr_hit[201] & reg_we & !reg_error;
assign alert_cause_42_wd = reg_wdata[0];
- assign alert_cause_43_we = addr_hit[193] & reg_we & !reg_error;
+ assign alert_cause_43_we = addr_hit[202] & reg_we & !reg_error;
assign alert_cause_43_wd = reg_wdata[0];
- assign alert_cause_44_we = addr_hit[194] & reg_we & !reg_error;
+ assign alert_cause_44_we = addr_hit[203] & reg_we & !reg_error;
assign alert_cause_44_wd = reg_wdata[0];
- assign alert_cause_45_we = addr_hit[195] & reg_we & !reg_error;
+ assign alert_cause_45_we = addr_hit[204] & reg_we & !reg_error;
assign alert_cause_45_wd = reg_wdata[0];
- assign alert_cause_46_we = addr_hit[196] & reg_we & !reg_error;
+ assign alert_cause_46_we = addr_hit[205] & reg_we & !reg_error;
assign alert_cause_46_wd = reg_wdata[0];
- assign alert_cause_47_we = addr_hit[197] & reg_we & !reg_error;
+ assign alert_cause_47_we = addr_hit[206] & reg_we & !reg_error;
assign alert_cause_47_wd = reg_wdata[0];
- assign loc_alert_regwen_0_we = addr_hit[198] & reg_we & !reg_error;
+ assign alert_cause_48_we = addr_hit[207] & reg_we & !reg_error;
+ assign alert_cause_48_wd = reg_wdata[0];
+
+ assign alert_cause_49_we = addr_hit[208] & reg_we & !reg_error;
+ assign alert_cause_49_wd = reg_wdata[0];
+
+ assign alert_cause_50_we = addr_hit[209] & reg_we & !reg_error;
+ assign alert_cause_50_wd = reg_wdata[0];
+
+ assign loc_alert_regwen_0_we = addr_hit[210] & reg_we & !reg_error;
assign loc_alert_regwen_0_wd = reg_wdata[0];
- assign loc_alert_regwen_1_we = addr_hit[199] & reg_we & !reg_error;
+ assign loc_alert_regwen_1_we = addr_hit[211] & reg_we & !reg_error;
assign loc_alert_regwen_1_wd = reg_wdata[0];
- assign loc_alert_regwen_2_we = addr_hit[200] & reg_we & !reg_error;
+ assign loc_alert_regwen_2_we = addr_hit[212] & reg_we & !reg_error;
assign loc_alert_regwen_2_wd = reg_wdata[0];
- assign loc_alert_regwen_3_we = addr_hit[201] & reg_we & !reg_error;
+ assign loc_alert_regwen_3_we = addr_hit[213] & reg_we & !reg_error;
assign loc_alert_regwen_3_wd = reg_wdata[0];
- assign loc_alert_regwen_4_we = addr_hit[202] & reg_we & !reg_error;
+ assign loc_alert_regwen_4_we = addr_hit[214] & reg_we & !reg_error;
assign loc_alert_regwen_4_wd = reg_wdata[0];
- assign loc_alert_en_0_we = addr_hit[203] & reg_we & !reg_error;
+ assign loc_alert_en_0_we = addr_hit[215] & reg_we & !reg_error;
assign loc_alert_en_0_wd = reg_wdata[0];
- assign loc_alert_en_1_we = addr_hit[204] & reg_we & !reg_error;
+ assign loc_alert_en_1_we = addr_hit[216] & reg_we & !reg_error;
assign loc_alert_en_1_wd = reg_wdata[0];
- assign loc_alert_en_2_we = addr_hit[205] & reg_we & !reg_error;
+ assign loc_alert_en_2_we = addr_hit[217] & reg_we & !reg_error;
assign loc_alert_en_2_wd = reg_wdata[0];
- assign loc_alert_en_3_we = addr_hit[206] & reg_we & !reg_error;
+ assign loc_alert_en_3_we = addr_hit[218] & reg_we & !reg_error;
assign loc_alert_en_3_wd = reg_wdata[0];
- assign loc_alert_en_4_we = addr_hit[207] & reg_we & !reg_error;
+ assign loc_alert_en_4_we = addr_hit[219] & reg_we & !reg_error;
assign loc_alert_en_4_wd = reg_wdata[0];
- assign loc_alert_class_0_we = addr_hit[208] & reg_we & !reg_error;
+ assign loc_alert_class_0_we = addr_hit[220] & reg_we & !reg_error;
assign loc_alert_class_0_wd = reg_wdata[1:0];
- assign loc_alert_class_1_we = addr_hit[209] & reg_we & !reg_error;
+ assign loc_alert_class_1_we = addr_hit[221] & reg_we & !reg_error;
assign loc_alert_class_1_wd = reg_wdata[1:0];
- assign loc_alert_class_2_we = addr_hit[210] & reg_we & !reg_error;
+ assign loc_alert_class_2_we = addr_hit[222] & reg_we & !reg_error;
assign loc_alert_class_2_wd = reg_wdata[1:0];
- assign loc_alert_class_3_we = addr_hit[211] & reg_we & !reg_error;
+ assign loc_alert_class_3_we = addr_hit[223] & reg_we & !reg_error;
assign loc_alert_class_3_wd = reg_wdata[1:0];
- assign loc_alert_class_4_we = addr_hit[212] & reg_we & !reg_error;
+ assign loc_alert_class_4_we = addr_hit[224] & reg_we & !reg_error;
assign loc_alert_class_4_wd = reg_wdata[1:0];
- assign loc_alert_cause_0_we = addr_hit[213] & reg_we & !reg_error;
+ assign loc_alert_cause_0_we = addr_hit[225] & reg_we & !reg_error;
assign loc_alert_cause_0_wd = reg_wdata[0];
- assign loc_alert_cause_1_we = addr_hit[214] & reg_we & !reg_error;
+ assign loc_alert_cause_1_we = addr_hit[226] & reg_we & !reg_error;
assign loc_alert_cause_1_wd = reg_wdata[0];
- assign loc_alert_cause_2_we = addr_hit[215] & reg_we & !reg_error;
+ assign loc_alert_cause_2_we = addr_hit[227] & reg_we & !reg_error;
assign loc_alert_cause_2_wd = reg_wdata[0];
- assign loc_alert_cause_3_we = addr_hit[216] & reg_we & !reg_error;
+ assign loc_alert_cause_3_we = addr_hit[228] & reg_we & !reg_error;
assign loc_alert_cause_3_wd = reg_wdata[0];
- assign loc_alert_cause_4_we = addr_hit[217] & reg_we & !reg_error;
+ assign loc_alert_cause_4_we = addr_hit[229] & reg_we & !reg_error;
assign loc_alert_cause_4_wd = reg_wdata[0];
- assign classa_regwen_we = addr_hit[218] & reg_we & !reg_error;
+ assign classa_regwen_we = addr_hit[230] & reg_we & !reg_error;
assign classa_regwen_wd = reg_wdata[0];
- assign classa_ctrl_en_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_en_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_en_wd = reg_wdata[0];
- assign classa_ctrl_lock_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_lock_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_lock_wd = reg_wdata[1];
- assign classa_ctrl_en_e0_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_en_e0_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_en_e0_wd = reg_wdata[2];
- assign classa_ctrl_en_e1_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_en_e1_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_en_e1_wd = reg_wdata[3];
- assign classa_ctrl_en_e2_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_en_e2_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_en_e2_wd = reg_wdata[4];
- assign classa_ctrl_en_e3_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_en_e3_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_en_e3_wd = reg_wdata[5];
- assign classa_ctrl_map_e0_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_map_e0_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classa_ctrl_map_e1_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_map_e1_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classa_ctrl_map_e2_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_map_e2_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classa_ctrl_map_e3_we = addr_hit[219] & reg_we & !reg_error;
+ assign classa_ctrl_map_e3_we = addr_hit[231] & reg_we & !reg_error;
assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classa_clr_regwen_we = addr_hit[220] & reg_we & !reg_error;
+ assign classa_clr_regwen_we = addr_hit[232] & reg_we & !reg_error;
assign classa_clr_regwen_wd = reg_wdata[0];
- assign classa_clr_we = addr_hit[221] & reg_we & !reg_error;
+ assign classa_clr_we = addr_hit[233] & reg_we & !reg_error;
assign classa_clr_wd = reg_wdata[0];
- assign classa_accum_cnt_re = addr_hit[222] & reg_re & !reg_error;
+ assign classa_accum_cnt_re = addr_hit[234] & reg_re & !reg_error;
- assign classa_accum_thresh_we = addr_hit[223] & reg_we & !reg_error;
+ assign classa_accum_thresh_we = addr_hit[235] & reg_we & !reg_error;
assign classa_accum_thresh_wd = reg_wdata[15:0];
- assign classa_timeout_cyc_we = addr_hit[224] & reg_we & !reg_error;
+ assign classa_timeout_cyc_we = addr_hit[236] & reg_we & !reg_error;
assign classa_timeout_cyc_wd = reg_wdata[31:0];
- assign classa_phase0_cyc_we = addr_hit[225] & reg_we & !reg_error;
+ assign classa_phase0_cyc_we = addr_hit[237] & reg_we & !reg_error;
assign classa_phase0_cyc_wd = reg_wdata[31:0];
- assign classa_phase1_cyc_we = addr_hit[226] & reg_we & !reg_error;
+ assign classa_phase1_cyc_we = addr_hit[238] & reg_we & !reg_error;
assign classa_phase1_cyc_wd = reg_wdata[31:0];
- assign classa_phase2_cyc_we = addr_hit[227] & reg_we & !reg_error;
+ assign classa_phase2_cyc_we = addr_hit[239] & reg_we & !reg_error;
assign classa_phase2_cyc_wd = reg_wdata[31:0];
- assign classa_phase3_cyc_we = addr_hit[228] & reg_we & !reg_error;
+ assign classa_phase3_cyc_we = addr_hit[240] & reg_we & !reg_error;
assign classa_phase3_cyc_wd = reg_wdata[31:0];
- assign classa_esc_cnt_re = addr_hit[229] & reg_re & !reg_error;
+ assign classa_esc_cnt_re = addr_hit[241] & reg_re & !reg_error;
- assign classa_state_re = addr_hit[230] & reg_re & !reg_error;
+ assign classa_state_re = addr_hit[242] & reg_re & !reg_error;
- assign classb_regwen_we = addr_hit[231] & reg_we & !reg_error;
+ assign classb_regwen_we = addr_hit[243] & reg_we & !reg_error;
assign classb_regwen_wd = reg_wdata[0];
- assign classb_ctrl_en_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_en_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_en_wd = reg_wdata[0];
- assign classb_ctrl_lock_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_lock_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_lock_wd = reg_wdata[1];
- assign classb_ctrl_en_e0_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_en_e0_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_en_e0_wd = reg_wdata[2];
- assign classb_ctrl_en_e1_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_en_e1_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_en_e1_wd = reg_wdata[3];
- assign classb_ctrl_en_e2_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_en_e2_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_en_e2_wd = reg_wdata[4];
- assign classb_ctrl_en_e3_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_en_e3_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_en_e3_wd = reg_wdata[5];
- assign classb_ctrl_map_e0_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_map_e0_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classb_ctrl_map_e1_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_map_e1_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classb_ctrl_map_e2_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_map_e2_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classb_ctrl_map_e3_we = addr_hit[232] & reg_we & !reg_error;
+ assign classb_ctrl_map_e3_we = addr_hit[244] & reg_we & !reg_error;
assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classb_clr_regwen_we = addr_hit[233] & reg_we & !reg_error;
+ assign classb_clr_regwen_we = addr_hit[245] & reg_we & !reg_error;
assign classb_clr_regwen_wd = reg_wdata[0];
- assign classb_clr_we = addr_hit[234] & reg_we & !reg_error;
+ assign classb_clr_we = addr_hit[246] & reg_we & !reg_error;
assign classb_clr_wd = reg_wdata[0];
- assign classb_accum_cnt_re = addr_hit[235] & reg_re & !reg_error;
+ assign classb_accum_cnt_re = addr_hit[247] & reg_re & !reg_error;
- assign classb_accum_thresh_we = addr_hit[236] & reg_we & !reg_error;
+ assign classb_accum_thresh_we = addr_hit[248] & reg_we & !reg_error;
assign classb_accum_thresh_wd = reg_wdata[15:0];
- assign classb_timeout_cyc_we = addr_hit[237] & reg_we & !reg_error;
+ assign classb_timeout_cyc_we = addr_hit[249] & reg_we & !reg_error;
assign classb_timeout_cyc_wd = reg_wdata[31:0];
- assign classb_phase0_cyc_we = addr_hit[238] & reg_we & !reg_error;
+ assign classb_phase0_cyc_we = addr_hit[250] & reg_we & !reg_error;
assign classb_phase0_cyc_wd = reg_wdata[31:0];
- assign classb_phase1_cyc_we = addr_hit[239] & reg_we & !reg_error;
+ assign classb_phase1_cyc_we = addr_hit[251] & reg_we & !reg_error;
assign classb_phase1_cyc_wd = reg_wdata[31:0];
- assign classb_phase2_cyc_we = addr_hit[240] & reg_we & !reg_error;
+ assign classb_phase2_cyc_we = addr_hit[252] & reg_we & !reg_error;
assign classb_phase2_cyc_wd = reg_wdata[31:0];
- assign classb_phase3_cyc_we = addr_hit[241] & reg_we & !reg_error;
+ assign classb_phase3_cyc_we = addr_hit[253] & reg_we & !reg_error;
assign classb_phase3_cyc_wd = reg_wdata[31:0];
- assign classb_esc_cnt_re = addr_hit[242] & reg_re & !reg_error;
+ assign classb_esc_cnt_re = addr_hit[254] & reg_re & !reg_error;
- assign classb_state_re = addr_hit[243] & reg_re & !reg_error;
+ assign classb_state_re = addr_hit[255] & reg_re & !reg_error;
- assign classc_regwen_we = addr_hit[244] & reg_we & !reg_error;
+ assign classc_regwen_we = addr_hit[256] & reg_we & !reg_error;
assign classc_regwen_wd = reg_wdata[0];
- assign classc_ctrl_en_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_en_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_en_wd = reg_wdata[0];
- assign classc_ctrl_lock_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_lock_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_lock_wd = reg_wdata[1];
- assign classc_ctrl_en_e0_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_en_e0_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_en_e0_wd = reg_wdata[2];
- assign classc_ctrl_en_e1_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_en_e1_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_en_e1_wd = reg_wdata[3];
- assign classc_ctrl_en_e2_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_en_e2_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_en_e2_wd = reg_wdata[4];
- assign classc_ctrl_en_e3_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_en_e3_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_en_e3_wd = reg_wdata[5];
- assign classc_ctrl_map_e0_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_map_e0_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classc_ctrl_map_e1_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_map_e1_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classc_ctrl_map_e2_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_map_e2_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classc_ctrl_map_e3_we = addr_hit[245] & reg_we & !reg_error;
+ assign classc_ctrl_map_e3_we = addr_hit[257] & reg_we & !reg_error;
assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classc_clr_regwen_we = addr_hit[246] & reg_we & !reg_error;
+ assign classc_clr_regwen_we = addr_hit[258] & reg_we & !reg_error;
assign classc_clr_regwen_wd = reg_wdata[0];
- assign classc_clr_we = addr_hit[247] & reg_we & !reg_error;
+ assign classc_clr_we = addr_hit[259] & reg_we & !reg_error;
assign classc_clr_wd = reg_wdata[0];
- assign classc_accum_cnt_re = addr_hit[248] & reg_re & !reg_error;
+ assign classc_accum_cnt_re = addr_hit[260] & reg_re & !reg_error;
- assign classc_accum_thresh_we = addr_hit[249] & reg_we & !reg_error;
+ assign classc_accum_thresh_we = addr_hit[261] & reg_we & !reg_error;
assign classc_accum_thresh_wd = reg_wdata[15:0];
- assign classc_timeout_cyc_we = addr_hit[250] & reg_we & !reg_error;
+ assign classc_timeout_cyc_we = addr_hit[262] & reg_we & !reg_error;
assign classc_timeout_cyc_wd = reg_wdata[31:0];
- assign classc_phase0_cyc_we = addr_hit[251] & reg_we & !reg_error;
+ assign classc_phase0_cyc_we = addr_hit[263] & reg_we & !reg_error;
assign classc_phase0_cyc_wd = reg_wdata[31:0];
- assign classc_phase1_cyc_we = addr_hit[252] & reg_we & !reg_error;
+ assign classc_phase1_cyc_we = addr_hit[264] & reg_we & !reg_error;
assign classc_phase1_cyc_wd = reg_wdata[31:0];
- assign classc_phase2_cyc_we = addr_hit[253] & reg_we & !reg_error;
+ assign classc_phase2_cyc_we = addr_hit[265] & reg_we & !reg_error;
assign classc_phase2_cyc_wd = reg_wdata[31:0];
- assign classc_phase3_cyc_we = addr_hit[254] & reg_we & !reg_error;
+ assign classc_phase3_cyc_we = addr_hit[266] & reg_we & !reg_error;
assign classc_phase3_cyc_wd = reg_wdata[31:0];
- assign classc_esc_cnt_re = addr_hit[255] & reg_re & !reg_error;
+ assign classc_esc_cnt_re = addr_hit[267] & reg_re & !reg_error;
- assign classc_state_re = addr_hit[256] & reg_re & !reg_error;
+ assign classc_state_re = addr_hit[268] & reg_re & !reg_error;
- assign classd_regwen_we = addr_hit[257] & reg_we & !reg_error;
+ assign classd_regwen_we = addr_hit[269] & reg_we & !reg_error;
assign classd_regwen_wd = reg_wdata[0];
- assign classd_ctrl_en_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_en_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_en_wd = reg_wdata[0];
- assign classd_ctrl_lock_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_lock_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_lock_wd = reg_wdata[1];
- assign classd_ctrl_en_e0_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_en_e0_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_en_e0_wd = reg_wdata[2];
- assign classd_ctrl_en_e1_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_en_e1_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_en_e1_wd = reg_wdata[3];
- assign classd_ctrl_en_e2_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_en_e2_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_en_e2_wd = reg_wdata[4];
- assign classd_ctrl_en_e3_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_en_e3_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_en_e3_wd = reg_wdata[5];
- assign classd_ctrl_map_e0_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_map_e0_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classd_ctrl_map_e1_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_map_e1_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classd_ctrl_map_e2_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_map_e2_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classd_ctrl_map_e3_we = addr_hit[258] & reg_we & !reg_error;
+ assign classd_ctrl_map_e3_we = addr_hit[270] & reg_we & !reg_error;
assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classd_clr_regwen_we = addr_hit[259] & reg_we & !reg_error;
+ assign classd_clr_regwen_we = addr_hit[271] & reg_we & !reg_error;
assign classd_clr_regwen_wd = reg_wdata[0];
- assign classd_clr_we = addr_hit[260] & reg_we & !reg_error;
+ assign classd_clr_we = addr_hit[272] & reg_we & !reg_error;
assign classd_clr_wd = reg_wdata[0];
- assign classd_accum_cnt_re = addr_hit[261] & reg_re & !reg_error;
+ assign classd_accum_cnt_re = addr_hit[273] & reg_re & !reg_error;
- assign classd_accum_thresh_we = addr_hit[262] & reg_we & !reg_error;
+ assign classd_accum_thresh_we = addr_hit[274] & reg_we & !reg_error;
assign classd_accum_thresh_wd = reg_wdata[15:0];
- assign classd_timeout_cyc_we = addr_hit[263] & reg_we & !reg_error;
+ assign classd_timeout_cyc_we = addr_hit[275] & reg_we & !reg_error;
assign classd_timeout_cyc_wd = reg_wdata[31:0];
- assign classd_phase0_cyc_we = addr_hit[264] & reg_we & !reg_error;
+ assign classd_phase0_cyc_we = addr_hit[276] & reg_we & !reg_error;
assign classd_phase0_cyc_wd = reg_wdata[31:0];
- assign classd_phase1_cyc_we = addr_hit[265] & reg_we & !reg_error;
+ assign classd_phase1_cyc_we = addr_hit[277] & reg_we & !reg_error;
assign classd_phase1_cyc_wd = reg_wdata[31:0];
- assign classd_phase2_cyc_we = addr_hit[266] & reg_we & !reg_error;
+ assign classd_phase2_cyc_we = addr_hit[278] & reg_we & !reg_error;
assign classd_phase2_cyc_wd = reg_wdata[31:0];
- assign classd_phase3_cyc_we = addr_hit[267] & reg_we & !reg_error;
+ assign classd_phase3_cyc_we = addr_hit[279] & reg_we & !reg_error;
assign classd_phase3_cyc_wd = reg_wdata[31:0];
- assign classd_esc_cnt_re = addr_hit[268] & reg_re & !reg_error;
+ assign classd_esc_cnt_re = addr_hit[280] & reg_re & !reg_error;
- assign classd_state_re = addr_hit[269] & reg_re & !reg_error;
+ assign classd_state_re = addr_hit[281] & reg_re & !reg_error;
// Read data return
always_comb begin
@@ -11055,666 +11475,714 @@
end
addr_hit[54]: begin
- reg_rdata_next[0] = alert_en_0_qs;
+ reg_rdata_next[0] = alert_regwen_48_qs;
end
addr_hit[55]: begin
- reg_rdata_next[0] = alert_en_1_qs;
+ reg_rdata_next[0] = alert_regwen_49_qs;
end
addr_hit[56]: begin
- reg_rdata_next[0] = alert_en_2_qs;
+ reg_rdata_next[0] = alert_regwen_50_qs;
end
addr_hit[57]: begin
- reg_rdata_next[0] = alert_en_3_qs;
+ reg_rdata_next[0] = alert_en_0_qs;
end
addr_hit[58]: begin
- reg_rdata_next[0] = alert_en_4_qs;
+ reg_rdata_next[0] = alert_en_1_qs;
end
addr_hit[59]: begin
- reg_rdata_next[0] = alert_en_5_qs;
+ reg_rdata_next[0] = alert_en_2_qs;
end
addr_hit[60]: begin
- reg_rdata_next[0] = alert_en_6_qs;
+ reg_rdata_next[0] = alert_en_3_qs;
end
addr_hit[61]: begin
- reg_rdata_next[0] = alert_en_7_qs;
+ reg_rdata_next[0] = alert_en_4_qs;
end
addr_hit[62]: begin
- reg_rdata_next[0] = alert_en_8_qs;
+ reg_rdata_next[0] = alert_en_5_qs;
end
addr_hit[63]: begin
- reg_rdata_next[0] = alert_en_9_qs;
+ reg_rdata_next[0] = alert_en_6_qs;
end
addr_hit[64]: begin
- reg_rdata_next[0] = alert_en_10_qs;
+ reg_rdata_next[0] = alert_en_7_qs;
end
addr_hit[65]: begin
- reg_rdata_next[0] = alert_en_11_qs;
+ reg_rdata_next[0] = alert_en_8_qs;
end
addr_hit[66]: begin
- reg_rdata_next[0] = alert_en_12_qs;
+ reg_rdata_next[0] = alert_en_9_qs;
end
addr_hit[67]: begin
- reg_rdata_next[0] = alert_en_13_qs;
+ reg_rdata_next[0] = alert_en_10_qs;
end
addr_hit[68]: begin
- reg_rdata_next[0] = alert_en_14_qs;
+ reg_rdata_next[0] = alert_en_11_qs;
end
addr_hit[69]: begin
- reg_rdata_next[0] = alert_en_15_qs;
+ reg_rdata_next[0] = alert_en_12_qs;
end
addr_hit[70]: begin
- reg_rdata_next[0] = alert_en_16_qs;
+ reg_rdata_next[0] = alert_en_13_qs;
end
addr_hit[71]: begin
- reg_rdata_next[0] = alert_en_17_qs;
+ reg_rdata_next[0] = alert_en_14_qs;
end
addr_hit[72]: begin
- reg_rdata_next[0] = alert_en_18_qs;
+ reg_rdata_next[0] = alert_en_15_qs;
end
addr_hit[73]: begin
- reg_rdata_next[0] = alert_en_19_qs;
+ reg_rdata_next[0] = alert_en_16_qs;
end
addr_hit[74]: begin
- reg_rdata_next[0] = alert_en_20_qs;
+ reg_rdata_next[0] = alert_en_17_qs;
end
addr_hit[75]: begin
- reg_rdata_next[0] = alert_en_21_qs;
+ reg_rdata_next[0] = alert_en_18_qs;
end
addr_hit[76]: begin
- reg_rdata_next[0] = alert_en_22_qs;
+ reg_rdata_next[0] = alert_en_19_qs;
end
addr_hit[77]: begin
- reg_rdata_next[0] = alert_en_23_qs;
+ reg_rdata_next[0] = alert_en_20_qs;
end
addr_hit[78]: begin
- reg_rdata_next[0] = alert_en_24_qs;
+ reg_rdata_next[0] = alert_en_21_qs;
end
addr_hit[79]: begin
- reg_rdata_next[0] = alert_en_25_qs;
+ reg_rdata_next[0] = alert_en_22_qs;
end
addr_hit[80]: begin
- reg_rdata_next[0] = alert_en_26_qs;
+ reg_rdata_next[0] = alert_en_23_qs;
end
addr_hit[81]: begin
- reg_rdata_next[0] = alert_en_27_qs;
+ reg_rdata_next[0] = alert_en_24_qs;
end
addr_hit[82]: begin
- reg_rdata_next[0] = alert_en_28_qs;
+ reg_rdata_next[0] = alert_en_25_qs;
end
addr_hit[83]: begin
- reg_rdata_next[0] = alert_en_29_qs;
+ reg_rdata_next[0] = alert_en_26_qs;
end
addr_hit[84]: begin
- reg_rdata_next[0] = alert_en_30_qs;
+ reg_rdata_next[0] = alert_en_27_qs;
end
addr_hit[85]: begin
- reg_rdata_next[0] = alert_en_31_qs;
+ reg_rdata_next[0] = alert_en_28_qs;
end
addr_hit[86]: begin
- reg_rdata_next[0] = alert_en_32_qs;
+ reg_rdata_next[0] = alert_en_29_qs;
end
addr_hit[87]: begin
- reg_rdata_next[0] = alert_en_33_qs;
+ reg_rdata_next[0] = alert_en_30_qs;
end
addr_hit[88]: begin
- reg_rdata_next[0] = alert_en_34_qs;
+ reg_rdata_next[0] = alert_en_31_qs;
end
addr_hit[89]: begin
- reg_rdata_next[0] = alert_en_35_qs;
+ reg_rdata_next[0] = alert_en_32_qs;
end
addr_hit[90]: begin
- reg_rdata_next[0] = alert_en_36_qs;
+ reg_rdata_next[0] = alert_en_33_qs;
end
addr_hit[91]: begin
- reg_rdata_next[0] = alert_en_37_qs;
+ reg_rdata_next[0] = alert_en_34_qs;
end
addr_hit[92]: begin
- reg_rdata_next[0] = alert_en_38_qs;
+ reg_rdata_next[0] = alert_en_35_qs;
end
addr_hit[93]: begin
- reg_rdata_next[0] = alert_en_39_qs;
+ reg_rdata_next[0] = alert_en_36_qs;
end
addr_hit[94]: begin
- reg_rdata_next[0] = alert_en_40_qs;
+ reg_rdata_next[0] = alert_en_37_qs;
end
addr_hit[95]: begin
- reg_rdata_next[0] = alert_en_41_qs;
+ reg_rdata_next[0] = alert_en_38_qs;
end
addr_hit[96]: begin
- reg_rdata_next[0] = alert_en_42_qs;
+ reg_rdata_next[0] = alert_en_39_qs;
end
addr_hit[97]: begin
- reg_rdata_next[0] = alert_en_43_qs;
+ reg_rdata_next[0] = alert_en_40_qs;
end
addr_hit[98]: begin
- reg_rdata_next[0] = alert_en_44_qs;
+ reg_rdata_next[0] = alert_en_41_qs;
end
addr_hit[99]: begin
- reg_rdata_next[0] = alert_en_45_qs;
+ reg_rdata_next[0] = alert_en_42_qs;
end
addr_hit[100]: begin
- reg_rdata_next[0] = alert_en_46_qs;
+ reg_rdata_next[0] = alert_en_43_qs;
end
addr_hit[101]: begin
- reg_rdata_next[0] = alert_en_47_qs;
+ reg_rdata_next[0] = alert_en_44_qs;
end
addr_hit[102]: begin
- reg_rdata_next[1:0] = alert_class_0_qs;
+ reg_rdata_next[0] = alert_en_45_qs;
end
addr_hit[103]: begin
- reg_rdata_next[1:0] = alert_class_1_qs;
+ reg_rdata_next[0] = alert_en_46_qs;
end
addr_hit[104]: begin
- reg_rdata_next[1:0] = alert_class_2_qs;
+ reg_rdata_next[0] = alert_en_47_qs;
end
addr_hit[105]: begin
- reg_rdata_next[1:0] = alert_class_3_qs;
+ reg_rdata_next[0] = alert_en_48_qs;
end
addr_hit[106]: begin
- reg_rdata_next[1:0] = alert_class_4_qs;
+ reg_rdata_next[0] = alert_en_49_qs;
end
addr_hit[107]: begin
- reg_rdata_next[1:0] = alert_class_5_qs;
+ reg_rdata_next[0] = alert_en_50_qs;
end
addr_hit[108]: begin
- reg_rdata_next[1:0] = alert_class_6_qs;
+ reg_rdata_next[1:0] = alert_class_0_qs;
end
addr_hit[109]: begin
- reg_rdata_next[1:0] = alert_class_7_qs;
+ reg_rdata_next[1:0] = alert_class_1_qs;
end
addr_hit[110]: begin
- reg_rdata_next[1:0] = alert_class_8_qs;
+ reg_rdata_next[1:0] = alert_class_2_qs;
end
addr_hit[111]: begin
- reg_rdata_next[1:0] = alert_class_9_qs;
+ reg_rdata_next[1:0] = alert_class_3_qs;
end
addr_hit[112]: begin
- reg_rdata_next[1:0] = alert_class_10_qs;
+ reg_rdata_next[1:0] = alert_class_4_qs;
end
addr_hit[113]: begin
- reg_rdata_next[1:0] = alert_class_11_qs;
+ reg_rdata_next[1:0] = alert_class_5_qs;
end
addr_hit[114]: begin
- reg_rdata_next[1:0] = alert_class_12_qs;
+ reg_rdata_next[1:0] = alert_class_6_qs;
end
addr_hit[115]: begin
- reg_rdata_next[1:0] = alert_class_13_qs;
+ reg_rdata_next[1:0] = alert_class_7_qs;
end
addr_hit[116]: begin
- reg_rdata_next[1:0] = alert_class_14_qs;
+ reg_rdata_next[1:0] = alert_class_8_qs;
end
addr_hit[117]: begin
- reg_rdata_next[1:0] = alert_class_15_qs;
+ reg_rdata_next[1:0] = alert_class_9_qs;
end
addr_hit[118]: begin
- reg_rdata_next[1:0] = alert_class_16_qs;
+ reg_rdata_next[1:0] = alert_class_10_qs;
end
addr_hit[119]: begin
- reg_rdata_next[1:0] = alert_class_17_qs;
+ reg_rdata_next[1:0] = alert_class_11_qs;
end
addr_hit[120]: begin
- reg_rdata_next[1:0] = alert_class_18_qs;
+ reg_rdata_next[1:0] = alert_class_12_qs;
end
addr_hit[121]: begin
- reg_rdata_next[1:0] = alert_class_19_qs;
+ reg_rdata_next[1:0] = alert_class_13_qs;
end
addr_hit[122]: begin
- reg_rdata_next[1:0] = alert_class_20_qs;
+ reg_rdata_next[1:0] = alert_class_14_qs;
end
addr_hit[123]: begin
- reg_rdata_next[1:0] = alert_class_21_qs;
+ reg_rdata_next[1:0] = alert_class_15_qs;
end
addr_hit[124]: begin
- reg_rdata_next[1:0] = alert_class_22_qs;
+ reg_rdata_next[1:0] = alert_class_16_qs;
end
addr_hit[125]: begin
- reg_rdata_next[1:0] = alert_class_23_qs;
+ reg_rdata_next[1:0] = alert_class_17_qs;
end
addr_hit[126]: begin
- reg_rdata_next[1:0] = alert_class_24_qs;
+ reg_rdata_next[1:0] = alert_class_18_qs;
end
addr_hit[127]: begin
- reg_rdata_next[1:0] = alert_class_25_qs;
+ reg_rdata_next[1:0] = alert_class_19_qs;
end
addr_hit[128]: begin
- reg_rdata_next[1:0] = alert_class_26_qs;
+ reg_rdata_next[1:0] = alert_class_20_qs;
end
addr_hit[129]: begin
- reg_rdata_next[1:0] = alert_class_27_qs;
+ reg_rdata_next[1:0] = alert_class_21_qs;
end
addr_hit[130]: begin
- reg_rdata_next[1:0] = alert_class_28_qs;
+ reg_rdata_next[1:0] = alert_class_22_qs;
end
addr_hit[131]: begin
- reg_rdata_next[1:0] = alert_class_29_qs;
+ reg_rdata_next[1:0] = alert_class_23_qs;
end
addr_hit[132]: begin
- reg_rdata_next[1:0] = alert_class_30_qs;
+ reg_rdata_next[1:0] = alert_class_24_qs;
end
addr_hit[133]: begin
- reg_rdata_next[1:0] = alert_class_31_qs;
+ reg_rdata_next[1:0] = alert_class_25_qs;
end
addr_hit[134]: begin
- reg_rdata_next[1:0] = alert_class_32_qs;
+ reg_rdata_next[1:0] = alert_class_26_qs;
end
addr_hit[135]: begin
- reg_rdata_next[1:0] = alert_class_33_qs;
+ reg_rdata_next[1:0] = alert_class_27_qs;
end
addr_hit[136]: begin
- reg_rdata_next[1:0] = alert_class_34_qs;
+ reg_rdata_next[1:0] = alert_class_28_qs;
end
addr_hit[137]: begin
- reg_rdata_next[1:0] = alert_class_35_qs;
+ reg_rdata_next[1:0] = alert_class_29_qs;
end
addr_hit[138]: begin
- reg_rdata_next[1:0] = alert_class_36_qs;
+ reg_rdata_next[1:0] = alert_class_30_qs;
end
addr_hit[139]: begin
- reg_rdata_next[1:0] = alert_class_37_qs;
+ reg_rdata_next[1:0] = alert_class_31_qs;
end
addr_hit[140]: begin
- reg_rdata_next[1:0] = alert_class_38_qs;
+ reg_rdata_next[1:0] = alert_class_32_qs;
end
addr_hit[141]: begin
- reg_rdata_next[1:0] = alert_class_39_qs;
+ reg_rdata_next[1:0] = alert_class_33_qs;
end
addr_hit[142]: begin
- reg_rdata_next[1:0] = alert_class_40_qs;
+ reg_rdata_next[1:0] = alert_class_34_qs;
end
addr_hit[143]: begin
- reg_rdata_next[1:0] = alert_class_41_qs;
+ reg_rdata_next[1:0] = alert_class_35_qs;
end
addr_hit[144]: begin
- reg_rdata_next[1:0] = alert_class_42_qs;
+ reg_rdata_next[1:0] = alert_class_36_qs;
end
addr_hit[145]: begin
- reg_rdata_next[1:0] = alert_class_43_qs;
+ reg_rdata_next[1:0] = alert_class_37_qs;
end
addr_hit[146]: begin
- reg_rdata_next[1:0] = alert_class_44_qs;
+ reg_rdata_next[1:0] = alert_class_38_qs;
end
addr_hit[147]: begin
- reg_rdata_next[1:0] = alert_class_45_qs;
+ reg_rdata_next[1:0] = alert_class_39_qs;
end
addr_hit[148]: begin
- reg_rdata_next[1:0] = alert_class_46_qs;
+ reg_rdata_next[1:0] = alert_class_40_qs;
end
addr_hit[149]: begin
- reg_rdata_next[1:0] = alert_class_47_qs;
+ reg_rdata_next[1:0] = alert_class_41_qs;
end
addr_hit[150]: begin
- reg_rdata_next[0] = alert_cause_0_qs;
+ reg_rdata_next[1:0] = alert_class_42_qs;
end
addr_hit[151]: begin
- reg_rdata_next[0] = alert_cause_1_qs;
+ reg_rdata_next[1:0] = alert_class_43_qs;
end
addr_hit[152]: begin
- reg_rdata_next[0] = alert_cause_2_qs;
+ reg_rdata_next[1:0] = alert_class_44_qs;
end
addr_hit[153]: begin
- reg_rdata_next[0] = alert_cause_3_qs;
+ reg_rdata_next[1:0] = alert_class_45_qs;
end
addr_hit[154]: begin
- reg_rdata_next[0] = alert_cause_4_qs;
+ reg_rdata_next[1:0] = alert_class_46_qs;
end
addr_hit[155]: begin
- reg_rdata_next[0] = alert_cause_5_qs;
+ reg_rdata_next[1:0] = alert_class_47_qs;
end
addr_hit[156]: begin
- reg_rdata_next[0] = alert_cause_6_qs;
+ reg_rdata_next[1:0] = alert_class_48_qs;
end
addr_hit[157]: begin
- reg_rdata_next[0] = alert_cause_7_qs;
+ reg_rdata_next[1:0] = alert_class_49_qs;
end
addr_hit[158]: begin
- reg_rdata_next[0] = alert_cause_8_qs;
+ reg_rdata_next[1:0] = alert_class_50_qs;
end
addr_hit[159]: begin
- reg_rdata_next[0] = alert_cause_9_qs;
+ reg_rdata_next[0] = alert_cause_0_qs;
end
addr_hit[160]: begin
- reg_rdata_next[0] = alert_cause_10_qs;
+ reg_rdata_next[0] = alert_cause_1_qs;
end
addr_hit[161]: begin
- reg_rdata_next[0] = alert_cause_11_qs;
+ reg_rdata_next[0] = alert_cause_2_qs;
end
addr_hit[162]: begin
- reg_rdata_next[0] = alert_cause_12_qs;
+ reg_rdata_next[0] = alert_cause_3_qs;
end
addr_hit[163]: begin
- reg_rdata_next[0] = alert_cause_13_qs;
+ reg_rdata_next[0] = alert_cause_4_qs;
end
addr_hit[164]: begin
- reg_rdata_next[0] = alert_cause_14_qs;
+ reg_rdata_next[0] = alert_cause_5_qs;
end
addr_hit[165]: begin
- reg_rdata_next[0] = alert_cause_15_qs;
+ reg_rdata_next[0] = alert_cause_6_qs;
end
addr_hit[166]: begin
- reg_rdata_next[0] = alert_cause_16_qs;
+ reg_rdata_next[0] = alert_cause_7_qs;
end
addr_hit[167]: begin
- reg_rdata_next[0] = alert_cause_17_qs;
+ reg_rdata_next[0] = alert_cause_8_qs;
end
addr_hit[168]: begin
- reg_rdata_next[0] = alert_cause_18_qs;
+ reg_rdata_next[0] = alert_cause_9_qs;
end
addr_hit[169]: begin
- reg_rdata_next[0] = alert_cause_19_qs;
+ reg_rdata_next[0] = alert_cause_10_qs;
end
addr_hit[170]: begin
- reg_rdata_next[0] = alert_cause_20_qs;
+ reg_rdata_next[0] = alert_cause_11_qs;
end
addr_hit[171]: begin
- reg_rdata_next[0] = alert_cause_21_qs;
+ reg_rdata_next[0] = alert_cause_12_qs;
end
addr_hit[172]: begin
- reg_rdata_next[0] = alert_cause_22_qs;
+ reg_rdata_next[0] = alert_cause_13_qs;
end
addr_hit[173]: begin
- reg_rdata_next[0] = alert_cause_23_qs;
+ reg_rdata_next[0] = alert_cause_14_qs;
end
addr_hit[174]: begin
- reg_rdata_next[0] = alert_cause_24_qs;
+ reg_rdata_next[0] = alert_cause_15_qs;
end
addr_hit[175]: begin
- reg_rdata_next[0] = alert_cause_25_qs;
+ reg_rdata_next[0] = alert_cause_16_qs;
end
addr_hit[176]: begin
- reg_rdata_next[0] = alert_cause_26_qs;
+ reg_rdata_next[0] = alert_cause_17_qs;
end
addr_hit[177]: begin
- reg_rdata_next[0] = alert_cause_27_qs;
+ reg_rdata_next[0] = alert_cause_18_qs;
end
addr_hit[178]: begin
- reg_rdata_next[0] = alert_cause_28_qs;
+ reg_rdata_next[0] = alert_cause_19_qs;
end
addr_hit[179]: begin
- reg_rdata_next[0] = alert_cause_29_qs;
+ reg_rdata_next[0] = alert_cause_20_qs;
end
addr_hit[180]: begin
- reg_rdata_next[0] = alert_cause_30_qs;
+ reg_rdata_next[0] = alert_cause_21_qs;
end
addr_hit[181]: begin
- reg_rdata_next[0] = alert_cause_31_qs;
+ reg_rdata_next[0] = alert_cause_22_qs;
end
addr_hit[182]: begin
- reg_rdata_next[0] = alert_cause_32_qs;
+ reg_rdata_next[0] = alert_cause_23_qs;
end
addr_hit[183]: begin
- reg_rdata_next[0] = alert_cause_33_qs;
+ reg_rdata_next[0] = alert_cause_24_qs;
end
addr_hit[184]: begin
- reg_rdata_next[0] = alert_cause_34_qs;
+ reg_rdata_next[0] = alert_cause_25_qs;
end
addr_hit[185]: begin
- reg_rdata_next[0] = alert_cause_35_qs;
+ reg_rdata_next[0] = alert_cause_26_qs;
end
addr_hit[186]: begin
- reg_rdata_next[0] = alert_cause_36_qs;
+ reg_rdata_next[0] = alert_cause_27_qs;
end
addr_hit[187]: begin
- reg_rdata_next[0] = alert_cause_37_qs;
+ reg_rdata_next[0] = alert_cause_28_qs;
end
addr_hit[188]: begin
- reg_rdata_next[0] = alert_cause_38_qs;
+ reg_rdata_next[0] = alert_cause_29_qs;
end
addr_hit[189]: begin
- reg_rdata_next[0] = alert_cause_39_qs;
+ reg_rdata_next[0] = alert_cause_30_qs;
end
addr_hit[190]: begin
- reg_rdata_next[0] = alert_cause_40_qs;
+ reg_rdata_next[0] = alert_cause_31_qs;
end
addr_hit[191]: begin
- reg_rdata_next[0] = alert_cause_41_qs;
+ reg_rdata_next[0] = alert_cause_32_qs;
end
addr_hit[192]: begin
- reg_rdata_next[0] = alert_cause_42_qs;
+ reg_rdata_next[0] = alert_cause_33_qs;
end
addr_hit[193]: begin
- reg_rdata_next[0] = alert_cause_43_qs;
+ reg_rdata_next[0] = alert_cause_34_qs;
end
addr_hit[194]: begin
- reg_rdata_next[0] = alert_cause_44_qs;
+ reg_rdata_next[0] = alert_cause_35_qs;
end
addr_hit[195]: begin
- reg_rdata_next[0] = alert_cause_45_qs;
+ reg_rdata_next[0] = alert_cause_36_qs;
end
addr_hit[196]: begin
- reg_rdata_next[0] = alert_cause_46_qs;
+ reg_rdata_next[0] = alert_cause_37_qs;
end
addr_hit[197]: begin
- reg_rdata_next[0] = alert_cause_47_qs;
+ reg_rdata_next[0] = alert_cause_38_qs;
end
addr_hit[198]: begin
- reg_rdata_next[0] = loc_alert_regwen_0_qs;
+ reg_rdata_next[0] = alert_cause_39_qs;
end
addr_hit[199]: begin
- reg_rdata_next[0] = loc_alert_regwen_1_qs;
+ reg_rdata_next[0] = alert_cause_40_qs;
end
addr_hit[200]: begin
- reg_rdata_next[0] = loc_alert_regwen_2_qs;
+ reg_rdata_next[0] = alert_cause_41_qs;
end
addr_hit[201]: begin
- reg_rdata_next[0] = loc_alert_regwen_3_qs;
+ reg_rdata_next[0] = alert_cause_42_qs;
end
addr_hit[202]: begin
- reg_rdata_next[0] = loc_alert_regwen_4_qs;
+ reg_rdata_next[0] = alert_cause_43_qs;
end
addr_hit[203]: begin
- reg_rdata_next[0] = loc_alert_en_0_qs;
+ reg_rdata_next[0] = alert_cause_44_qs;
end
addr_hit[204]: begin
- reg_rdata_next[0] = loc_alert_en_1_qs;
+ reg_rdata_next[0] = alert_cause_45_qs;
end
addr_hit[205]: begin
- reg_rdata_next[0] = loc_alert_en_2_qs;
+ reg_rdata_next[0] = alert_cause_46_qs;
end
addr_hit[206]: begin
- reg_rdata_next[0] = loc_alert_en_3_qs;
+ reg_rdata_next[0] = alert_cause_47_qs;
end
addr_hit[207]: begin
- reg_rdata_next[0] = loc_alert_en_4_qs;
+ reg_rdata_next[0] = alert_cause_48_qs;
end
addr_hit[208]: begin
- reg_rdata_next[1:0] = loc_alert_class_0_qs;
+ reg_rdata_next[0] = alert_cause_49_qs;
end
addr_hit[209]: begin
- reg_rdata_next[1:0] = loc_alert_class_1_qs;
+ reg_rdata_next[0] = alert_cause_50_qs;
end
addr_hit[210]: begin
- reg_rdata_next[1:0] = loc_alert_class_2_qs;
+ reg_rdata_next[0] = loc_alert_regwen_0_qs;
end
addr_hit[211]: begin
- reg_rdata_next[1:0] = loc_alert_class_3_qs;
+ reg_rdata_next[0] = loc_alert_regwen_1_qs;
end
addr_hit[212]: begin
- reg_rdata_next[1:0] = loc_alert_class_4_qs;
+ reg_rdata_next[0] = loc_alert_regwen_2_qs;
end
addr_hit[213]: begin
- reg_rdata_next[0] = loc_alert_cause_0_qs;
+ reg_rdata_next[0] = loc_alert_regwen_3_qs;
end
addr_hit[214]: begin
- reg_rdata_next[0] = loc_alert_cause_1_qs;
+ reg_rdata_next[0] = loc_alert_regwen_4_qs;
end
addr_hit[215]: begin
- reg_rdata_next[0] = loc_alert_cause_2_qs;
+ reg_rdata_next[0] = loc_alert_en_0_qs;
end
addr_hit[216]: begin
- reg_rdata_next[0] = loc_alert_cause_3_qs;
+ reg_rdata_next[0] = loc_alert_en_1_qs;
end
addr_hit[217]: begin
- reg_rdata_next[0] = loc_alert_cause_4_qs;
+ reg_rdata_next[0] = loc_alert_en_2_qs;
end
addr_hit[218]: begin
- reg_rdata_next[0] = classa_regwen_qs;
+ reg_rdata_next[0] = loc_alert_en_3_qs;
end
addr_hit[219]: begin
+ reg_rdata_next[0] = loc_alert_en_4_qs;
+ end
+
+ addr_hit[220]: begin
+ reg_rdata_next[1:0] = loc_alert_class_0_qs;
+ end
+
+ addr_hit[221]: begin
+ reg_rdata_next[1:0] = loc_alert_class_1_qs;
+ end
+
+ addr_hit[222]: begin
+ reg_rdata_next[1:0] = loc_alert_class_2_qs;
+ end
+
+ addr_hit[223]: begin
+ reg_rdata_next[1:0] = loc_alert_class_3_qs;
+ end
+
+ addr_hit[224]: begin
+ reg_rdata_next[1:0] = loc_alert_class_4_qs;
+ end
+
+ addr_hit[225]: begin
+ reg_rdata_next[0] = loc_alert_cause_0_qs;
+ end
+
+ addr_hit[226]: begin
+ reg_rdata_next[0] = loc_alert_cause_1_qs;
+ end
+
+ addr_hit[227]: begin
+ reg_rdata_next[0] = loc_alert_cause_2_qs;
+ end
+
+ addr_hit[228]: begin
+ reg_rdata_next[0] = loc_alert_cause_3_qs;
+ end
+
+ addr_hit[229]: begin
+ reg_rdata_next[0] = loc_alert_cause_4_qs;
+ end
+
+ addr_hit[230]: begin
+ reg_rdata_next[0] = classa_regwen_qs;
+ end
+
+ addr_hit[231]: begin
reg_rdata_next[0] = classa_ctrl_en_qs;
reg_rdata_next[1] = classa_ctrl_lock_qs;
reg_rdata_next[2] = classa_ctrl_en_e0_qs;
@@ -11727,55 +12195,55 @@
reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
end
- addr_hit[220]: begin
+ addr_hit[232]: begin
reg_rdata_next[0] = classa_clr_regwen_qs;
end
- addr_hit[221]: begin
+ addr_hit[233]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[222]: begin
+ addr_hit[234]: begin
reg_rdata_next[15:0] = classa_accum_cnt_qs;
end
- addr_hit[223]: begin
+ addr_hit[235]: begin
reg_rdata_next[15:0] = classa_accum_thresh_qs;
end
- addr_hit[224]: begin
+ addr_hit[236]: begin
reg_rdata_next[31:0] = classa_timeout_cyc_qs;
end
- addr_hit[225]: begin
+ addr_hit[237]: begin
reg_rdata_next[31:0] = classa_phase0_cyc_qs;
end
- addr_hit[226]: begin
+ addr_hit[238]: begin
reg_rdata_next[31:0] = classa_phase1_cyc_qs;
end
- addr_hit[227]: begin
+ addr_hit[239]: begin
reg_rdata_next[31:0] = classa_phase2_cyc_qs;
end
- addr_hit[228]: begin
+ addr_hit[240]: begin
reg_rdata_next[31:0] = classa_phase3_cyc_qs;
end
- addr_hit[229]: begin
+ addr_hit[241]: begin
reg_rdata_next[31:0] = classa_esc_cnt_qs;
end
- addr_hit[230]: begin
+ addr_hit[242]: begin
reg_rdata_next[2:0] = classa_state_qs;
end
- addr_hit[231]: begin
+ addr_hit[243]: begin
reg_rdata_next[0] = classb_regwen_qs;
end
- addr_hit[232]: begin
+ addr_hit[244]: begin
reg_rdata_next[0] = classb_ctrl_en_qs;
reg_rdata_next[1] = classb_ctrl_lock_qs;
reg_rdata_next[2] = classb_ctrl_en_e0_qs;
@@ -11788,55 +12256,55 @@
reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
end
- addr_hit[233]: begin
+ addr_hit[245]: begin
reg_rdata_next[0] = classb_clr_regwen_qs;
end
- addr_hit[234]: begin
+ addr_hit[246]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[235]: begin
+ addr_hit[247]: begin
reg_rdata_next[15:0] = classb_accum_cnt_qs;
end
- addr_hit[236]: begin
+ addr_hit[248]: begin
reg_rdata_next[15:0] = classb_accum_thresh_qs;
end
- addr_hit[237]: begin
+ addr_hit[249]: begin
reg_rdata_next[31:0] = classb_timeout_cyc_qs;
end
- addr_hit[238]: begin
+ addr_hit[250]: begin
reg_rdata_next[31:0] = classb_phase0_cyc_qs;
end
- addr_hit[239]: begin
+ addr_hit[251]: begin
reg_rdata_next[31:0] = classb_phase1_cyc_qs;
end
- addr_hit[240]: begin
+ addr_hit[252]: begin
reg_rdata_next[31:0] = classb_phase2_cyc_qs;
end
- addr_hit[241]: begin
+ addr_hit[253]: begin
reg_rdata_next[31:0] = classb_phase3_cyc_qs;
end
- addr_hit[242]: begin
+ addr_hit[254]: begin
reg_rdata_next[31:0] = classb_esc_cnt_qs;
end
- addr_hit[243]: begin
+ addr_hit[255]: begin
reg_rdata_next[2:0] = classb_state_qs;
end
- addr_hit[244]: begin
+ addr_hit[256]: begin
reg_rdata_next[0] = classc_regwen_qs;
end
- addr_hit[245]: begin
+ addr_hit[257]: begin
reg_rdata_next[0] = classc_ctrl_en_qs;
reg_rdata_next[1] = classc_ctrl_lock_qs;
reg_rdata_next[2] = classc_ctrl_en_e0_qs;
@@ -11849,55 +12317,55 @@
reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
end
- addr_hit[246]: begin
+ addr_hit[258]: begin
reg_rdata_next[0] = classc_clr_regwen_qs;
end
- addr_hit[247]: begin
+ addr_hit[259]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[248]: begin
+ addr_hit[260]: begin
reg_rdata_next[15:0] = classc_accum_cnt_qs;
end
- addr_hit[249]: begin
+ addr_hit[261]: begin
reg_rdata_next[15:0] = classc_accum_thresh_qs;
end
- addr_hit[250]: begin
+ addr_hit[262]: begin
reg_rdata_next[31:0] = classc_timeout_cyc_qs;
end
- addr_hit[251]: begin
+ addr_hit[263]: begin
reg_rdata_next[31:0] = classc_phase0_cyc_qs;
end
- addr_hit[252]: begin
+ addr_hit[264]: begin
reg_rdata_next[31:0] = classc_phase1_cyc_qs;
end
- addr_hit[253]: begin
+ addr_hit[265]: begin
reg_rdata_next[31:0] = classc_phase2_cyc_qs;
end
- addr_hit[254]: begin
+ addr_hit[266]: begin
reg_rdata_next[31:0] = classc_phase3_cyc_qs;
end
- addr_hit[255]: begin
+ addr_hit[267]: begin
reg_rdata_next[31:0] = classc_esc_cnt_qs;
end
- addr_hit[256]: begin
+ addr_hit[268]: begin
reg_rdata_next[2:0] = classc_state_qs;
end
- addr_hit[257]: begin
+ addr_hit[269]: begin
reg_rdata_next[0] = classd_regwen_qs;
end
- addr_hit[258]: begin
+ addr_hit[270]: begin
reg_rdata_next[0] = classd_ctrl_en_qs;
reg_rdata_next[1] = classd_ctrl_lock_qs;
reg_rdata_next[2] = classd_ctrl_en_e0_qs;
@@ -11910,47 +12378,47 @@
reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
end
- addr_hit[259]: begin
+ addr_hit[271]: begin
reg_rdata_next[0] = classd_clr_regwen_qs;
end
- addr_hit[260]: begin
+ addr_hit[272]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[261]: begin
+ addr_hit[273]: begin
reg_rdata_next[15:0] = classd_accum_cnt_qs;
end
- addr_hit[262]: begin
+ addr_hit[274]: begin
reg_rdata_next[15:0] = classd_accum_thresh_qs;
end
- addr_hit[263]: begin
+ addr_hit[275]: begin
reg_rdata_next[31:0] = classd_timeout_cyc_qs;
end
- addr_hit[264]: begin
+ addr_hit[276]: begin
reg_rdata_next[31:0] = classd_phase0_cyc_qs;
end
- addr_hit[265]: begin
+ addr_hit[277]: begin
reg_rdata_next[31:0] = classd_phase1_cyc_qs;
end
- addr_hit[266]: begin
+ addr_hit[278]: begin
reg_rdata_next[31:0] = classd_phase2_cyc_qs;
end
- addr_hit[267]: begin
+ addr_hit[279]: begin
reg_rdata_next[31:0] = classd_phase3_cyc_qs;
end
- addr_hit[268]: begin
+ addr_hit[280]: begin
reg_rdata_next[31:0] = classd_esc_cnt_qs;
end
- addr_hit[269]: begin
+ addr_hit[281]: begin
reg_rdata_next[2:0] = classd_state_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index c46dc83..91270ae 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1331,7 +1331,9 @@
.rst_core_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
);
- i2c u_i2c0 (
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8])
+ ) u_i2c0 (
// Input
.cio_sda_i (cio_i2c0_sda_p2d),
@@ -1360,6 +1362,9 @@
.intr_acq_overflow_o (intr_i2c0_acq_overflow),
.intr_ack_stop_o (intr_i2c0_ack_stop),
.intr_host_timeout_o (intr_i2c0_host_timeout),
+ // [8]: fatal_fault
+ .alert_tx_o ( alert_tx[8:8] ),
+ .alert_rx_i ( alert_rx[8:8] ),
// Inter-module signals
.tl_i(i2c0_tl_req),
@@ -1370,7 +1375,9 @@
.rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
);
- i2c u_i2c1 (
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9])
+ ) u_i2c1 (
// Input
.cio_sda_i (cio_i2c1_sda_p2d),
@@ -1399,6 +1406,9 @@
.intr_acq_overflow_o (intr_i2c1_acq_overflow),
.intr_ack_stop_o (intr_i2c1_ack_stop),
.intr_host_timeout_o (intr_i2c1_host_timeout),
+ // [9]: fatal_fault
+ .alert_tx_o ( alert_tx[9:9] ),
+ .alert_rx_i ( alert_rx[9:9] ),
// Inter-module signals
.tl_i(i2c1_tl_req),
@@ -1409,7 +1419,9 @@
.rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
);
- i2c u_i2c2 (
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10])
+ ) u_i2c2 (
// Input
.cio_sda_i (cio_i2c2_sda_p2d),
@@ -1438,6 +1450,9 @@
.intr_acq_overflow_o (intr_i2c2_acq_overflow),
.intr_ack_stop_o (intr_i2c2_ack_stop),
.intr_host_timeout_o (intr_i2c2_host_timeout),
+ // [10]: fatal_fault
+ .alert_tx_o ( alert_tx[10:10] ),
+ .alert_rx_i ( alert_rx[10:10] ),
// Inter-module signals
.tl_i(i2c2_tl_req),
@@ -1449,7 +1464,7 @@
);
pattgen #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[11:11])
) u_pattgen (
// Output
@@ -1465,9 +1480,9 @@
// Interrupt
.intr_done_ch0_o (intr_pattgen_done_ch0),
.intr_done_ch1_o (intr_pattgen_done_ch1),
- // [8]: fatal_fault
- .alert_tx_o ( alert_tx[8:8] ),
- .alert_rx_i ( alert_rx[8:8] ),
+ // [11]: fatal_fault
+ .alert_tx_o ( alert_tx[11:11] ),
+ .alert_rx_i ( alert_rx[11:11] ),
// Inter-module signals
.tl_i(pattgen_tl_req),
@@ -1561,7 +1576,7 @@
);
otp_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:9]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[13:12]),
.MemInitFile(OtpCtrlMemInitFile),
.RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
.RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
@@ -1570,10 +1585,10 @@
// Interrupt
.intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
.intr_otp_error_o (intr_otp_ctrl_otp_error),
- // [9]: fatal_macro_error
- // [10]: fatal_check_error
- .alert_tx_o ( alert_tx[10:9] ),
- .alert_rx_i ( alert_rx[10:9] ),
+ // [12]: fatal_macro_error
+ // [13]: fatal_check_error
+ .alert_tx_o ( alert_tx[13:12] ),
+ .alert_rx_i ( alert_rx[13:12] ),
// Inter-module signals
.otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
@@ -1614,16 +1629,16 @@
);
lc_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[13:11]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:14]),
.RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
.RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
.RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
) u_lc_ctrl (
- // [11]: fatal_prog_error
- // [12]: fatal_state_error
- // [13]: fatal_bus_integ_error
- .alert_tx_o ( alert_tx[13:11] ),
- .alert_rx_i ( alert_rx[13:11] ),
+ // [14]: fatal_prog_error
+ // [15]: fatal_state_error
+ // [16]: fatal_bus_integ_error
+ .alert_tx_o ( alert_tx[16:14] ),
+ .alert_rx_i ( alert_rx[16:14] ),
// Inter-module signals
.jtag_i(pinmux_aon_lc_jtag_req),
@@ -1871,12 +1886,12 @@
);
pinmux #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:14]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[17:17]),
.TargetCfg(PinmuxAonTargetCfg)
) u_pinmux_aon (
- // [14]: fatal_fault
- .alert_tx_o ( alert_tx[14:14] ),
- .alert_rx_i ( alert_rx[14:14] ),
+ // [17]: fatal_fault
+ .alert_tx_o ( alert_tx[17:17] ),
+ .alert_rx_i ( alert_rx[17:17] ),
// Inter-module signals
.lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
@@ -1950,25 +1965,25 @@
);
sensor_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:15])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:18])
) u_sensor_ctrl_aon (
// Output
.cio_ast_debug_out_o (cio_sensor_ctrl_aon_ast_debug_out_d2p),
.cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
- // [15]: recov_as
- // [16]: recov_cg
- // [17]: recov_gd
- // [18]: recov_ts_hi
- // [19]: recov_ts_lo
- // [20]: recov_fla
- // [21]: recov_otp
- // [22]: recov_ot0
- // [23]: recov_ot1
- // [24]: recov_ot2
- // [25]: recov_ot3
- .alert_tx_o ( alert_tx[25:15] ),
- .alert_rx_i ( alert_rx[25:15] ),
+ // [18]: recov_as
+ // [19]: recov_cg
+ // [20]: recov_gd
+ // [21]: recov_ts_hi
+ // [22]: recov_ts_lo
+ // [23]: recov_fla
+ // [24]: recov_otp
+ // [25]: recov_ot0
+ // [26]: recov_ot1
+ // [27]: recov_ot2
+ // [28]: recov_ot3
+ .alert_tx_o ( alert_tx[28:18] ),
+ .alert_rx_i ( alert_rx[28:18] ),
// Inter-module signals
.ast_alert_i(sensor_ctrl_ast_alert_req_i),
@@ -1985,16 +2000,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:26]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:29]),
.RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
.RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm),
.InstrExec(SramCtrlRetAonInstrExec)
) u_sram_ctrl_ret_aon (
- // [26]: fatal_intg_error
- // [27]: fatal_parity_error
- .alert_tx_o ( alert_tx[27:26] ),
- .alert_rx_i ( alert_rx[27:26] ),
+ // [29]: fatal_intg_error
+ // [30]: fatal_parity_error
+ .alert_tx_o ( alert_tx[30:29] ),
+ .alert_rx_i ( alert_rx[30:29] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
@@ -2019,7 +2034,7 @@
);
flash_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:28]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:31]),
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
.RndCnstDataKey(RndCnstFlashCtrlDataKey),
.RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -2042,12 +2057,12 @@
.intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
.intr_op_done_o (intr_flash_ctrl_op_done),
.intr_err_o (intr_flash_ctrl_err),
- // [28]: recov_err
- // [29]: recov_mp_err
- // [30]: recov_ecc_err
- // [31]: fatal_intg_err
- .alert_tx_o ( alert_tx[31:28] ),
- .alert_rx_i ( alert_rx[31:28] ),
+ // [31]: recov_err
+ // [32]: recov_mp_err
+ // [33]: recov_ecc_err
+ // [34]: fatal_intg_err
+ .alert_tx_o ( alert_tx[34:31] ),
+ .alert_rx_i ( alert_rx[34:31] ),
// Inter-module signals
.flash_o(flash_ctrl_flash_req),
@@ -2093,7 +2108,7 @@
);
aes #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:35]),
.AES192Enable(1'b1),
.Masking(AesMasking),
.SBoxImpl(AesSBoxImpl),
@@ -2106,10 +2121,10 @@
.RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
.RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
) u_aes (
- // [32]: recov_ctrl_update_err
- // [33]: fatal_fault
- .alert_tx_o ( alert_tx[33:32] ),
- .alert_rx_i ( alert_rx[33:32] ),
+ // [35]: recov_ctrl_update_err
+ // [36]: fatal_fault
+ .alert_tx_o ( alert_tx[36:35] ),
+ .alert_rx_i ( alert_rx[36:35] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[0]),
@@ -2127,16 +2142,16 @@
);
hmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:37])
) u_hmac (
// Interrupt
.intr_hmac_done_o (intr_hmac_hmac_done),
.intr_fifo_empty_o (intr_hmac_fifo_empty),
.intr_hmac_err_o (intr_hmac_hmac_err),
- // [34]: fatal_fault
- .alert_tx_o ( alert_tx[34:34] ),
- .alert_rx_i ( alert_rx[34:34] ),
+ // [37]: fatal_fault
+ .alert_tx_o ( alert_tx[37:37] ),
+ .alert_rx_i ( alert_rx[37:37] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[1]),
@@ -2149,7 +2164,7 @@
);
kmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:35]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38]),
.EnMasking(KmacEnMasking),
.ReuseShare(KmacReuseShare)
) u_kmac (
@@ -2158,9 +2173,9 @@
.intr_kmac_done_o (intr_kmac_kmac_done),
.intr_fifo_empty_o (intr_kmac_fifo_empty),
.intr_kmac_err_o (intr_kmac_kmac_err),
- // [35]: fatal_fault
- .alert_tx_o ( alert_tx[35:35] ),
- .alert_rx_i ( alert_rx[35:35] ),
+ // [38]: fatal_fault
+ .alert_tx_o ( alert_tx[38:38] ),
+ .alert_rx_i ( alert_rx[38:38] ),
// Inter-module signals
.keymgr_key_i(keymgr_kmac_key),
@@ -2180,7 +2195,7 @@
);
keymgr #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:36]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]),
.RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
.RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
.RndCnstRandPerm(RndCnstKeymgrRandPerm),
@@ -2198,10 +2213,10 @@
// Interrupt
.intr_op_done_o (intr_keymgr_op_done),
- // [36]: fatal_fault_err
- // [37]: recov_operation_err
- .alert_tx_o ( alert_tx[37:36] ),
- .alert_rx_i ( alert_rx[37:36] ),
+ // [39]: fatal_fault_err
+ // [40]: recov_operation_err
+ .alert_tx_o ( alert_tx[40:39] ),
+ .alert_rx_i ( alert_rx[40:39] ),
// Inter-module signals
.edn_o(edn0_edn_req[0]),
@@ -2228,7 +2243,7 @@
);
csrng #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41]),
.SBoxImpl(CsrngSBoxImpl)
) u_csrng (
@@ -2237,9 +2252,9 @@
.intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
.intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
.intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
- // [38]: fatal_alert
- .alert_tx_o ( alert_tx[38:38] ),
- .alert_rx_i ( alert_rx[38:38] ),
+ // [41]: fatal_alert
+ .alert_tx_o ( alert_tx[41:41] ),
+ .alert_rx_i ( alert_rx[41:41] ),
// Inter-module signals
.csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2259,7 +2274,7 @@
);
entropy_src #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
.Stub(EntropySrcStub)
) u_entropy_src (
@@ -2268,10 +2283,10 @@
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
.intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
.intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [39]: recov_alert
- // [40]: fatal_alert
- .alert_tx_o ( alert_tx[40:39] ),
- .alert_rx_i ( alert_rx[40:39] ),
+ // [42]: recov_alert
+ // [43]: fatal_alert
+ .alert_tx_o ( alert_tx[43:42] ),
+ .alert_rx_i ( alert_rx[43:42] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2294,15 +2309,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44])
) u_edn0 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
- // [41]: fatal_alert
- .alert_tx_o ( alert_tx[41:41] ),
- .alert_rx_i ( alert_rx[41:41] ),
+ // [44]: fatal_alert
+ .alert_tx_o ( alert_tx[44:44] ),
+ .alert_rx_i ( alert_rx[44:44] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2318,15 +2333,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:42])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:45])
) u_edn1 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
- // [42]: fatal_alert
- .alert_tx_o ( alert_tx[42:42] ),
- .alert_rx_i ( alert_rx[42:42] ),
+ // [45]: fatal_alert
+ .alert_tx_o ( alert_tx[45:45] ),
+ .alert_rx_i ( alert_rx[45:45] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2342,16 +2357,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46]),
.RndCnstSramKey(RndCnstSramCtrlMainSramKey),
.RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm),
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [43]: fatal_intg_error
- // [44]: fatal_parity_error
- .alert_tx_o ( alert_tx[44:43] ),
- .alert_rx_i ( alert_rx[44:43] ),
+ // [46]: fatal_intg_error
+ // [47]: fatal_parity_error
+ .alert_tx_o ( alert_tx[47:46] ),
+ .alert_rx_i ( alert_rx[47:46] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2376,7 +2391,7 @@
);
otbn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48]),
.Stub(OtbnStub),
.RegFile(OtbnRegFile),
.RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
@@ -2385,10 +2400,10 @@
// Interrupt
.intr_done_o (intr_otbn_done),
- // [45]: fatal
- // [46]: recov
- .alert_tx_o ( alert_tx[46:45] ),
- .alert_rx_i ( alert_rx[46:45] ),
+ // [48]: fatal
+ // [49]: recov
+ .alert_tx_o ( alert_tx[49:48] ),
+ .alert_rx_i ( alert_rx[49:48] ),
// Inter-module signals
.edn_rnd_o(edn1_edn_req[0]),
@@ -2408,14 +2423,14 @@
);
rom_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:47]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:50]),
.BootRomInitFile(RomCtrlBootRomInitFile),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey)
) u_rom_ctrl (
- // [47]: fatal
- .alert_tx_o ( alert_tx[47:47] ),
- .alert_rx_i ( alert_rx[47:47] ),
+ // [50]: fatal
+ .alert_tx_o ( alert_tx[50:50] ),
+ .alert_rx_i ( alert_rx[50:50] ),
// Inter-module signals
.rom_cfg_i(ast_rom_cfg),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 32d3950..617426b 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -202,7 +202,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[48] = {
+ top_earlgrey_alert_for_peripheral[51] = {
[kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0,
[kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1,
[kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2,
@@ -211,6 +211,9 @@
[kTopEarlgreyAlertIdSpiDeviceFatalFault] = kTopEarlgreyAlertPeripheralSpiDevice,
[kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,
[kTopEarlgreyAlertIdSpiHost1FatalFault] = kTopEarlgreyAlertPeripheralSpiHost1,
+ [kTopEarlgreyAlertIdI2c0FatalFault] = kTopEarlgreyAlertPeripheralI2c0,
+ [kTopEarlgreyAlertIdI2c1FatalFault] = kTopEarlgreyAlertPeripheralI2c1,
+ [kTopEarlgreyAlertIdI2c2FatalFault] = kTopEarlgreyAlertPeripheralI2c2,
[kTopEarlgreyAlertIdPattgenFatalFault] = kTopEarlgreyAlertPeripheralPattgen,
[kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
[kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index eb95b77..b455a3d 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1096,25 +1096,28 @@
kTopEarlgreyAlertPeripheralSpiDevice = 5, /**< spi_device */
kTopEarlgreyAlertPeripheralSpiHost0 = 6, /**< spi_host0 */
kTopEarlgreyAlertPeripheralSpiHost1 = 7, /**< spi_host1 */
- kTopEarlgreyAlertPeripheralPattgen = 8, /**< pattgen */
- kTopEarlgreyAlertPeripheralOtpCtrl = 9, /**< otp_ctrl */
- kTopEarlgreyAlertPeripheralLcCtrl = 10, /**< lc_ctrl */
- kTopEarlgreyAlertPeripheralPinmuxAon = 11, /**< pinmux_aon */
- kTopEarlgreyAlertPeripheralSensorCtrlAon = 12, /**< sensor_ctrl_aon */
- kTopEarlgreyAlertPeripheralSramCtrlRetAon = 13, /**< sram_ctrl_ret_aon */
- kTopEarlgreyAlertPeripheralFlashCtrl = 14, /**< flash_ctrl */
- kTopEarlgreyAlertPeripheralAes = 15, /**< aes */
- kTopEarlgreyAlertPeripheralHmac = 16, /**< hmac */
- kTopEarlgreyAlertPeripheralKmac = 17, /**< kmac */
- kTopEarlgreyAlertPeripheralKeymgr = 18, /**< keymgr */
- kTopEarlgreyAlertPeripheralCsrng = 19, /**< csrng */
- kTopEarlgreyAlertPeripheralEntropySrc = 20, /**< entropy_src */
- kTopEarlgreyAlertPeripheralEdn0 = 21, /**< edn0 */
- kTopEarlgreyAlertPeripheralEdn1 = 22, /**< edn1 */
- kTopEarlgreyAlertPeripheralSramCtrlMain = 23, /**< sram_ctrl_main */
- kTopEarlgreyAlertPeripheralOtbn = 24, /**< otbn */
- kTopEarlgreyAlertPeripheralRomCtrl = 25, /**< rom_ctrl */
- kTopEarlgreyAlertPeripheralLast = 25, /**< \internal Final Alert peripheral */
+ kTopEarlgreyAlertPeripheralI2c0 = 8, /**< i2c0 */
+ kTopEarlgreyAlertPeripheralI2c1 = 9, /**< i2c1 */
+ kTopEarlgreyAlertPeripheralI2c2 = 10, /**< i2c2 */
+ kTopEarlgreyAlertPeripheralPattgen = 11, /**< pattgen */
+ kTopEarlgreyAlertPeripheralOtpCtrl = 12, /**< otp_ctrl */
+ kTopEarlgreyAlertPeripheralLcCtrl = 13, /**< lc_ctrl */
+ kTopEarlgreyAlertPeripheralPinmuxAon = 14, /**< pinmux_aon */
+ kTopEarlgreyAlertPeripheralSensorCtrlAon = 15, /**< sensor_ctrl_aon */
+ kTopEarlgreyAlertPeripheralSramCtrlRetAon = 16, /**< sram_ctrl_ret_aon */
+ kTopEarlgreyAlertPeripheralFlashCtrl = 17, /**< flash_ctrl */
+ kTopEarlgreyAlertPeripheralAes = 18, /**< aes */
+ kTopEarlgreyAlertPeripheralHmac = 19, /**< hmac */
+ kTopEarlgreyAlertPeripheralKmac = 20, /**< kmac */
+ kTopEarlgreyAlertPeripheralKeymgr = 21, /**< keymgr */
+ kTopEarlgreyAlertPeripheralCsrng = 22, /**< csrng */
+ kTopEarlgreyAlertPeripheralEntropySrc = 23, /**< entropy_src */
+ kTopEarlgreyAlertPeripheralEdn0 = 24, /**< edn0 */
+ kTopEarlgreyAlertPeripheralEdn1 = 25, /**< edn1 */
+ kTopEarlgreyAlertPeripheralSramCtrlMain = 26, /**< sram_ctrl_main */
+ kTopEarlgreyAlertPeripheralOtbn = 27, /**< otbn */
+ kTopEarlgreyAlertPeripheralRomCtrl = 28, /**< rom_ctrl */
+ kTopEarlgreyAlertPeripheralLast = 28, /**< \internal Final Alert peripheral */
} top_earlgrey_alert_peripheral_t;
/**
@@ -1132,47 +1135,50 @@
kTopEarlgreyAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
kTopEarlgreyAlertIdSpiHost0FatalFault = 6, /**< spi_host0_fatal_fault */
kTopEarlgreyAlertIdSpiHost1FatalFault = 7, /**< spi_host1_fatal_fault */
- kTopEarlgreyAlertIdPattgenFatalFault = 8, /**< pattgen_fatal_fault */
- kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 9, /**< otp_ctrl_fatal_macro_error */
- kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 10, /**< otp_ctrl_fatal_check_error */
- kTopEarlgreyAlertIdLcCtrlFatalProgError = 11, /**< lc_ctrl_fatal_prog_error */
- kTopEarlgreyAlertIdLcCtrlFatalStateError = 12, /**< lc_ctrl_fatal_state_error */
- kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 13, /**< lc_ctrl_fatal_bus_integ_error */
- kTopEarlgreyAlertIdPinmuxAonFatalFault = 14, /**< pinmux_aon_fatal_fault */
- kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 15, /**< sensor_ctrl_aon_recov_as */
- kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 16, /**< sensor_ctrl_aon_recov_cg */
- kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 17, /**< sensor_ctrl_aon_recov_gd */
- kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 18, /**< sensor_ctrl_aon_recov_ts_hi */
- kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 19, /**< sensor_ctrl_aon_recov_ts_lo */
- kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 20, /**< sensor_ctrl_aon_recov_fla */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 21, /**< sensor_ctrl_aon_recov_otp */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 22, /**< sensor_ctrl_aon_recov_ot0 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 23, /**< sensor_ctrl_aon_recov_ot1 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 24, /**< sensor_ctrl_aon_recov_ot2 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 25, /**< sensor_ctrl_aon_recov_ot3 */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 26, /**< sram_ctrl_ret_aon_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 27, /**< sram_ctrl_ret_aon_fatal_parity_error */
- kTopEarlgreyAlertIdFlashCtrlRecovErr = 28, /**< flash_ctrl_recov_err */
- kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 29, /**< flash_ctrl_recov_mp_err */
- kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 30, /**< flash_ctrl_recov_ecc_err */
- kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 31, /**< flash_ctrl_fatal_intg_err */
- kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 32, /**< aes_recov_ctrl_update_err */
- kTopEarlgreyAlertIdAesFatalFault = 33, /**< aes_fatal_fault */
- kTopEarlgreyAlertIdHmacFatalFault = 34, /**< hmac_fatal_fault */
- kTopEarlgreyAlertIdKmacFatalFault = 35, /**< kmac_fatal_fault */
- kTopEarlgreyAlertIdKeymgrFatalFaultErr = 36, /**< keymgr_fatal_fault_err */
- kTopEarlgreyAlertIdKeymgrRecovOperationErr = 37, /**< keymgr_recov_operation_err */
- kTopEarlgreyAlertIdCsrngFatalAlert = 38, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdEntropySrcRecovAlert = 39, /**< entropy_src_recov_alert */
- kTopEarlgreyAlertIdEntropySrcFatalAlert = 40, /**< entropy_src_fatal_alert */
- kTopEarlgreyAlertIdEdn0FatalAlert = 41, /**< edn0_fatal_alert */
- kTopEarlgreyAlertIdEdn1FatalAlert = 42, /**< edn1_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 43, /**< sram_ctrl_main_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 44, /**< sram_ctrl_main_fatal_parity_error */
- kTopEarlgreyAlertIdOtbnFatal = 45, /**< otbn_fatal */
- kTopEarlgreyAlertIdOtbnRecov = 46, /**< otbn_recov */
- kTopEarlgreyAlertIdRomCtrlFatal = 47, /**< rom_ctrl_fatal */
- kTopEarlgreyAlertIdLast = 47, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdI2c0FatalFault = 8, /**< i2c0_fatal_fault */
+ kTopEarlgreyAlertIdI2c1FatalFault = 9, /**< i2c1_fatal_fault */
+ kTopEarlgreyAlertIdI2c2FatalFault = 10, /**< i2c2_fatal_fault */
+ kTopEarlgreyAlertIdPattgenFatalFault = 11, /**< pattgen_fatal_fault */
+ kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 12, /**< otp_ctrl_fatal_macro_error */
+ kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 13, /**< otp_ctrl_fatal_check_error */
+ kTopEarlgreyAlertIdLcCtrlFatalProgError = 14, /**< lc_ctrl_fatal_prog_error */
+ kTopEarlgreyAlertIdLcCtrlFatalStateError = 15, /**< lc_ctrl_fatal_state_error */
+ kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 16, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopEarlgreyAlertIdPinmuxAonFatalFault = 17, /**< pinmux_aon_fatal_fault */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 18, /**< sensor_ctrl_aon_recov_as */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 19, /**< sensor_ctrl_aon_recov_cg */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 20, /**< sensor_ctrl_aon_recov_gd */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 21, /**< sensor_ctrl_aon_recov_ts_hi */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 22, /**< sensor_ctrl_aon_recov_ts_lo */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 23, /**< sensor_ctrl_aon_recov_fla */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 24, /**< sensor_ctrl_aon_recov_otp */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 25, /**< sensor_ctrl_aon_recov_ot0 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 26, /**< sensor_ctrl_aon_recov_ot1 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 27, /**< sensor_ctrl_aon_recov_ot2 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 28, /**< sensor_ctrl_aon_recov_ot3 */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 29, /**< sram_ctrl_ret_aon_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 30, /**< sram_ctrl_ret_aon_fatal_parity_error */
+ kTopEarlgreyAlertIdFlashCtrlRecovErr = 31, /**< flash_ctrl_recov_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 32, /**< flash_ctrl_recov_mp_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 33, /**< flash_ctrl_recov_ecc_err */
+ kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 34, /**< flash_ctrl_fatal_intg_err */
+ kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 35, /**< aes_recov_ctrl_update_err */
+ kTopEarlgreyAlertIdAesFatalFault = 36, /**< aes_fatal_fault */
+ kTopEarlgreyAlertIdHmacFatalFault = 37, /**< hmac_fatal_fault */
+ kTopEarlgreyAlertIdKmacFatalFault = 38, /**< kmac_fatal_fault */
+ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 39, /**< keymgr_fatal_fault_err */
+ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 40, /**< keymgr_recov_operation_err */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 41, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 42, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 43, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdEdn0FatalAlert = 44, /**< edn0_fatal_alert */
+ kTopEarlgreyAlertIdEdn1FatalAlert = 45, /**< edn1_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 46, /**< sram_ctrl_main_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 47, /**< sram_ctrl_main_fatal_parity_error */
+ kTopEarlgreyAlertIdOtbnFatal = 48, /**< otbn_fatal */
+ kTopEarlgreyAlertIdOtbnRecov = 49, /**< otbn_recov */
+ kTopEarlgreyAlertIdRomCtrlFatal = 50, /**< rom_ctrl_fatal */
+ kTopEarlgreyAlertIdLast = 50, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1182,7 +1188,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[48];
+ top_earlgrey_alert_for_peripheral[51];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
