| commit | ced4526ea04948e02fc8b970d375d99a6ed5d97f | [log] [tgz] |
|---|---|---|
| author | Pirmin Vogel <vogelpi@lowrisc.org> | Wed Sep 16 17:07:17 2020 +0200 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Tue Sep 22 08:18:10 2020 +0200 |
| tree | cb9b81820e217a2fa270b7d8ed99f41a25de63e4 | |
| parent | c32adb3be718812853c68cf5714eb7df0137b82c [diff] |
[top] Provide top/target-specific parameters for AES This commit provides top/target-specific parameters for the AES unit. The selection of the S-Box implementation and Masking hast a high impact on FPGA resource utilization/ASIC area, the trigger delay should only be used when performing SCA analysis. This is just a first step. Ultimately, some of these parameters will be driven through fusesoc, which will allow us to consolidate some of the top levels. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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