[top] Provide top/target-specific parameters for AES

This commit provides top/target-specific parameters for the AES unit.
The selection of the S-Box implementation and Masking hast a high
impact on FPGA resource utilization/ASIC area, the trigger delay
should only be used when performing SCA analysis.

This is just a first step. Ultimately, some of these parameters will
be driven through fusesoc, which will allow us to consolidate some
of the top levels.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

hw/top_earlgrey/rtl/top_earlgrey_artys7.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
index 8352fc3..f93e800 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -165,6 +165,9 @@
   //////////////////////
 
   top_earlgrey #(
+    .AesMasking(1'b0),
+    .AesSBoxImpl(aes_pkg::SBoxImplLut),
+    .SecAesStartTriggerDelay(0),
     .IbexPipeLine(1),
     .BootRomInitFile(BootRomInitFile)
   ) top_earlgrey (

hw/top_earlgrey/rtl/top_earlgrey_asic.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index 7afe21b..083cba5 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -241,7 +241,11 @@
   // Top-level design //
   //////////////////////
 
-  top_earlgrey top_earlgrey (
+  top_earlgrey #(
+    .AesMasking(1'b0),
+    .AesSBoxImpl(aes_pkg::SBoxImplCanright),
+    .SecAesStartTriggerDelay(0)
+  ) top_earlgrey (
     .rst_ni          ( rst_n         ),
     // ast connections
     .clk_main_i      ( ast_base_clks.clk_sys ),

hw/top_earlgrey/rtl/top_earlgrey_cw305.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
index 2167fea..d5a1ed6 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
@@ -227,6 +227,9 @@
   // for verilator purposes, make these two the same.
   assign ast_base_rst.aon_pok      = rst_n;
   top_earlgrey #(
+    .AesMasking(1'b0),
+    .AesSBoxImpl(aes_pkg::SBoxImplLut),
+    .SecAesStartTriggerDelay(40),
     .IbexPipeLine(1),
     .BootRomInitFile(BootRomInitFile)
   ) top_earlgrey (

hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index a881aa7..6000740 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -223,6 +223,9 @@
   // for verilator purposes, make these two the same.
   assign ast_base_rst.aon_pok      = rst_n;
   top_earlgrey #(
+    .AesMasking(1'b0),
+    .AesSBoxImpl(aes_pkg::SBoxImplLut),
+    .SecAesStartTriggerDelay(0),
     .IbexPipeLine(1),
     .BootRomInitFile(BootRomInitFile)
   ) top_earlgrey (