)]}'
{
  "commit": "ced4526ea04948e02fc8b970d375d99a6ed5d97f",
  "tree": "cb9b81820e217a2fa270b7d8ed99f41a25de63e4",
  "parents": [
    "c32adb3be718812853c68cf5714eb7df0137b82c"
  ],
  "author": {
    "name": "Pirmin Vogel",
    "email": "vogelpi@lowrisc.org",
    "time": "Wed Sep 16 17:07:17 2020 +0200"
  },
  "committer": {
    "name": "Pirmin Vogel",
    "email": "vogelpi@lowrisc.org",
    "time": "Tue Sep 22 08:18:10 2020 +0200"
  },
  "message": "[top] Provide top/target-specific parameters for AES\n\nThis commit provides top/target-specific parameters for the AES unit.\nThe selection of the S-Box implementation and Masking hast a high\nimpact on FPGA resource utilization/ASIC area, the trigger delay\nshould only be used when performing SCA analysis.\n\nThis is just a first step. Ultimately, some of these parameters will\nbe driven through fusesoc, which will allow us to consolidate some\nof the top levels.\n\nSigned-off-by: Pirmin Vogel \u003cvogelpi@lowrisc.org\u003e\n",
  "tree_diff": [
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      "new_path": "hw/top_earlgrey/rtl/top_earlgrey_artys7.sv"
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      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/rtl/top_earlgrey_asic.sv"
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      "new_mode": 33188,
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    },
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      "new_path": "hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv"
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}