hw/top_earlgrey/dv/chip_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: chip

  // Top level dut name (sv module).
  dut: top_earlgrey

  // Top level testbench name (sv module).
  tb: tb

  // Default simulator used to sign off.
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:chip_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/top_earlgrey/data/chip_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/top_earlgrey/data/top_earlgrey.hjson"

  // Add additional tops for simulation.
  sim_tops: ["-top xbar_main_bind",
             "-top xbar_peri_bind"]

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/data/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/data/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/data/tests/tl_access_tests.hjson"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 1

  // Default UVM test and seq class name.
  uvm_test: chip_base_test
  uvm_test_seq: chip_base_vseq
  sw_build_device: sim_dv

  // Add default build_opts.
  build_opts: [// Use generic implementations of prim modules.
               "+define+PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric"]

  // Add default run opts.
  run_opts: [// TODO: temp fix for C based tests.
             "+disable_assert_final_checks"]

  // Add build modes.
  build_modes: [
    {
      name: en_ibex_tracer
      build_opts: ["+define+RVFI=1"]
    }
  ]

  // Add run modes.
  run_modes: [
    {
      name: stub_cpu
      run_opts: ["+stub_cpu=1"]
    }

    {
      // Append stub cpu mode to mem_tests_mode
      name: mem_tests_mode
      en_run_modes: ["stub_cpu"]
    }
  ]

  // List of test specifications.
  tests: [
    {
      name: chip_sanity
      uvm_test_seq: chip_sw_test_base_vseq
      sw_name: hello_world
      sw_dir: examples/hello_world
    }
    {
      name: chip_flash_test
      uvm_test_seq: chip_sw_test_base_vseq
      sw_name: flash_test
      sw_dir: tests/flash_ctrl
      run_opts: ["+sw_test_timeout_ns=15000000"]
    }
    {
      name: chip_sha256_test
      uvm_test_seq: chip_sw_test_base_vseq
      sw_name: sha256_test
      sw_dir: tests/hmac
      run_opts: ["+sw_test_timeout_ns=4000000"]
    }
    {
      name: chip_rv_timer_test
      uvm_test_seq: chip_sw_test_base_vseq
      sw_name: rv_timer_test
      sw_dir: tests/rv_timer
      run_opts: ["+sw_test_timeout_ns=40000000"]
    }
    {
      name: coremark
      uvm_test_seq: chip_sw_test_base_vseq
      sw_name: coremark
      sw_dir: benchmarks/coremark
      run_opts: ["+sw_test_timeout_ns=20000000"]
    }

    // TODO: CSR suite of tests. Rather than reuse the common one, we are
    // replicating here since we dont want CSR tests added to the sanity just yet.
    {
      name: chip_csr_hw_reset
      uvm_test_seq: chip_common_vseq
      run_opts: ["+en_scb=0", "+csr_hw_reset"]
      en_run_modes: ["stub_cpu"]
    }

    {
      name: chip_csr_rw
      uvm_test_seq: chip_common_vseq
      run_opts: ["+en_scb=0", "+csr_rw"]
      en_run_modes: ["stub_cpu"]
    }

    {
      name: chip_csr_bit_bash
      uvm_test_seq: chip_common_vseq
      run_opts: ["+en_scb=0", "+csr_bit_bash"]
      en_run_modes: ["stub_cpu"]
    }

    {
      name: chip_csr_aliasing
      uvm_test_seq: chip_common_vseq
      run_opts: ["+en_scb=0", "+csr_aliasing"]
      en_run_modes: ["stub_cpu"]
    }

    {
      name: "chip_same_csr_outstanding"
      uvm_test_seq: chip_common_vseq
      run_opts: ["+en_scb=0", "+run_same_csr_outstanding"]
      en_run_modes: ["stub_cpu"]
    }

    {
      name: chip_tl_errors
      uvm_test_seq: chip_common_vseq
      run_opts: ["+run_tl_errors"]
      en_run_modes: ["stub_cpu"]
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: sanity
      tests: ["chip_sanity"]
    }
    {
      name: sw_access
      tests: ["chip_csr_hw_reset",
              "chip_csr_rw",
              "chip_csr_bit_bash",
              "chip_csr_aliasing"]
    }
  ]
}