tree: 7ca20ed87009b12fef3086398ee05197783f06c7 [path history] [tgz]
  1. env/
  2. tb/
  3. tests/
  4. chip_sim.core
  5. chip_sim_cfg.hjson
  6. Makefile
  7. README.md
  8. top_earlgrey_sim_cfgs.hjson
hw/top_earlgrey/dv/README.md

TOP Earl Grey

How to run simulation

Please run the following command to build and run tests: make TEST_NAME=<test-name>

Please see adjoining Makefile file for list of available tests to run. Please see hw/dv/tools/README.md for additional details on options that can be passed (such as enabling waves, running with specific seed etc.).

Note: Currently, ibex core raises an assertion but it doesn't harm UART TX and GPIO functionalities. Please ignore until it is resolved.