| commit | 4d77215e28c6b62f0feb1af8ec692882fe8ddf1a | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@opentitan.org> | Mon Mar 06 12:52:18 2023 -0800 |
| committer | Cindy Chen <cindy.chen0316@gmail.com> | Wed Mar 08 11:41:58 2023 -0800 |
| tree | 40cbc0f427c9b033829bcee5d8b71d2704ffb10d | |
| parent | 5cbddc36d85756fbe86f2a615717881292405c83 [diff] |
[dv/cip] Fix csr_rw corner cases Due to the async clock config, alert receiver and sender domain can have different clock frequencies. The cip_base_vseq intend to check there is no fatal alert at the end of the simulation, and allow recoverable alert to fire due to alert_test reg. The current wait cycles method does not handle the different clock domain very well. This new method will just wait until the first alert handshake is done. Signed-off-by: Cindy Chen <chencindy@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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