)]}'
{
  "commit": "4d77215e28c6b62f0feb1af8ec692882fe8ddf1a",
  "tree": "40cbc0f427c9b033829bcee5d8b71d2704ffb10d",
  "parents": [
    "5cbddc36d85756fbe86f2a615717881292405c83"
  ],
  "author": {
    "name": "Cindy Chen",
    "email": "chencindy@opentitan.org",
    "time": "Mon Mar 06 12:52:18 2023 -0800"
  },
  "committer": {
    "name": "Cindy Chen",
    "email": "cindy.chen0316@gmail.com",
    "time": "Wed Mar 08 11:41:58 2023 -0800"
  },
  "message": "[dv/cip] Fix csr_rw corner cases\n\nDue to the async clock config, alert receiver and sender domain can have\ndifferent clock frequencies.\nThe cip_base_vseq intend to check there is no fatal alert at the end of\nthe simulation, and allow recoverable alert to fire due to alert_test\nreg.\nThe current wait cycles method does not handle the different clock\ndomain very well. This new method will just wait until the first alert\nhandshake is done.\n\nSigned-off-by: Cindy Chen \u003cchencindy@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6ebf7b84819223e050b988f5f6b199204132e8b6",
      "old_mode": 33188,
      "old_path": "hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv",
      "new_id": "848ad33c9ac946f09052eafc507aec610db2da9c",
      "new_mode": 33188,
      "new_path": "hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv"
    }
  ]
}