tree 40cbc0f427c9b033829bcee5d8b71d2704ffb10d
parent 5cbddc36d85756fbe86f2a615717881292405c83
author Cindy Chen <chencindy@opentitan.org> 1678135938 -0800
committer Cindy Chen <cindy.chen0316@gmail.com> 1678304518 -0800

[dv/cip] Fix csr_rw corner cases

Due to the async clock config, alert receiver and sender domain can have
different clock frequencies.
The cip_base_vseq intend to check there is no fatal alert at the end of
the simulation, and allow recoverable alert to fire due to alert_test
reg.
The current wait cycles method does not handle the different clock
domain very well. This new method will just wait until the first alert
handshake is done.

Signed-off-by: Cindy Chen <chencindy@opentitan.org>