commit 12ff857147a47d00362151bb2da29bfda6b20ac3
author Cindy Liu <hcindyl@google.com> Wed Feb 16 20:08:34 2022 -0800
committer Cindy Liu <hcindyl@google.com> Wed Feb 16 20:08:34 2022 -0800
tree f61e393b7c78a2254a4c6d4980ec14909f8d1c85
parent f116160714be10db5430c20fbb523719bcc157bc

sw:vec_iree: Use vze32x to define elen max

Per LLVM RISCV contributor discussion, the flag
-riscv-v-fixed-length-vector-elen-max will be retired and use vze32x to
define the maximum element length.

Change-Id: Id495dbb5b90d7128056679938d01c57e946aafa5

samples/float_model/CMakeLists.txt

diff --git a/samples/float_model/CMakeLists.txt b/samples/float_model/CMakeLists.txt
index 3ada748..f921a2e 100644
--- a/samples/float_model/CMakeLists.txt
+++ b/samples/float_model/CMakeLists.txt
@@ -1,5 +1,5 @@
 #-------------------------------------------------------------------------------
-# Build the mlir bytecode modules with iree-translate. Note the last three flags
+# Build the mlir bytecode modules with iree-translate. Note the last two flags
 # are for RVV support.
 #-------------------------------------------------------------------------------
 
@@ -14,7 +14,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   RVV_OFF
   PUBLIC
 )
@@ -30,7 +29,6 @@
     "-iree-input-type=mhlo"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   RVV_OFF
   PUBLIC
 )

samples/quant_model/CMakeLists.txt

diff --git a/samples/quant_model/CMakeLists.txt b/samples/quant_model/CMakeLists.txt
index 9675f1d..c0ed7c3 100644
--- a/samples/quant_model/CMakeLists.txt
+++ b/samples/quant_model/CMakeLists.txt
@@ -1,5 +1,5 @@
 #-------------------------------------------------------------------------------
-# Build the mlir bytecode modules with iree-translate. Note the last three flags
+# Build the mlir bytecode modules with iree-translate. Note the last two flags
 # are for RVV support.
 #-------------------------------------------------------------------------------
 
@@ -14,7 +14,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -29,7 +28,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -44,7 +42,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -61,7 +58,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -76,7 +72,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -91,7 +86,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -106,7 +100,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -121,7 +114,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -136,7 +128,6 @@
     "-iree-input-type=tosa"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 

samples/simple_vec_mul/CMakeLists.txt

diff --git a/samples/simple_vec_mul/CMakeLists.txt b/samples/simple_vec_mul/CMakeLists.txt
index 0b5ff77..661032a 100644
--- a/samples/simple_vec_mul/CMakeLists.txt
+++ b/samples/simple_vec_mul/CMakeLists.txt
@@ -1,5 +1,5 @@
 #-------------------------------------------------------------------------------
-# Build the mlir bytecode modules with iree-translate. Note the last three flags
+# Build the mlir bytecode modules with iree-translate. Note the last two flags
 # are for RVV support.
 # https://github.com/llvm/llvm-project/blob/0eeab8b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp#L30-L51
 #-------------------------------------------------------------------------------
@@ -15,7 +15,6 @@
     "-iree-input-type=mhlo"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )
 
@@ -30,7 +29,6 @@
     "-iree-input-type=mhlo"
     "-riscv-v-vector-bits-min=512"
     "-riscv-v-fixed-length-vector-lmul-max=8"
-    "-riscv-v-fixed-length-vector-elen-max=32"
   PUBLIC
 )