hal/src/smc_ctrl_hal.rs

// Generated register constants for smc_ctrl.
// This file is licensed under either of:
//   Apache License, Version 2.0 (LICENSE-APACHE <http://www.apache.org/licenses/LICENSE-2.0>)
//   MIT License (LICENSE-MIT <http://opensource.org/licenses/MIT>)

// Build date: 2023-02-22T01:20:33.682585

// Original reference file: hw/matcha/hw/top_matcha/ip/smc_ctrl/data/smc_ctrl.hjson
use kernel::common::registers::{
    register_bitfields, register_structs, ReadWrite
};
use kernel::common::StaticRef;
// Register width
pub const SMC_CTRL_PARAM_REG_WIDTH: u32 = 32;

pub const SMC_CTRL_REGISTERS: StaticRef<SmcCtrlRegisters> =
    unsafe { StaticRef::new(matcha_config::SMC_CTRL_BASE_ADDRESS as *const SmcCtrlRegisters) };
pub static mut SMC_CTRL: SmcCtrl = SmcCtrl::new(SMC_CTRL_REGISTERS /*, matcha_config::CHIP_PERIPH_FREQ*/);

register_structs! {
    pub SmcCtrlRegisters {
        // Register write enable for software controllable boot enable.
        (0x0000 => pub(crate) smc_boot_en_regwen: ReadWrite<u32, SMC_BOOT_EN_REGWEN::Register>),
        // Software controllable boot enable.
        (0x0004 => pub(crate) smc_boot_en_ctrl: ReadWrite<u32, SMC_BOOT_EN_CTRL::Register>),
        (0x0008 => @END),
    }
}

register_bitfields![u32,
    pub(crate) SMC_BOOT_EN_REGWEN [
        REGWEN OFFSET(0) NUMBITS(1) []
    ],
    pub(crate) SMC_BOOT_EN_CTRL [
        EN_CTRL OFFSET(0) NUMBITS(1) []
    ]
];

// End generated register constants for smc_ctrl

pub struct SmcCtrl {
    registers: StaticRef<SmcCtrlRegisters>,
}

pub trait SmcCtrlHal {
    fn smc_ctrl_start(&self);
}

impl SmcCtrl {
    pub const fn new(base: StaticRef<SmcCtrlRegisters>) -> SmcCtrl {
        SmcCtrl {
            registers: base,
        }
    }
}

impl SmcCtrlHal for SmcCtrl {
    fn smc_ctrl_start(&self) {
        self.registers.smc_boot_en_ctrl.modify(SMC_BOOT_EN_CTRL::EN_CTRL::SET);
    }
}