| //! Named interrupts for the Matcha chip. |
| |
| #![allow(dead_code)] |
| |
| pub const PWRMGRWAKEUP: u32 = 0x50; |
| |
| pub const NO_INTERRUPT: u32 = 0; |
| |
| pub const UART0_TX_WATERMARK: u32 = 1; |
| pub const UART0_RX_WATERMARK: u32 = 2; |
| pub const UART0_TX_EMPTY: u32 = 3; |
| pub const UART0_RX_OVERFLOW: u32 = 4; |
| pub const UART0_RX_FRAME_ERR: u32 = 5; |
| pub const UART0_RX_BREAK_ERR: u32 = 6; |
| pub const UART0_RX_TIMEOUT: u32 = 7; |
| pub const UART0_RX_PARITY_ERR: u32 = 8; |
| |
| pub const UART1_TX_WATERMARK: u32 = 9; |
| pub const UART1_RX_WATERMARK: u32 = 10; |
| pub const UART1_TX_EMPTY: u32 = 11; |
| pub const UART1_RX_OVERFLOW: u32 = 12; |
| pub const UART1_RX_FRAME_ERR: u32 = 13; |
| pub const UART1_RX_BREAK_ERR: u32 = 14; |
| pub const UART1_RX_TIMEOUT: u32 = 15; |
| pub const UART1_RX_PARITY_ERR: u32 = 16; |
| |
| pub const UART2_TX_WATERMARK: u32 = 17; |
| pub const UART2_RX_WATERMARK: u32 = 18; |
| pub const UART2_TX_EMPTY: u32 = 19; |
| pub const UART2_RX_OVERFLOW: u32 = 20; |
| pub const UART2_RX_FRAME_ERR: u32 = 21; |
| pub const UART2_RX_BREAK_ERR: u32 = 22; |
| pub const UART2_RX_TIMEOUT: u32 = 23; |
| pub const UART2_RX_PARITY_ERR: u32 = 24; |
| |
| pub const UART3_TX_WATERMARK: u32 = 25; |
| pub const UART3_RX_WATERMARK: u32 = 26; |
| pub const UART3_TX_EMPTY: u32 = 27; |
| pub const UART3_RX_OVERFLOW: u32 = 28; |
| pub const UART3_RX_FRAME_ERR: u32 = 29; |
| pub const UART3_RX_BREAK_ERR: u32 = 30; |
| pub const UART3_RX_TIMEOUT: u32 = 31; |
| pub const UART3_RX_PARITY_ERR: u32 = 32; |
| |
| pub const GPIO_PIN0: u32 = 33; |
| pub const GPIO_PIN1: u32 = 34; |
| pub const GPIO_PIN2: u32 = 35; |
| pub const GPIO_PIN3: u32 = 36; |
| pub const GPIO_PIN4: u32 = 37; |
| pub const GPIO_PIN5: u32 = 38; |
| pub const GPIO_PIN6: u32 = 39; |
| pub const GPIO_PIN7: u32 = 40; |
| pub const GPIO_PIN8: u32 = 41; |
| pub const GPIO_PIN9: u32 = 42; |
| pub const GPIO_PIN10: u32 = 43; |
| pub const GPIO_PIN11: u32 = 44; |
| pub const GPIO_PIN12: u32 = 45; |
| pub const GPIO_PIN13: u32 = 46; |
| pub const GPIO_PIN14: u32 = 47; |
| pub const GPIO_PIN15: u32 = 48; |
| pub const GPIO_PIN16: u32 = 49; |
| pub const GPIO_PIN17: u32 = 50; |
| pub const GPIO_PIN18: u32 = 51; |
| pub const GPIO_PIN19: u32 = 52; |
| pub const GPIO_PIN20: u32 = 53; |
| pub const GPIO_PIN21: u32 = 54; |
| pub const GPIO_PIN22: u32 = 55; |
| pub const GPIO_PIN23: u32 = 56; |
| pub const GPIO_PIN24: u32 = 57; |
| pub const GPIO_PIN25: u32 = 58; |
| pub const GPIO_PIN26: u32 = 59; |
| pub const GPIO_PIN27: u32 = 60; |
| pub const GPIO_PIN28: u32 = 61; |
| pub const GPIO_PIN29: u32 = 62; |
| pub const GPIO_PIN30: u32 = 63; |
| pub const GPIO_PIN31: u32 = 64; |
| |
| pub const SPI_DEVICE_RXF: u32 = 65; |
| pub const SPI_DEVICE_RXLVL: u32 = 66; |
| pub const SPI_DEVICE_TXLVL: u32 = 67; |
| pub const SPI_DEVICE_RXERR: u32 = 68; |
| pub const SPI_DEVICE_RXOVERFLOW: u32 = 69; |
| pub const SPI_DEVICE_TXUNDERFLOW: u32 = 70; |
| |
| |
| pub const SPI_HOST0_ERROR: u32 = 71; |
| pub const SPI_HOST0_SPIEVENT: u32 = 72; |
| pub const SPI_HOST1_ERROR: u32 = 73; |
| pub const SPI_HOST1_SPIEVENT: u32 = 74; |
| |
| pub const I2C0_FMT_WATERMARK: u32 = 75; |
| pub const I2C0_RX_WATERMARK: u32 = 76; |
| pub const I2C0_FMT_OVERFLOW: u32 = 77; |
| pub const I2C0_RX_OVERFLOW: u32 = 78; |
| pub const I2C0_NAK: u32 = 79; |
| pub const I2C0_SCL_INTERFERENCE: u32 = 80; |
| pub const I2C0_SDA_INTERFERENCE: u32 = 81; |
| pub const I2C0_STRETCH_TIMEOUT: u32 = 82; |
| pub const I2C0_SDA_UNSTABLE: u32 = 83; |
| pub const I2C0_TRANS_COMPLETE: u32 = 84; |
| pub const I2C0_TX_EMPTY: u32 = 85; |
| pub const I2C0_TX_NONEMPTY: u32 = 86; |
| pub const I2C0_TX_OVERFLOW: u32 = 87; |
| pub const I2C0_ACQ_OVERFLOW: u32 = 88; |
| pub const I2C0_ACK_STOP: u32 = 89; |
| pub const I2C0_HOST_TIMEOUT: u32 = 90; |
| |
| pub const I2C1_FMT_WATERMARK: u32 = 91; |
| pub const I2C1_RX_WATERMARK: u32 = 92; |
| pub const I2C1_FMT_OVERFLOW: u32 = 93; |
| pub const I2C1_RX_OVERFLOW: u32 = 94; |
| pub const I2C1_NAK: u32 = 95; |
| pub const I2C1_SCL_INTERFERENCE: u32 = 96; |
| pub const I2C1_SDA_INTERFERENCE: u32 = 97; |
| pub const I2C1_STRETCH_TIMEOUT: u32 = 98; |
| pub const I2C1_SDA_UNSTABLE: u32 = 99; |
| pub const I2C1_TRANS_COMPLETE: u32 = 100; |
| pub const I2C1_TX_EMPTY: u32 = 101; |
| pub const I2C1_TX_NONEMPTY: u32 = 102; |
| pub const I2C1_TX_OVERFLOW: u32 = 103; |
| pub const I2C1_ACQ_OVERFLOW: u32 = 104; |
| pub const I2C1_ACK_STOP: u32 = 105; |
| pub const I2C1_HOST_TIMEOUT: u32 = 106; |
| |
| pub const I2C2_FMT_WATERMARK: u32 = 107; |
| pub const I2C2_RX_WATERMARK: u32 = 108; |
| pub const I2C2_FMT_OVERFLOW: u32 = 109; |
| pub const I2C2_RX_OVERFLOW: u32 = 110; |
| pub const I2C2_NAK: u32 = 111; |
| pub const I2C2_SCL_INTERFERENCE: u32 = 112; |
| pub const I2C2_SDA_INTERFERENCE: u32 = 113; |
| pub const I2C2_STRETCH_TIMEOUT: u32 = 114; |
| pub const I2C2_SDA_UNSTABLE: u32 = 115; |
| pub const I2C2_TRANS_COMPLETE: u32 = 116; |
| pub const I2C2_TX_EMPTY: u32 = 117; |
| pub const I2C2_TX_NONEMPTY: u32 = 118; |
| pub const I2C2_TX_OVERFLOW: u32 = 119; |
| pub const I2C2_ACQ_OVERFLOW: u32 = 120; |
| pub const I2C2_ACK_STOP: u32 = 121; |
| pub const I2C2_HOST_TIMEOUT: u32 = 122; |
| |
| pub const PATTGEN_DONE_CH0: u32 = 123; |
| pub const PATTGEN_DONE_CH1: u32 = 124; |
| |
| pub const RV_TIMER_EXPIRED0_0: u32 = 125; |
| |
| pub const USBDEV_PKT_RECEIVED: u32 = 126; |
| pub const USBDEV_PKT_SENT: u32 = 127; |
| pub const USBDEV_DISCONNECTED: u32 = 128; |
| pub const USBDEV_HOST_LOST: u32 = 129; |
| pub const USBDEV_LINK_RESET: u32 = 130; |
| pub const USBDEV_LINK_SUSPEND: u32 = 131; |
| pub const USBDEV_LINK_RESUME: u32 = 132; |
| pub const USBDEV_AV_EMPTY: u32 = 133; |
| pub const USBDEV_RX_FULL: u32 = 134; |
| pub const USBDEV_AV_OVERFLOW: u32 = 135; |
| pub const USBDEV_LINK_IN_ERR: u32 = 136; |
| pub const USBDEV_RX_CRC_ERR: u32 = 137; |
| pub const USBDEV_RX_PID_ERR: u32 = 138; |
| pub const USBDEV_RX_BITSTUFF_ERR: u32 = 139; |
| pub const USBDEV_FRAME: u32 = 140; |
| pub const USBDEV_CONNECTED: u32 = 141; |
| pub const USBDEV_LINK_OUT_ERR: u32 = 142; |
| |
| pub const OTP_CTRL_OTP_OPERATION_DONE: u32 = 143; |
| pub const OTP_CTRL_OTP_ERR: u32 = 144; |
| |
| pub const ALERT_CLASSA: u32 = 145; |
| pub const ALERT_CLASSB: u32 = 146; |
| pub const ALERT_CLASSC: u32 = 147; |
| pub const ALERT_CLASSD: u32 = 148; |
| |
| pub const PWRMGR_AON_WAKEUP: u32 = 149; |
| |
| pub const ADC_CTRL_AON_DEBUG_CABLE: u32 = 150; |
| |
| pub const AON_TIMER_AON_WAKEUP_TIMER_EXPIRED: u32 = 151; |
| pub const AON_TIMER_AON_WATCHDOG_EXPIRED: u32 = 152; |
| |
| pub const FLASH_PROG_EMPTY: u32 = 153; |
| pub const FLASH_PROG_LVL: u32 = 154; |
| pub const FLASH_RD_FULL: u32 = 155; |
| pub const FLASH_RD_LVL: u32 = 156; |
| pub const FLASH_OP_DONE: u32 = 157; |
| |
| pub const HMAC_HMAC_DONE: u32 = 158; |
| pub const HMAC_FIFO_EMPTY: u32 = 159; |
| pub const HMAC_HMAC_ERR: u32 = 160; |
| |
| pub const KMAC_KMAC_DONE: u32 = 161; |
| pub const KMAC_FIFO_EMPTY: u32 = 162; |
| pub const KMAC_KMAC_ERR: u32 = 163; |
| |
| pub const KEYMGR_OP_DONE: u32 = 164; |
| |
| pub const CSRNG_CS_CMD_REQ_DONE: u32 = 165; |
| pub const CSRNG_CS_ENTROPY_REQ: u32 = 166; |
| pub const CSRNG_CS_HW_INST_EXC: u32 = 167; |
| pub const CSRNG_CS_FATAL_ERR: u32 = 168; |
| pub const ENTROPY_SRC_ES_ENTROPY_VALID: u32 = 169; |
| pub const ENTROPY_SRC_ES_HEALTH_TEST_FAILED: u32 = 170; |
| pub const ENTROPY_SRC_ES_FATAL_ERR: u32 = 171; |
| |
| pub const EDN0_EDN_CMD_REQ_DONE: u32 = 172; |
| pub const EDN0_EDN_FATAL_ERR: u32 = 173; |
| |
| pub const EDN1_EDN_CMD_REQ_DONE: u32 = 174; |
| pub const EDN1_EDN_FATAL_ERR: u32 = 175; |
| |
| pub const OTBN_DONE: u32 = 176; |
